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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id g28sm132656016pfd.100.2019.01.10.04.49.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:49:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vc880LwbgUgrvinaZJ29rDm6AdQgGipIK6nkHZKqFT4=; b=NHiI4Su6RveQDiMLHanz/4Y6KYUcDFnfSEJ93u90avaY703CH4Vq5okR0ORJMP5C63 f/c2ppZatJZZUA2wPriDVB3zg+tIBwz+XkYYjFuBgnD0KKp7mW4eZrn1b/DeyORa82fN q6WG2MJtP//SAz4OFw5JDWjoISQv+jbwESK64= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vc880LwbgUgrvinaZJ29rDm6AdQgGipIK6nkHZKqFT4=; b=Aoctira/wXcw/USQN4lR7QI31fQnr2UpIqySENOq/YpgVRGX5nd85oVz5oSj9rZSR/ FPpc2XCKf4hUNLd4Wud7tLrkK+hhohNNQhEq2amNeUYpZyrYZyT1brRauYcKK9UBIbzv gNXiQB1fMe1hGN5qDAVwWCDb/ljNZaH6He6HlAxJsGFKglbSC/FP5+SsMaXkCA/sdaOX +gJHCw+NvfXEj2OUYGTLQivv0ItpSOyhu6QAY0f/QDvIEv9E5zUaZ9IC+HIUfwx4TwZc q3yp3xPk4s+QQlITTWhRFlxK4eAL3OoVr0cUB3LXVY3PbV9gvz1WnpWU18nn9Nkvt59q wEUw== X-Gm-Message-State: AJcUukccGoekZNN/j4y3jWvhjwIGrUFa7Y6RlTKa9f8GupI1Iy85OO/o MVQ0JfgsIpcdtJVawP9dTApm9LR3hQ1ISw== X-Google-Smtp-Source: ALg8bN5uh3qxOIPvQ7nRmIFPypdOrHuktVXBsFcWcQmgtBn3KizYsOJWWn5U/IZQONwukCsovU4olA== X-Received: by 2002:a63:7044:: with SMTP id a4mr9084621pgn.359.1547124600044; Thu, 10 Jan 2019 04:50:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:49:48 +1100 Message-Id: <20190110124951.15473-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110124951.15473-1-richard.henderson@linaro.org> References: <20190110124951.15473-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 1/4] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Split out gen_top_byte_ignore in preparation of handling these data accesses; the new tbflags field is not yet honored. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/translate.h | 3 ++- target/arm/helper.c | 1 + target/arm/translate-a64.c | 40 +++++++++++++++++--------------------- 4 files changed, 22 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 929f16dd6b..02e6dcce25 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2996,6 +2996,7 @@ FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, TBID, 12, 2) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index f73939d7b4..17748ddfb9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,7 +26,8 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for insns */ + uint8_t tbid; /* TBI1|TBI0 for data */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4e9ea2ed39..8c28c6d044 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13108,6 +13108,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f225517077..9548252782 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -284,31 +284,17 @@ void gen_a64_set_pc_im(uint64_t val) tcg_gen_movi_i64(cpu_pc, val); } =20 -/* Load the PC from a generic TCG variable. - * - * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in it: - * + for EL2 and EL3 there is only one TBI bit, and if it is set - * then the address is zero-extended, clearing bits [63:56] - * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 - * and TBI1 controls addressses with bit 55 =3D=3D 1. - * If the appropriate TBI bit is set for the address then - * the address is sign-extended from bit 55 into bits [63:56] - * - * We can avoid doing this for relative-branches, because the - * PC + offset can never overflow into the tag bits (assuming - * that virtual addresses are less than 56 bits wide, as they - * are currently), but we must handle it for branch-to-register. +/* + * Handle Top Byte Ignore (TBI) bits. + * We have concatenated tbi{1,0} into tbi. */ -static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, + TCGv_i64 src, int tbi) { - /* Note that TBII is TBI1:TBI0. */ - int tbi =3D s->tbii; - if (s->current_el <=3D 1) { if (tbi !=3D 0) { /* Sign-extend from bit 55. */ - tcg_gen_sextract_i64(cpu_pc, src, 0, 56); + tcg_gen_sextract_i64(dst, src, 0, 56); =20 if (tbi !=3D 3) { TCGv_i64 tcg_zero =3D tcg_const_i64(0); @@ -327,13 +313,22 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) } else { if (tbi !=3D 0) { /* Force tag byte to all zero */ - tcg_gen_extract_i64(cpu_pc, src, 0, 56); + tcg_gen_extract_i64(dst, src, 0, 56); return; } } =20 /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_mov_i64(dst, src); +} + +static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +{ + /* + * If address tagging is enabled for instructions via the TCR TBI bits, + * then loading an address into the PC will clear out any tag. + */ + gen_top_byte_ignore(s, cpu_pc, src, s->tbii); } =20 typedef struct DisasCompare64 { @@ -13981,6 +13976,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); + dc->tbid =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBID); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); --=20 2.17.2 From nobody Fri Mar 29 09:47:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547124908465246.70901640429736; Thu, 10 Jan 2019 04:55:08 -0800 (PST) Received: from localhost ([127.0.0.1]:37708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZrW-0007kc-SX for importer@patchew.org; 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id g28sm132656016pfd.100.2019.01.10.04.50.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:50:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aiq7cociCao/2bYT3GZsZhijKGK9KJST01JsHggxgBs=; b=bmnGkA2IWuo6tc2WJ/JLKah7O9xRTmiLBVzRPAg4qk77OC2lYy1AROX9krdXyFCFM3 FnTJR+wGjJ+n0OUByzLUqvwv5mHsPuLzl5pjxbs+W9KdxzOJpLfkjYdhSu+XZ0pJhbLB sOd3a7nbO7S8Z8eZjpCFFZlDu3IGJUedhJtFI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aiq7cociCao/2bYT3GZsZhijKGK9KJST01JsHggxgBs=; b=SBAycaiE/XKj7krZGyKw4/6rweoWAsk8V+FJ5EsOalqxQl4FPO2s6Z5lQ8Wd8PN/Ey D75BQtviN6S7NcGlh/jIRcWNUdGgmmq7Ebd9uhg55jQC3yR6lo61k3pV5WLfedQDIIX8 AkYe3jDbR/WvYtiEmjNoLErHeTDKfGBL0M8NBwD5nUmMc7eXJIlJaGPjbyrYY1t2yNxX 8osTYAtj//Umsar/FVTBludmFVSyjpH4w+XfDn9ojcn22WkCLoOr64h3sN2Iwp3ZQYuP VNs6UnHXCWHBXglc946JeJs4u72b5eZzfS1gtcgJtcnCf14up+UtSqkpaNiOy4hCpgB8 8dOA== X-Gm-Message-State: AJcUukeXEifDDV2RtUEX69Wk1RnSlROKhX1kls2Inf1ciabBMcrlIsqz WRpaRDfDlvFxQYjrh2IAatMCgDGcKyB9EQ== X-Google-Smtp-Source: ALg8bN4aZZ6M33cm6pNaZ0xc+RAwGW5t66LtmAGuBb4MYG+WZepALWtRGkrzojkit4ZXcALmaWjphA== X-Received: by 2002:a17:902:850c:: with SMTP id bj12mr10043939plb.46.1547124602732; Thu, 10 Jan 2019 04:50:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:49:49 +1100 Message-Id: <20190110124951.15473-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110124951.15473-1-richard.henderson@linaro.org> References: <20190110124951.15473-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Clean TBI for data operations in the translator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will allow TBI to be used in user-only mode, as well as avoid ping-ponging the softmmu TLB when TBI is in use. It will also enable other armv8 extensions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 217 ++++++++++++++++++++----------------- 1 file changed, 116 insertions(+), 101 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9548252782..1d9e204884 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -331,6 +331,18 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 s= rc) gen_top_byte_ignore(s, cpu_pc, src, s->tbii); } =20 +/* + * Return a "clean" address for ADDR according to TBID. + * This is always a fresh temporary, as we need to be able to + * increment this independently of a dirty write-back address. + */ +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +{ + TCGv_i64 clean =3D new_tmp_a64(s); + gen_top_byte_ignore(s, clean, addr, s->tbid); + return clean; +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2342,12 +2354,13 @@ static void gen_compare_and_swap(DisasContext *s, i= nt rs, int rt, TCGv_i64 tcg_rs =3D cpu_reg(s, rs); TCGv_i64 tcg_rt =3D cpu_reg(s, rt); int memidx =3D get_mem_index(s); - TCGv_i64 addr =3D cpu_reg_sp(s, rn); + TCGv_i64 clean_addr; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_gen_atomic_cmpxchg_i64(tcg_rs, addr, tcg_rs, tcg_rt, memidx, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } =20 @@ -2358,12 +2371,13 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 s2 =3D cpu_reg(s, rs + 1); TCGv_i64 t1 =3D cpu_reg(s, rt); TCGv_i64 t2 =3D cpu_reg(s, rt + 1); - TCGv_i64 addr =3D cpu_reg_sp(s, rn); + TCGv_i64 clean_addr; int memidx =3D get_mem_index(s); =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2377,7 +2391,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat32_i64(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i64(cmp, addr, cmp, val, memidx, + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, MO_64 | MO_ALIGN | s->be_data); tcg_temp_free_i64(val); =20 @@ -2391,9 +2405,11 @@ static void gen_compare_and_swap_pair(DisasContext *= s, int rs, int rt, if (HAVE_CMPXCHG128) { TCGv_i32 tcg_rs =3D tcg_const_i32(rs); if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_casp_le_parallel(cpu_env, tcg_rs, + clean_addr, t1, t2); } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_casp_be_parallel(cpu_env, tcg_rs, + clean_addr, t1, t2); } tcg_temp_free_i32(tcg_rs); } else { @@ -2409,10 +2425,10 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 zero =3D tcg_const_i64(0); =20 /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, addr, memidx, + tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, addr, 8); - tcg_gen_qemu_ld_i64(d2, addr, memidx, MO_64 | s->be_data); + tcg_gen_addi_i64(a2, clean_addr, 8); + tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); =20 /* Compare the two words, also in memory order. */ tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); @@ -2422,7 +2438,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, /* If compare equal, write back new data, else write back old data= . */ tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, addr, memidx, MO_64 | s->be_data); + tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); tcg_temp_free_i64(a2); tcg_temp_free_i64(c1); @@ -2475,7 +2491,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) int is_lasr =3D extract32(insn, 15, 1); int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr; =20 switch (o2_L_o1_o0) { case 0x0: /* STXR */ @@ -2486,8 +2502,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, false); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 case 0x4: /* LDXR */ @@ -2495,9 +2511,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, tcg_addr, size, false); + gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2515,8 +2531,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - do_gpr_st(s, cpu_reg(s, rt), tcg_addr, size, true, rt, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2531,8 +2547,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - do_gpr_ld(s, cpu_reg(s, rt), tcg_addr, size, false, false, true, r= t, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2545,8 +2561,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, true); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } if (rt2 =3D=3D 31 @@ -2563,9 +2579,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, tcg_addr, size, true); + gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2614,7 +2630,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) int opc =3D extract32(insn, 30, 2); bool is_signed =3D false; int size =3D 2; - TCGv_i64 tcg_rt, tcg_addr; + TCGv_i64 tcg_rt, clean_addr; =20 if (is_vector) { if (opc =3D=3D 3) { @@ -2636,17 +2652,17 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - tcg_addr =3D tcg_const_i64((s->pc - 4) + imm); + clean_addr =3D tcg_const_i64((s->pc - 4) + imm); if (is_vector) { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; =20 - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, true, rt, iss_sf, false); } - tcg_temp_free_i64(tcg_addr); + tcg_temp_free_i64(clean_addr); } =20 /* @@ -2692,7 +2708,8 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) bool postindex =3D false; bool wback =3D false; =20 - TCGv_i64 tcg_addr; /* calculated address */ + TCGv_i64 clean_addr, dirty_addr; + int size; =20 if (opc =3D=3D 3) { @@ -2748,23 +2765,23 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) gen_check_sp_alignment(s); } =20 - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); if (!postindex) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_load) { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } else { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); if (is_load) { - do_fp_ld(s, rt2, tcg_addr, size); + do_fp_ld(s, rt2, clean_addr, size); } else { - do_fp_st(s, rt2, tcg_addr, size); + do_fp_st(s, rt2, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -2776,30 +2793,28 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) /* Do not modify tcg_rt before recognizing any exception * from the second load. */ - do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false, + do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, false, 0, false, false); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); + do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, false, 0, false, false); =20 tcg_gen_mov_i64(tcg_rt, tmp); tcg_temp_free_i64(tmp); } else { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, false, 0, false, false); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - do_gpr_st(s, tcg_rt2, tcg_addr, size, + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); + do_gpr_st(s, tcg_rt2, clean_addr, size, false, 0, false, false); } } =20 if (wback) { if (postindex) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); - } else { - tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); } } =20 @@ -2836,7 +2851,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool post_index; bool writeback; =20 - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr, dirty_addr; =20 if (is_vector) { size |=3D (opc & 2) << 1; @@ -2887,17 +2902,18 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); =20 + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); if (!post_index) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -2905,10 +2921,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { - do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, + do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, is_signed, is_extended, memidx, iss_valid, rt, iss_sf, false); } @@ -2917,9 +2933,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (writeback) { TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); if (post_index) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_mov_i64(tcg_rn, dirty_addr); } } =20 @@ -2958,8 +2974,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, bool is_store =3D false; bool is_extended =3D false; =20 - TCGv_i64 tcg_rm; - TCGv_i64 tcg_addr; + TCGv_i64 tcg_rm, clean_addr, dirty_addr; =20 if (extract32(opt, 1, 1) =3D=3D 0) { unallocated_encoding(s); @@ -2993,27 +3008,28 @@ static void disas_ldst_reg_roffset(DisasContext *s,= uint32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); =20 tcg_rm =3D read_cpu_reg(s, rm, 1); ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); + tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, tcg_addr, size, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, true, rt, iss_sf, false); } @@ -3047,7 +3063,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, unsigned int imm12 =3D extract32(insn, 10, 12); unsigned int offset; =20 - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr, dirty_addr; =20 bool is_store; bool is_signed =3D false; @@ -3080,24 +3096,25 @@ static void disas_ldst_reg_unsigned_imm(DisasContex= t *s, uint32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, true, rt, iss_sf, false); } } @@ -3123,7 +3140,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int rs =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); - TCGv_i64 tcg_rn, tcg_rs; + TCGv_i64 tcg_rs, clean_addr; AtomicThreeOpFn *fn; =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { @@ -3166,7 +3183,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_rn =3D cpu_reg_sp(s, rn); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ @@ -3176,7 +3193,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, /* The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ - fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), + fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), s->be_data | size | MO_ALIGN); } =20 @@ -3201,7 +3218,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, bool is_wback =3D extract32(insn, 11, 1); bool use_key_a =3D !extract32(insn, 23, 1); int offset; - TCGv_i64 tcg_addr, tcg_rt; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; =20 if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { unallocated_encoding(s); @@ -3211,29 +3228,31 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); =20 if (s->pauth_active) { if (use_key_a) { - gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); } else { - gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); } } =20 /* Form the 10-bit signed, scaled offset. */ offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 tcg_rt =3D cpu_reg(s, rt); - - do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, + do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); } } =20 @@ -3301,7 +3320,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) bool is_store =3D !extract32(insn, 22, 1); bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; TCGMemOp endian =3D s->be_data; =20 int ebytes; /* bytes per element */ @@ -3379,8 +3398,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) elements =3D (is_q ? 16 : 8) / ebytes; =20 tcg_rn =3D cpu_reg_sp(s, rn); - tcg_addr =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tcg_addr, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (r =3D 0; r < rpt; r++) { @@ -3390,14 +3408,15 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) for (xs =3D 0; xs < selem; xs++) { int tt =3D (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, tcg_addr, size, endian); + do_vec_st(s, tt, e, clean_addr, size, endian); } else { - do_vec_ld(s, tt, e, tcg_addr, size, endian); + do_vec_ld(s, tt, e, clean_addr, size, endian); } - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } } } + tcg_temp_free_i64(tcg_ebytes); =20 if (!is_store) { /* For non-quad operations, setting a slice of the low @@ -3416,13 +3435,11 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) if (is_postidx) { int rm =3D extract32(insn, 16, 5); if (rm =3D=3D 31) { - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebyt= es); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } - tcg_temp_free_i64(tcg_ebytes); - tcg_temp_free_i64(tcg_addr); } =20 /* AdvSIMD load/store single structure @@ -3464,7 +3481,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) bool replicate =3D false; int index =3D is_q << 3 | S << 2 | size; int ebytes, xs; - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; =20 switch (scale) { case 3: @@ -3515,8 +3532,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } =20 tcg_rn =3D cpu_reg_sp(s, rn); - tcg_addr =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tcg_addr, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (xs =3D 0; xs < selem; xs++) { @@ -3524,7 +3540,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) /* Load and replicate to all elements */ TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), s->be_data + scale); tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), @@ -3533,25 +3549,24 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data); + do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); } else { - do_vec_st(s, rt, index, tcg_addr, scale, s->be_data); + do_vec_st(s, rt, index, clean_addr, scale, s->be_data); } } - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); rt =3D (rt + 1) % 32; } + tcg_temp_free_i64(tcg_ebytes); =20 if (is_postidx) { int rm =3D extract32(insn, 16, 5); if (rm =3D=3D 31) { - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } - tcg_temp_free_i64(tcg_ebytes); - tcg_temp_free_i64(tcg_addr); } =20 /* Loads and stores */ --=20 2.17.2 From nobody Fri Mar 29 09:47:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547124904618371.8669081621739; Thu, 10 Jan 2019 04:55:04 -0800 (PST) Received: from localhost ([127.0.0.1]:37692 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZrT-0007iO-0o for importer@patchew.org; Thu, 10 Jan 2019 07:55:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZmh-0003Q4-ST for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ghZmh-0007Bs-1z for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:07 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:41149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ghZmg-00079z-Sc for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:06 -0500 Received: by mail-pf1-x444.google.com with SMTP id b7so5263526pfi.8 for ; Thu, 10 Jan 2019 04:50:06 -0800 (PST) Received: from cloudburst.twiddle.net (c220-239-117-135.belrs4.nsw.optusnet.com.au. [220.239.117.135]) by smtp.gmail.com with ESMTPSA id g28sm132656016pfd.100.2019.01.10.04.50.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lgpz8q+muFznxKLaWMgdH+QvhIvbcK4cjoZjSmcuDjg=; b=Uid/lklzKYYOiyR5eu4jRLu3OhCiA1mZLad+uRRHymK+MjTO8DluOYwhYf2RtypCIg bsFwJNHEpMkSERXwNegxN/1CmiGqmcUvmpoTvEZrcCyyA3Fmqur/xVNPlx0wQLuzGvrH kqBvygISLCZeey5lPk/xpoKJdMgaaqPfTBCdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lgpz8q+muFznxKLaWMgdH+QvhIvbcK4cjoZjSmcuDjg=; b=IyOGkUeCTlvd37XwWcBJ0iJ4fftvaV1/A4eIirfmseSo3O5oytC6+wtr0ti6w4z/7V W/bmSxiTMt7CLglzVIHiXcTuOJZXALrWYP70L6wGh2ZI6VtlsOs5ao7kmNKv8jS1ZTmQ SZGLGWGncweHoWqY4/laOoZvcC84jrXqKYFMmMQs5BH5XA6frbu6O3rvoMFYVZzeVLhJ GRR+RMCQcZn0aN0d+JOZmXLo71/B0I4KNle28AaTC4DMeIVePVil13kbAXbGaI/VMRsR V83AU6xvEv7yXjyvzNBXHr2v0+zTCXv+tYhn11/whfUl9e8JtksAWB/9pIJPvcGHvaN9 3jPA== X-Gm-Message-State: AJcUukekDqCiLP5zdBJCUsnALUxvQBfXOlyVKEdvLogLImeYcnNka5AG mSESdR1Ql5vyBxIJaWrLUP5MhRQ9gc+ZJw== X-Google-Smtp-Source: ALg8bN55fKvA+Z26RIz5UV5AUgouKTJXp4Z0uT6N1QlreWrGAzmfOXlZnSZtxewjW8CPJufv/wj+9g== X-Received: by 2002:a63:6346:: with SMTP id x67mr7060533pgb.183.1547124605250; Thu, 10 Jan 2019 04:50:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:49:50 +1100 Message-Id: <20190110124951.15473-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110124951.15473-1-richard.henderson@linaro.org> References: <20190110124951.15473-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Compute TB_FLAGS for TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Enables, but does not turn on, TBI for CONFIG_USER_ONLY. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 21 --------------------- target/arm/helper.c | 13 ++++++------- 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d01a3f9f44..a4bd1becb7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -963,30 +963,9 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; =20 -#ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx) -{ - return (ARMVAParameters) { - /* 48-bit address space */ - .tsz =3D 16, - /* We can't handle tagged addresses properly in user-only mode */ - .tbi =3D false, - }; -} - -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool d= ata) -{ - return aa64_va_parameters_both(env, va, mmu_idx); -} -#else ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -#endif =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c28c6d044..0ceb1fa2b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6549,7 +6549,7 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY =20 /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) @@ -8923,6 +8923,7 @@ void arm_cpu_do_interrupt(CPUState *cs) cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } } +#endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9084,6 +9085,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) } } =20 +#ifndef CONFIG_USER_ONLY /* Translate section/page access permissions to page * R/W protection flags * @@ -9771,6 +9773,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *env,= uint8_t s2attrs) =20 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +#endif /* !CONFIG_USER_ONLY */ =20 ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx) @@ -9841,6 +9844,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, return ret; } =20 +#ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -13087,11 +13091,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 -#ifndef CONFIG_USER_ONLY - /* - * Get control bits for tagged addresses. Note that the - * translator only uses this for instruction addresses. - */ + /* Get control bits for tagged addresses. */ { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); @@ -13110,7 +13110,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } -#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.17.2 From nobody Fri Mar 29 09:47:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547124748792940.9126817061692; Thu, 10 Jan 2019 04:52:28 -0800 (PST) Received: from localhost ([127.0.0.1]:37033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZox-0005Fr-6e for importer@patchew.org; Thu, 10 Jan 2019 07:52:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZmj-0003Re-T5 for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ghZmj-0007Eb-5c for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:09 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:45225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ghZmi-0007EM-WB for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:50:09 -0500 Received: by mail-pl1-x644.google.com with SMTP id a14so5135581plm.12 for ; Thu, 10 Jan 2019 04:50:08 -0800 (PST) Received: from cloudburst.twiddle.net (c220-239-117-135.belrs4.nsw.optusnet.com.au. [220.239.117.135]) by smtp.gmail.com with ESMTPSA id g28sm132656016pfd.100.2019.01.10.04.50.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:50:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gWMN06resPZXoHAK8JhnRzlcGJaOLJwrfdNNmZFKbB8=; b=N2QiAF4j9j9+9kTNuM264OisPOYmhcc8KO2N5mbc9ReXajoygLtC47ej6s3WaUfCoO XjjUDN5I4x3KebJa4JWppk75bUDZnuGkKlgeYurIxsXnn4caqDdnu8y2ijp3bSKyryve 4VNqqE1A5A8ctJxO2jFfOeK6duCHXvIyi9Zi4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gWMN06resPZXoHAK8JhnRzlcGJaOLJwrfdNNmZFKbB8=; b=KNTx9ULgqg5DvIl9a3mnl++q8gZb2So3govexMFxWBT+sKttIg5J/IILtaNVfn2t2X mApQ2/4T6YCSKesjYVuzCHM6yRAWfLwkDVIGhhVReLgJe71HtqirlTyT2iREjpm3RvEQ 4MYEX2iUpd5lz8GMA3EyVVeMjtmg2QGm6YpnRSS4COrzDa9mgBVG3fV/K7myu50vE0nh mwps5ght3IgklLhK7+uEl6bLWC2ronoC1SfrvtU79QS+cY8OCA2KzQU2g1w4m4CMOkrO l0nJ41f7kXv/H8Uk61PWpREzXtpci1w/cGd8pStxlwzOwoOMGSHYGdfRl4MFY0z2sLRZ B4UQ== X-Gm-Message-State: AJcUukfiVUcKH1L2r2Vx2+vXgpIbV9mb0LtKFN+NOonAXoOSxeOXNZ6r /vyfDoVy9/W8otz/PNBOLQpc9btoA6MoPw== X-Google-Smtp-Source: ALg8bN6F5laW2U8XH5BDFhmybf6AeF0OTgUJUDUaMxkDb4tL6L04Krw7aaN2Q+YjtltD/BxVYKILTw== X-Received: by 2002:a17:902:9a47:: with SMTP id x7mr9102907plv.126.1547124607749; Thu, 10 Jan 2019 04:50:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:49:51 +1100 Message-Id: <20190110124951.15473-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110124951.15473-1-richard.henderson@linaro.org> References: <20190110124951.15473-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Enable TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This has been enabled in the linux kernel since v3.11 (commit d50240a5f6cea, 2013-09-03, "arm64: mm: permit use of tagged pointers at EL0"). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 14bc24a35a..5eff6995ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -174,6 +174,12 @@ static void arm_cpu_reset(CPUState *s) env->vfp.zcr_el[1] =3D cpu->sve_max_vq - 1; env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; + /* + * Enable TBI0 and TBI1. While the real kernel only enables TBI0, + * turning on both here will produce smaller code and otherwise + * make no difference to the user-level emulation. + */ + env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { --=20 2.17.2