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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DwJeWp+Qr2T2kEfXaMPGSK0wBAkLZExGSauaPxWOW3g=; b=GOZXTnC47VTuCQleB8WQDgwHVMls5Qx7z3vyNriSz7QBJexNOpBaTh5T7AFWOk5otE npSwyrVW6l1k1+N6PMHGWTSfo1EPOcPRx7bCAqJW8pMcSeL1qIxyvEgEQj2WEfgHUDeu GzYbGKIV+LWTbbJFWXnRenJVjSEENG/v3u+Cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DwJeWp+Qr2T2kEfXaMPGSK0wBAkLZExGSauaPxWOW3g=; b=MrEE4nKscsh5CBr990A0Z/RYMkTx9avdo+iazTVjQawyHurQqKyJ47mdAPJ1/CkbCZ byUFQxWtI1pLy46UraOKVFq1yLvplb3qCIzdogN1Lq5QsS8sP/+sdpBYQC5pNG2gUUXN nUJRLtFPX+BqIJfWWgy1h3/8HS1pSJvb/g6ii1L2S1Z23azZsGI/HmsbIaXVbdNM/I8U uRYzclP8q1E+dTYe9VIPFKYBjKGQqwEkR76huOE0zzuyT4rzfmSceZUDg/6Qzdt5c0QC hIjE6jjV/ep3ji5v5XOZGGjSpwr3ZOkP1WImi5mb0zrgOqXym53yKEvNfkMUaCxKptVn vtpw== X-Gm-Message-State: AJcUukfG9LP/rsAG/DBYyAxpSy2zmM7XnaEoJmthOhpLFGE2ad8rgUz/ yXbgL2e/6GJ3uj9EuKkvxiTtkex+ThU= X-Google-Smtp-Source: ALg8bN7jbrPxE6IwfOp9En8gpKS6kHz91zglocsw/hG2FJdQyXvmzqKpy2APwy5h1+m+u37l4+wNeQ== X-Received: by 2002:a17:902:82c2:: with SMTP id u2mr3586368plz.110.1546986706294; Tue, 08 Jan 2019 14:31:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:02 +1000 Message-Id: <20190108223129.5570-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This path uses cpu_loop_exit_restore to unwind current processor state. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 7 +++++++ target/arm/op_helper.c | 19 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 78e026d6e9..c01a3f8c96 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -103,6 +103,13 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-b= e-1 prefix */ void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el); =20 +/* + * Similarly, but also use unwinding to restore cpu state. + */ +void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_e= l, + uintptr_t ra); + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ef72361a36..8b31c6a13b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,8 +28,8 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs =3D CPU(arm_env_get_cpu(env)); =20 @@ -50,9 +50,24 @@ void raise_exception(CPUARMState *env, uint32_t excp, cs->exception_index =3D excp; env->exception.syndrome =3D syndrome; env->exception.target_el =3D target_el; + + return cs; +} + +void raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) +{ + CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); cpu_loop_exit(cs); } =20 +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t target_el, uintptr_t ra) +{ + CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); + cpu_loop_exit_restore(cs, ra); +} + static int exception_target_el(CPUARMState *env) { int target_el =3D MAX(1, arm_current_el(env)); --=20 2.17.2