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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/zabiqBD3w7s8c81oBx5z5thZaUzr5Ml+9EbpNixrdM=; b=d7XNEfIv6/yYZfm2/6ExFE2XJdzZsGWCDY3nnJr153uZI+97A5w1Ti3UADl9FaVMrW bh6bI1x+aZPsBKn7zwTsOaCDsvxV7IWjvhts7t2SY80et7X6pCXxdFo9HEW+j+F4R+8R ElzQwxh9xRoyFKamu86LvZUCCDTGaGlrnFJwA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/zabiqBD3w7s8c81oBx5z5thZaUzr5Ml+9EbpNixrdM=; b=gKXPv38l4NnjcQ0v+KueCVja4xRs5YBlvpFoPwYl7eqhJuwYZwZT6t5LMeYQEmQ3/Q +nXOIYVxd27NLP9LszS38Y6kES9ctnEy5R2VUUZ2ucYwo9mALkQ7OVD57dUDO5R1yR7d D9snvmngLFVnQvwSdxe+4T5bCWUApwSDFY+gyyj3FfDALwUbU4GlCjPuZ0oaT/08EeIe sII2bXzKab56yvS1PGWyASHIWD6QHSoE/byMlUA5KPw7PfpHpLBJlU0Yas5nz3YNhRNY KaQbyvjByvnvQXTdgBeAcF3jMl8++QZMaweJJsyxYnNFYzvbZ7zdA90b8W3Wdv7/xnTI Ud0g== X-Gm-Message-State: AJcUuke3mQoeRz5WhI41n9H3ut5bqx/l3nl/mhIdKnn/PEv/8DewAHss VnP6xJuAKCQDQowKaLSJKTMJB28ssaU= X-Google-Smtp-Source: ALg8bN4034DkosH1NAqxnGNgnGLEbEJaTpjO20vk+rIpIPZk1SwgTE/WmYrE5/0hW7OLmnuT0w9TuA== X-Received: by 2002:a62:47d9:: with SMTP id p86mr3431638pfi.95.1546986738053; Tue, 08 Jan 2019 14:32:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:14 +1000 Message-Id: <20190108223129.5570-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pattern ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Move arm_mmu_idx declaration to internals.h. --- target/arm/cpu.h | 9 ++++++++- target/arm/internals.h | 8 ++++++++ target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index eb83a71b67..c1d511f274 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2749,7 +2749,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUA= RMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 -/* Determine the current mmu_idx to use for normal loads/stores */ +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ int cpu_mmu_index(CPUARMState *env, bool ifetch); =20 /* Indexes used when registering address spaces with cpu_address_space_ini= t */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 0ed20c03cc..89f3b122a4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -919,4 +919,12 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_mmu_idx: + * @env: The cpu environment + * + * Return the full ARMMMUIdx for the current translation regime. + */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 56d0b60b74..ba6733c4f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32= _t lr, bool dotailchain, limit =3D env->v7m.msplim[M_REG_S]; } } else { - mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx =3D arm_mmu_idx(env); frame_sp_p =3D &env->regs[13]; limit =3D v7m_sp_limit(env); } @@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; uint32_t xpsr =3D xpsr_read(env); uint32_t frameptr =3D env->regs[13]; - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi =3D {}; - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 *attrs =3D (MemTxAttrs) {}; =20 @@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMStat= e *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } =20 -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el =3D arm_current_el(env); + int el; =20 if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, env->v7m.s= ecure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 + el =3D arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } =20 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); int current_el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, current_el); uint32_t flags =3D 0; --=20 2.17.2