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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q39li6splH2Yf4gr+YNRn+Uk8lT+2zbq9YESKjSFOLY=; b=UF407mYgQtMhHiVhNrNEL0XjYPW8fTAF5n3W5F6tLCwpty3DBYBgapu8SHrp1VrhmE 8Aoibud0z0rlbrkrMY8XucSh2lVpt13zRyxMOIA1X5KFlEJ43jp1x745BCI0CFrvNmka Pbw/EGNbIgSOl7WgJWSqJiKErT6Epsiny9XOw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q39li6splH2Yf4gr+YNRn+Uk8lT+2zbq9YESKjSFOLY=; b=ISv1jp3LJFpEvMQsjMR/8YqVhomAMk9By7uJT/a2DPv9Qm+oWZYfJm1f8YcR+KCx43 jzT4NIpLb8imb6Ap10VhIwqtUWyDozO6umDs/uqJ0rIZpsr9xCk/9OkBBsOAvwjxr5w8 DFpXNQmMa6QXsPEZX9PpETC4IYF4hiGQrMlLAdZMkjykrGjFfYUInrF7U4eLLIrWxHbe ZLd/kdE7ZjeO6ML0h5+3qMaoxcISLqVdMPWqTW+IML24cB9BF1HqMykTc0aCVqOoF79w gthfnrEOGbBSQ5itIpGNrxZ/hxOUn4Uctq1h3LDDp2K/fQU9UjUa3pTnEYWc+hvSkqJQ RhQQ== X-Gm-Message-State: AJcUukcKtGFUYwXozyB0nKiy+IL/cB9KCd2UIdTmL/PQya3UHlCq/b+M 37l9MoLW+pLTRjp4zfh3IwBBmeKHCtg= X-Google-Smtp-Source: ALg8bN42VdN5S2qtwKrSCyNbv8Qhbw7uCJloMmKAyUVKl5HCoEQCVtsBFRDHUUCpOUNkaOBgS7FGVg== X-Received: by 2002:a17:902:7296:: with SMTP id d22mr3640158pll.265.1546986698401; Tue, 08 Jan 2019 14:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:30:59 +1000 Message-Id: <20190108223129.5570-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add storage space for the 5 encryption keys. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Remove pointless double migration. Use a struct to make it clear which half is which. --- target/arm/cpu.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6f606eb97b..8b891bbc30 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -201,11 +201,16 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 -/* In AArch32 mode, predicate registers do not exist at all. */ #ifdef TARGET_AARCH64 +/* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); } ARMPredicateReg; + +/* In AArch32 mode, PAC keys do not exist at all. */ +typedef struct ARMPACKey { + uint64_t lo, hi; +} ARMPACKey; #endif =20 =20 @@ -605,6 +610,14 @@ typedef struct CPUARMState { uint32_t cregs[16]; } iwmmxt; =20 +#ifdef TARGET_AARCH64 + ARMPACKey apia_key; + ARMPACKey apib_key; + ARMPACKey apda_key; + ARMPACKey apdb_key; + ARMPACKey apga_key; +#endif + #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ int eabi; @@ -3264,6 +3277,21 @@ static inline bool isar_feature_aa64_fcma(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; } =20 +static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) +{ + /* + * Note that while QEMU will only implement the architected algorithm + * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation + * defined algorithms, and thus API+GPI, and this predicate controls + * migration of the 128-bit keys. + */ + return (id->id_aa64isar1 & + (FIELD_DP64(0, ID_AA64ISAR1, APA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, API, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPI, -1))) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987013061768.4115325429627; Tue, 8 Jan 2019 14:36:53 -0800 (PST) Received: from localhost ([127.0.0.1]:40781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzzP-00044L-Ua for importer@patchew.org; Tue, 08 Jan 2019 17:36:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzuR-0007w7-LK for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzuQ-00049k-I2 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:43 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzuQ-00048a-Cf for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:42 -0500 Received: by mail-pf1-x441.google.com with SMTP id b7so2607250pfi.8 for ; Tue, 08 Jan 2019 14:31:42 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hH55bLkql39OTMji4tcf4IYVIJI0UJzo6VknZottr4Q=; b=NdVSPtsfra2r4zlF2NpncgObmFB5jWJOhI1SvtPm1Dy8NHBYUXqNTrnOSF7PFdzfbM 3VtXHcAzKgLcI3LT/D9z3hBoXvLSii5yUWIQdlKlh2K+cqcS1EWUK1XoRkGF2TGBOq8k nZ4ltFBZdiL9gt6dOaU27N5mRSJUTuZm7hjBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hH55bLkql39OTMji4tcf4IYVIJI0UJzo6VknZottr4Q=; b=BtNl5PgctIkTYodOYHQL4IsHXPKLTjSY3OeheROMtaguOxWzXCioESTXGua4g1BTWi vJfJb/O+hdEhZm0Ra5BdbB1UapZsIuRlThcLLiH6b7jNwF781Wh1e7rNO0j2V9or3Otf GlYtlEz6zccJpmf4BGXHj7552C+ME3Ov6mTwi+VopqPxKYGHDU1b5IfidBA0L3R1T33M JSDcIpIAvfwhoypWsT+daX7Hqi/BctzWMKGDmzHTIVOWt43HWYuH8Dvg9+/raFfnD6N9 TQ1jan+D31adkz7R2QWZxYPTVXGzrmGUJ9jlROqy+UDHD7+tUoETkkp89Z8xatZXo1g9 m5iA== X-Gm-Message-State: AJcUukd8YhB2xnsypdZfIKcpdVWIF8rBCFP25BYruLoOUVcNvPyL8t1A rouXjK1vXhcxQbtjPeM6w+2+CRxFej4= X-Google-Smtp-Source: ALg8bN67o8++D1evwYADp/b2IjcYBnGuN9Lo+OgS2/962wC8WgB9bzjsiLMaRibI4Dv5NjNQl9+J2g== X-Received: by 2002:a63:3703:: with SMTP id e3mr944934pga.348.1546986701001; Tue, 08 Jan 2019 14:31:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:00 +1000 Message-Id: <20190108223129.5570-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Post v8.4 bits taken from SysReg_v85_xml-00bet8. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Review fixups from Peter. --- target/arm/cpu.h | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8b891bbc30..843d5936ea 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -991,12 +991,15 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_A (1U << 1) #define SCTLR_C (1U << 2) #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ -#define SCTLR_SA (1U << 3) +#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ +#define SCTLR_SA (1U << 3) /* AArch64 only */ #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ +#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ +#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -1004,35 +1007,53 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7 onward */ -#define SCTLR_Z (1U << 11) +#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ +#define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) -#define SCTLR_V (1U << 13) +#define SCTLR_V (1U << 13) /* AArch32 only */ +#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ #define SCTLR_RR (1U << 14) /* up to v7 */ #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWI (1U << 16) /* v8 onward */ -#define SCTLR_HA (1U << 17) +#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ #define SCTLR_BR (1U << 17) /* PMSA only */ #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWE (1U << 18) /* v8 onward */ #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ -#define SCTLR_UWXN (1U << 20) /* v7 onward */ -#define SCTLR_FI (1U << 21) -#define SCTLR_U (1U << 22) +#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ +#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ +#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ +#define SCTLR_EIS (1U << 22) /* v8.5-ExS */ #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ +#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ #define SCTLR_VE (1U << 24) /* up to v7 */ #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ #define SCTLR_EE (1U << 25) #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ -#define SCTLR_NMFI (1U << 27) -#define SCTLR_TRE (1U << 28) -#define SCTLR_AFE (1U << 29) -#define SCTLR_TE (1U << 30) +#define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ +#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ +#define SCTLR_TRE (1U << 28) /* AArch32 only */ +#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_AFE (1U << 29) /* AArch32 only */ +#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_TE (1U << 30) /* AArch32 only */ +#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ +#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ +#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ +#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ +#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ +#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ +#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ +#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ +#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ =20 #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sbd4WM6pLVZ+wZDxANSyv9ApfZdYcZeOcA2TgJcvPjg=; b=J0OMeA5LLB9RwCaRyMEPf7mbefxtfXw3XLZXFtGjRtJUTHIJkwZLqwra2eApIjbm/S x6npo1iQIKV5nSc34GKx5RMpzBnHgBtgaiUzgE8BV2ENH8BSMvRgBIM5Zr8elhfH7+aQ KYj6XmIVkHW+LDpVzzUkOH45Xf1Vi06QMZhlw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sbd4WM6pLVZ+wZDxANSyv9ApfZdYcZeOcA2TgJcvPjg=; b=EaWyc1sCYY5X2/Iocq5CZXzlhaciKdVJcwPg2HLNk7/gDKFWv9WKOg8zmBZZTKhsJ6 Wmrkjo8cFC/rKGmv3YjDI9L104xqnhR/kt0V87CRPJHbr4yXvpBNKKU4pRwTyhMiaBEH T79YuxN7hQlwUU6iD4H8GGZajXrBE3ReHAhC4EX60ehJ6RvLMC0y432g/IQ+VGfltlqF 439ENJOsh2QBjq+0vZ+NV6x07cEQkBRoupoo2boK3VsL32QuCz8M1TbANcCEZn0A6o55 F248NBshHVu2+WWm8OnW43dbAJoB0WyITtnBHmjHFPRhy4oV/iJZRyr1XfvF3V739Emz g+AA== X-Gm-Message-State: AJcUukft7s3UPyGZTFCzHRlO7Yd/BKnTIc8Hpfa8u7oe+CPJsYwYY6Qk elvPx4uM2TeYZWBXJ/Yu8ZjdmwUkQmU= X-Google-Smtp-Source: ALg8bN6oQLLhjjlbleNOxFJOF/n2EJiTACZnysPRpBupuVwW04dsEtFyp+2nPvg+vKuwwKYlrgeHTQ== X-Received: by 2002:a17:902:b68d:: with SMTP id c13mr3593080pls.102.1546986703719; Tue, 08 Jan 2019 14:31:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:01 +1000 Message-Id: <20190108223129.5570-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Fix whitespace, comment grammar. v3: Rebase on FIELD definition. --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 843d5936ea..9ad7b2d11e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3014,6 +3014,7 @@ FIELD(TBFLAG_A64, TBI0, 0, 1) FIELD(TBFLAG_A64, TBI1, 1, 1) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7..d8a8bb4e9c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f00c141ef9..f23555b1dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12983,6 +12983,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b6ab6371..37a57af715 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13409,6 +13409,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; + dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546986846814986.7927558967943; Tue, 8 Jan 2019 14:34:06 -0800 (PST) Received: from localhost ([127.0.0.1]:40034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzwj-0001Gg-DY for importer@patchew.org; Tue, 08 Jan 2019 17:34:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzuW-00081v-QK for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzuV-0004GH-S3 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:48 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:35298) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzuV-0004Ft-MH for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:47 -0500 Received: by mail-pl1-x642.google.com with SMTP id p8so2576110plo.2 for ; Tue, 08 Jan 2019 14:31:47 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DwJeWp+Qr2T2kEfXaMPGSK0wBAkLZExGSauaPxWOW3g=; b=GOZXTnC47VTuCQleB8WQDgwHVMls5Qx7z3vyNriSz7QBJexNOpBaTh5T7AFWOk5otE npSwyrVW6l1k1+N6PMHGWTSfo1EPOcPRx7bCAqJW8pMcSeL1qIxyvEgEQj2WEfgHUDeu GzYbGKIV+LWTbbJFWXnRenJVjSEENG/v3u+Cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DwJeWp+Qr2T2kEfXaMPGSK0wBAkLZExGSauaPxWOW3g=; b=MrEE4nKscsh5CBr990A0Z/RYMkTx9avdo+iazTVjQawyHurQqKyJ47mdAPJ1/CkbCZ byUFQxWtI1pLy46UraOKVFq1yLvplb3qCIzdogN1Lq5QsS8sP/+sdpBYQC5pNG2gUUXN nUJRLtFPX+BqIJfWWgy1h3/8HS1pSJvb/g6ii1L2S1Z23azZsGI/HmsbIaXVbdNM/I8U uRYzclP8q1E+dTYe9VIPFKYBjKGQqwEkR76huOE0zzuyT4rzfmSceZUDg/6Qzdt5c0QC hIjE6jjV/ep3ji5v5XOZGGjSpwr3ZOkP1WImi5mb0zrgOqXym53yKEvNfkMUaCxKptVn vtpw== X-Gm-Message-State: AJcUukfG9LP/rsAG/DBYyAxpSy2zmM7XnaEoJmthOhpLFGE2ad8rgUz/ yXbgL2e/6GJ3uj9EuKkvxiTtkex+ThU= X-Google-Smtp-Source: ALg8bN7jbrPxE6IwfOp9En8gpKS6kHz91zglocsw/hG2FJdQyXvmzqKpy2APwy5h1+m+u37l4+wNeQ== X-Received: by 2002:a17:902:82c2:: with SMTP id u2mr3586368plz.110.1546986706294; Tue, 08 Jan 2019 14:31:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:02 +1000 Message-Id: <20190108223129.5570-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This path uses cpu_loop_exit_restore to unwind current processor state. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 7 +++++++ target/arm/op_helper.c | 19 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 78e026d6e9..c01a3f8c96 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -103,6 +103,13 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-b= e-1 prefix */ void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el); =20 +/* + * Similarly, but also use unwinding to restore cpu state. + */ +void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_e= l, + uintptr_t ra); + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ef72361a36..8b31c6a13b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,8 +28,8 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs =3D CPU(arm_env_get_cpu(env)); =20 @@ -50,9 +50,24 @@ void raise_exception(CPUARMState *env, uint32_t excp, cs->exception_index =3D excp; env->exception.syndrome =3D syndrome; env->exception.target_el =3D target_el; + + return cs; +} + +void raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) +{ + CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); cpu_loop_exit(cs); } =20 +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t target_el, uintptr_t ra) +{ + CPUState *cs =3D do_raise_exception(env, excp, syndrome, target_el); + cpu_loop_exit_restore(cs, ra); +} + static int exception_target_el(CPUARMState *env) { int target_el =3D MAX(1, arm_current_el(env)); --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 154698720541222.95636498676481; Tue, 8 Jan 2019 14:40:05 -0800 (PST) Received: from localhost ([127.0.0.1]:41612 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh02R-0006v9-A5 for importer@patchew.org; Tue, 08 Jan 2019 17:39:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzua-00085n-11 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzuY-0004Iy-Gi for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:52 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:35965) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzuY-0004ID-9B for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:50 -0500 Received: by mail-pl1-x641.google.com with SMTP id g9so2570221plo.3 for ; Tue, 08 Jan 2019 14:31:50 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h+04INpMZROzc9/azuKb56sot5Z3Kx02xVkcUaXDkl4=; b=TgFB3Vm5T8K0javhMogC2lG4cgUkwL/C7+WLKyNezEwINI4o5IzRc2V6Nloq4Eck+d T9OkOGBVK8R/NwRUgVEjJRJK+KLc4FGryWnzrLmcvPQpLHG6EWBY61LnbkY8TVU2IsQc qov4yWDpP4JxQZmZFUMnAEkpR8Tr2s5XFDi8s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h+04INpMZROzc9/azuKb56sot5Z3Kx02xVkcUaXDkl4=; b=OjUf9+uw1WnQFBYbiYGm3O+nEA0PVGB31B03gNf1zs5PAgGF4yAqSfMTJq0HXRRXz1 9DJD/gOPEoM3JcRhoN57D/w1sZrNnDw7B1LPsbvX+km2yqmPTbrzBJ1VpvO2NgX6L3Ed p4lGAW+s1+bWXz9BYkkGSgojF++wD2FPj9picuxvUuo7dD0mZKTKFIRPGD3auh3x2UUF pkXHZVXS18tFUsScnbg50GKfQ+/ImmTaEl/1aMkdSSy8TBbqlAsadKNyyrj1zDyWOeNx 4GeLk013WK7NxZmQxZvQ7OmFZB1qwL3OWClYFQJ8xc12PapaO+HCWjJ+qjpCy4xupq9E 5b2Q== X-Gm-Message-State: AJcUukfApI/pdDAkIdNZhblknam/HnREr0I7wZ3AWTzJnHX2QA3nCEgd m/gK3DdKoOnknI+TazrTD8tkoQq2Ud4= X-Google-Smtp-Source: ALg8bN7CAfh3+3PObJpVKuxEyQsGcOrxu3JIm2sepQR4H7e0c3SsRzomC5P5whDlFUKaVsJHqjR2KA== X-Received: by 2002:a17:902:be0e:: with SMTP id r14mr3368419pls.124.1546986708807; Tue, 08 Jan 2019 14:31:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:03 +1000 Message-Id: <20190108223129.5570-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The cryptographic internals are stubbed out for now, but the enable and trap bits are checked. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell ---- v2: Remove trap from xpac* helpers; these are now side-effect free. Use struct ARMPACKey. v3: Move code to pauth_helper.c; use raise_exception_ra. --- target/arm/helper-a64.h | 12 +++ target/arm/internals.h | 6 ++ target/arm/pauth_helper.c | 186 ++++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 1 + 4 files changed, 205 insertions(+) create mode 100644 target/arm/pauth_helper.c diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 9d3a907049..28aa0af69d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -85,3 +85,15 @@ DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) +DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index c01a3f8c96..0ed20c03cc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -266,6 +266,7 @@ enum arm_exception_class { EC_CP14DTTRAP =3D 0x06, EC_ADVSIMDFPACCESSTRAP =3D 0x07, EC_FPIDTRAP =3D 0x08, + EC_PACTRAP =3D 0x09, EC_CP14RRTTRAP =3D 0x0c, EC_ILLEGALSTATE =3D 0x0e, EC_AA32_SVC =3D 0x11, @@ -433,6 +434,11 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } =20 +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c new file mode 100644 index 0000000000..902f68a24c --- /dev/null +++ b/target/arm/pauth_helper.c @@ -0,0 +1,186 @@ +/* + * ARM v8.3-PAuth Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, + ARMPACKey key) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modi= fier, + ARMPACKey *key, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifi= er, + ARMPACKey *key, bool data, int keynumber) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, + uintptr_t ra) +{ + raise_exception_ra(env, EXCP_UDEF, syn_pactrap(), target_el, ra); +} + +static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) +{ + if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool trap =3D !(hcr & HCR_API); + /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. = */ + if (trap) { + pauth_trap(env, 2, ra); + } + } + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + if (!(env->cp15.scr_el3 & SCR_API)) { + pauth_trap(env, 3, ra); + } + } +} + +static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) +{ + uint32_t sctlr; + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[el]; + } + return (sctlr & bit) !=3D 0; +} + +uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apia_key, false); +} + +uint64_t HELPER(pacib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apib_key, false); +} + +uint64_t HELPER(pacda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apda_key, true); +} + +uint64_t HELPER(pacdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apdb_key, true); +} + +uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) +{ + uint64_t pac; + + pauth_check_trap(env, arm_current_el(env), GETPC()); + pac =3D pauth_computepac(x, y, env->apga_key); + + return pac & 0xffffffff00000000ull; +} + +uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apia_key, false, 0); +} + +uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apib_key, false, 1); +} + +uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apda_key, true, 0); +} + +uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el =3D arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apdb_key, true, 1); +} + +uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, false); +} + +uint64_t HELPER(xpacd)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, true); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 11c7baf8a3..1a4fc06448 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,6 +8,7 @@ obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D neon_helper.o iwmmxt_helper.o vec_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o +obj-$(TARGET_AARCH64) +=3D pauth_helper.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1hpvolh3eiZvY+EUwSFoFURlL4sKnYluLlSrcZoczFI=; b=CQIP4kJxBA5D7C+yzEnqU/uqEzFoP9NmNjvYy/wMQ/q0PVDtRH/i7gzE4ohseQcqL4 C/E/hh02eupUdrbgVzs0Ndwy9uS3yVqypZpKJ5gj6V0QR2qdTbRqctyNji2FYTCutq2W zqCfEW83nVdArH8+9jjOySiKU/UmGEDtudZ0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1hpvolh3eiZvY+EUwSFoFURlL4sKnYluLlSrcZoczFI=; b=IUf+Er07EhO923PxXkhADPigF9jV2YR6yQcmCfuRbXYkdDhaPrBUlAv1bWpedzSFx0 LkJYKf8G2VgzZUJLQqyy4mKUtl2rz1gBO/wiiWgXDaEz34aOJGI1o7EV+3qLg/SkBBq7 HlLfra/x7EqSrQD6rmskN3CWB+Sl95MizI8rJM1a+InCfpcswjSZLl3NqL1cns0t0RHH GgYYx5VCy7g5gA5wp38rRv5PzfhtmEcxm/7E7dWrKO5YgCXfBv83i/7/IXdctasBkOnv +1xLI+hUrIjoen8vUtiHsuZmx4rVCK8WO46E4Tr4hgrtgEnHqzQyZ8XsaFJvE1Mxzt2o lk5g== X-Gm-Message-State: AJcUukeE2QcWwPQd0mxaqlArZMv/U1IToXFOgaDM1o5Hpuc9ABXyJdPN cC6cyk0zP02jNX0prrfH9VDZphDQSsg= X-Google-Smtp-Source: ALg8bN7aC3kD/MmjoEgzdi1TXlBHSQZXbdqQKJOrkQHJqh976cGlLObmxcyH9YHPaVqMwD6s2kJBMg== X-Received: by 2002:a17:902:ab92:: with SMTP id f18mr3426026plr.221.1546986711324; Tue, 08 Jan 2019 14:31:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:04 +1000 Message-Id: <20190108223129.5570-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use binary literals. --- target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 37a57af715..b72aea3e97 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t = insn, } =20 switch (selector) { - case 0: /* NOP */ - return; - case 3: /* WFI */ + case 0b00000: /* NOP */ + break; + case 0b00011: /* WFI */ s->base.is_jmp =3D DISAS_WFI; - return; + break; + case 0b00001: /* YIELD */ /* When running in MTTCG we don't generate jumps to the yield and * WFE helpers as it won't affect the scheduling of other vCPUs. * If we wanted to more completely model WFE/SEV so we don't busy * spin unnecessarily we would need to do something more involved. */ - case 1: /* YIELD */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp =3D DISAS_YIELD; } - return; - case 2: /* WFE */ + break; + case 0b00010: /* WFE */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp =3D DISAS_WFE; } - return; - case 4: /* SEV */ - case 5: /* SEVL */ + break; + case 0b00100: /* SEV */ + case 0b00101: /* SEVL */ /* we treat all as NOP at least for now */ - return; + break; + case 0b00111: /* XPACLRI */ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + break; + case 0b01000: /* PACIA1716 */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01010: /* PACIB1716 */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01100: /* AUTIA1716 */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01110: /* AUTIB1716 */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b11000: /* PACIAZ */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11001: /* PACIASP */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11010: /* PACIBZ */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11011: /* PACIBSP */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11100: /* AUTIAZ */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11101: /* AUTIASP */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11110: /* AUTIBZ */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11111: /* AUTIBSP */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; default: /* default specified as NOP equivalent */ - return; + break; } } =20 --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987205210253.52803249065357; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vn+yRU/rmAqgBGT/k9IA0vQaUDDZLiUOVZPLPr+Ejm8=; b=hwsJB3lJhqwc1/sRd63VVnxZH9+mLrABx3VrpfI6VTvMBL7FF9DpGd+yyvT54VK5LA zEiKCKR/JjAMKLml6Fwo3ixwFuz7Vm7lhl5V0V0R7PpSpUEq7FZXhaGr0h0XuTV6lcHA Lh/CKcPFQNSSOq+MlRoVENco67HItvXB4nC54= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vn+yRU/rmAqgBGT/k9IA0vQaUDDZLiUOVZPLPr+Ejm8=; b=LFfxcSaLrigbWlDrUxI00GwI2FjMme+/viNzUo33TZu8+6WaepS5thyE26oAqZLvr7 J22rPsAn32mRWte7G+aXXIUjk0GCC31oEbq226E50sQUbFPfe8n81WVa0Uqgw9XU0Xzq i7TGMpI+zxVUPxFqnb4LJz7Hc3Qya9qr0QVP3YCz3CkC69QWDwEGAf0O5ZWFflpRM1u6 U1P0IbOOdY/ct3q2MYNzoVPr+yOQF1RCMPFOh3/uHfm13blSeelWf5CEw2U3z7M3FNEi A9dNl8dg41Ti160pL0wmSCIOp3OvVkbJL1bsx0WlnOUP+7qc8j/8cllkeon6FTBmOsIa Ghhw== X-Gm-Message-State: AJcUukchdYQRSHLJfLjH9vnM0dwTngiKiVse+0JpSxYszw0Ydx+bnBVy LRl0iCB6u8kjRdRj7yg0T8cdmbvMdZU= X-Google-Smtp-Source: ALg8bN59Ca8wL8uI5gI3ExIpGwGyy84UoFpRFFvqfB+FOLrYg6w4VVGLsV1C7mXqCBe2jrtZGinFlQ== X-Received: by 2002:a17:902:b090:: with SMTP id p16mr3603596plr.190.1546986713869; Tue, 08 Jan 2019 14:31:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:05 +1000 Message-Id: <20190108223129.5570-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now properly signals unallocated for REV64 with SF=3D0. Allows for the opcode2 field to be decoded shortly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b72aea3e97..dac61a3c3a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4563,38 +4563,51 @@ static void handle_rev16(DisasContext *s, unsigned = int sf, */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsigned int sf, opcode, rn, rd; + unsigned int sf, opcode, opcode2, rn, rd; =20 - if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { + if (extract32(insn, 29, 1)) { unallocated_encoding(s); return; } =20 sf =3D extract32(insn, 31, 1); opcode =3D extract32(insn, 10, 6); + opcode2 =3D extract32(insn, 16, 5); rn =3D extract32(insn, 5, 5); rd =3D extract32(insn, 0, 5); =20 - switch (opcode) { - case 0: /* RBIT */ +#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) + + switch (MAP(sf, opcode2, opcode)) { + case MAP(0, 0x00, 0x00): /* RBIT */ + case MAP(1, 0x00, 0x00): handle_rbit(s, sf, rn, rd); break; - case 1: /* REV16 */ + case MAP(0, 0x00, 0x01): /* REV16 */ + case MAP(1, 0x00, 0x01): handle_rev16(s, sf, rn, rd); break; - case 2: /* REV32 */ + case MAP(0, 0x00, 0x02): /* REV/REV32 */ + case MAP(1, 0x00, 0x02): handle_rev32(s, sf, rn, rd); break; - case 3: /* REV64 */ + case MAP(1, 0x00, 0x03): /* REV64 */ handle_rev64(s, sf, rn, rd); break; - case 4: /* CLZ */ + case MAP(0, 0x00, 0x04): /* CLZ */ + case MAP(1, 0x00, 0x04): handle_clz(s, sf, rn, rd); break; - case 5: /* CLS */ + case MAP(0, 0x00, 0x05): /* CLS */ + case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + default: + unallocated_encoding(s); + break; } + +#undef MAP } =20 static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987041946435.08650165714107; Tue, 8 Jan 2019 14:37:21 -0800 (PST) Received: from localhost ([127.0.0.1]:40898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzzs-0004VN-QH for importer@patchew.org; Tue, 08 Jan 2019 17:37:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzuh-0008EK-MJ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzug-0004Sr-Ny for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:59 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:44810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzug-0004SL-GO for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:31:58 -0500 Received: by mail-pg1-x541.google.com with SMTP id t13so2345852pgr.11 for ; Tue, 08 Jan 2019 14:31:58 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RPDBYEPnq8VUHD21sOkgc4lwKfdr/8rUEWyrTjwmWuI=; b=gRNKnM+yk5lZJmN3sGTtEujymeq4rwAZgF4LnmUHWCYU8gblwAIM4cbcxnDkGzjucG AqSylImxzb26mXxRsARL7mo/lrTjvEQeIx9hCZQaQSJ5s9jpQZl35oA4/2p5xaW/5bQN 1l5P6Ea06bSpM7I8v8n9LeJ4M/l2HB3WjwEzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RPDBYEPnq8VUHD21sOkgc4lwKfdr/8rUEWyrTjwmWuI=; b=exyo1VgR79KpR8H8m3oQkF2E3tj1FryTvlWISltPOhNxrwIagRuphRCs8AiczzSS6s xuHqyM+LXI/oE+v9uepoIdvMnWoDNSI1+WzXrRcbGQ9zbBGBmyRvq1i6SUdnNBGFvYG3 IVhaf2QFiv0nPEnnSndrbigOUHfhehuBeKjzcSEXira5nYsVifArBsUugsLG0Oi8DpXx c1+aOqYJBSHUsxdYnyDZOquoE9aeVfgHrXDYyTlZBSiiQnzI/jfWwBLUY5BPQen6iLnV jAf3Io7SXMRh2DfsJ27Se7GpNFA/AWBmDF37coJUbZnVSlJR1OvFgB2ZVSqhqZzfflKx 5Fyw== X-Gm-Message-State: AJcUukf85AoVABf4i8L7sD8MdN/I4Mvfb8qqlXNA25VVFnncYif/JeyY GT5moUsNBN759HXzJJ6TXkkfykg6WiU= X-Google-Smtp-Source: ALg8bN4mnlISpDhG0G4gnFftcX7wNVzAT1Udi21h9jO40mK/95qMDKEJkaMmjVeAvnUtuqSQUhVtqQ== X-Received: by 2002:a63:d34a:: with SMTP id u10mr3181879pgi.301.1546986717065; Tue, 08 Jan 2019 14:31:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:06 +1000 Message-Id: <20190108223129.5570-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 146 +++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dac61a3c3a..8a8408c1b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4564,6 +4564,7 @@ static void handle_rev16(DisasContext *s, unsigned in= t sf, static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { unsigned int sf, opcode, opcode2, rn, rd; + TCGv_i64 tcg_rd; =20 if (extract32(insn, 29, 1)) { unallocated_encoding(s); @@ -4602,7 +4603,152 @@ static void disas_data_proc_1src(DisasContext *s, u= int32_t insn) case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + case MAP(1, 0x01, 0x00): /* PACIA */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x01): /* PACIB */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x02): /* PACDA */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x03): /* PACDB */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x04): /* AUTIA */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x05): /* AUTIB */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x06): /* AUTDA */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x07): /* AUTDB */ + if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x08): /* PACIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x09): /* PACIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0a): /* PACDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0b): /* PACDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0c): /* AUTIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0d): /* AUTIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0e): /* AUTDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0f): /* AUTDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x10): /* XPACI */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); + } + break; + case MAP(1, 0x01, 0x11): /* XPACD */ + if (!dc_isar_feature(aa64_pauth, s) || rn !=3D 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd =3D cpu_reg(s, rd); + gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); + } + break; default: + do_unallocated: unallocated_encoding(s); break; } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dXLS5fVNJnRkJgiMJ909NePnJV7jyqlbgEEqs1m1G7o=; b=E/jB7loO+9W4KF/KZCanNzSwbcf8w86J5GuVDV3nDdwyCaBmBG3aAs5EL6aLKMden1 kFrcgrpqCn+9j5o3G4QpJUx8iC1c1wvcTyk40Aj2asHPVugbAXNLKqF8kWN5MO57F8Mb Nj1/aZ3V+75yJ2WsNnD6F12jNZ+LHeo2QzSUM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dXLS5fVNJnRkJgiMJ909NePnJV7jyqlbgEEqs1m1G7o=; b=bSS6vy9rMpQI/RVrGbtdnJNqynztEb4DZvLvnwTNL90+BrY/7ADD7/7MgrwKTxZUzk x+5P/GTi76RS8uCiC0vjOyglGd21o8qrd5nE/PswEZchevCviIJTB07ygNqc0N2M3EWf iqcT/9lg2wOF9eiRsuEeWgFvpS50XZMZBRGixG8Y70k7/hXgcu8TWeJDSLtD4/oM8FZW P7mCKxXxGlr8H/tlwrSQh3Jq+PMgAclgKEl7ikqrGyaIkdpm4EoOY3slXKCAiHdprPwA mLE81I8xg3hH7Vbp2ci3/vSRA2YOOk/lNwmI8m3MN06ghwyLg4xkcnm/YWwAzcx+FSA7 dJkw== X-Gm-Message-State: AJcUukdcJKn/5uC7fsoxjbS8eWJVuHNsUrHNh/i7R6N9HpNfCsdPRbBF t4EJw1RQlYi7nXVPvO6t51gZFJLR8uw= X-Google-Smtp-Source: ALg8bN6ZH1WE9CNsJLR/8UhmRxwxLhjU7husCXBqCHEsGgMePuzllv+FezvohuQ3qv7pgnEzr1FbbA== X-Received: by 2002:a17:902:f20b:: with SMTP id gn11mr3432458plb.274.1546986719958; Tue, 08 Jan 2019 14:31:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:07 +1000 Message-Id: <20190108223129.5570-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a8408c1b7..3f08db580b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4884,6 +4884,13 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) case 11: /* RORV */ handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); break; + case 12: /* PACGA */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + gen_helper_pacga(cpu_reg(s, rd), cpu_env, + cpu_reg(s, rn), cpu_reg_sp(s, rm)); + break; case 16: case 17: case 18: @@ -4899,6 +4906,7 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) break; } default: + do_unallocated: unallocated_encoding(s); break; } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987374493599.8714306258306; Tue, 8 Jan 2019 14:42:54 -0800 (PST) Received: from localhost ([127.0.0.1]:42401 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh05F-0001UO-B5 for importer@patchew.org; Tue, 08 Jan 2019 17:42:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52640) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzuz-0008Ty-G6 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzuv-0004ca-5X for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:15 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:46779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzur-0004Xr-M7 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:11 -0500 Received: by mail-pg1-x544.google.com with SMTP id w7so2340599pgp.13 for ; Tue, 08 Jan 2019 14:32:04 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lt41ush15v+T/TJPDHCvxVydKk9mEhGCuLjZ+pQgQ+U=; b=I/Eb/QmcRDHn+0XQrWKxVg88WTBUjXi/LUYfKghc1jqUxlmUcNskAznlpvx43oq4u+ kxuvIWnrh3RHcr42BogdFM6ot6RT/KtIPqX6jpfHPfU3RAvVAUWrWj4QNWep79jBtwl9 ThigbRTkRk3Cf68j0CBLhTAee2PcR5msZcJNo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lt41ush15v+T/TJPDHCvxVydKk9mEhGCuLjZ+pQgQ+U=; b=Z0fhp1Cg9pHBu1PEzS67tQenP8NDIEvBB6WQZYb4IiGA7ZE+GJWFzrXOCjSVRQENN5 YrgSqsRK57cp9g5Lqby0MTMg/0dUE72ZcKXG3WAwPR6T/SJH7J9QkpGjOiA3VcuETLnm zrIySK+NJB9LLWUQoNXZIVE8gbAIYlaUW1iPGoFNiwyOcDyGIhyIw03m8aYFqG1pAhSJ Uj+uc7egS7RHeC03nuLmO52R/RFvXSP2vsRETZ3LqgrvgtFCF6sot6pd1gCHK7PZyWnZ OG2KR00qJ3lc2QlMc/zUiZX4yyof3orx8prS9UHIQIqrze48ARZvjTgYjHrv4MpLILam 2oKA== X-Gm-Message-State: AJcUukcGKZpxwa99gXnJub9dAdlHb8Uw3LPvs/3+GwInTninsRZfJDdt OendQDfo44+HYD3cSbkeHvdaFIH17No= X-Google-Smtp-Source: ALg8bN5AKcoWykwMeyCIJQn5rGv77n1eamlxXNrH0SH7ST9npxc6raYaTBbsNCOsph7j0HzuxoGvIQ== X-Received: by 2002:a63:4342:: with SMTP id q63mr3152610pga.63.1546986722784; Tue, 08 Jan 2019 14:32:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:08 +1000 Message-Id: <20190108223129.5570-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This function is only used by AArch64. Code movement only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 155 ++++++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 155 ---------------------------------------- 4 files changed, 157 insertions(+), 156 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 28aa0af69d..55299896c4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,6 +86,8 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) =20 +DEF_HELPER_1(exception_return, void, env) + DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index 8c9590091b..53a38188c6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -79,7 +79,6 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) -DEF_HELPER_1(exception_return, void, env) =20 DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 61799d20e1..66ff70dcdb 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -887,6 +887,161 @@ uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void = *fpstp) return float16_to_uint16(a, fpst); } =20 +static int el_from_spsr(uint32_t spsr) +{ + /* Return the exception level that this SPSR is requesting a return to, + * or -1 if it is invalid (an illegal return) + */ + if (spsr & PSTATE_nRW) { + switch (spsr & CPSR_M) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_FIQ: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_SYS: + return 1; + case ARM_CPU_MODE_MON: + /* Returning to Mon from AArch64 is never possible, + * so this is an illegal return. + */ + default: + return -1; + } + } else { + if (extract32(spsr, 1, 1)) { + /* Return with reserved M[1] bit set */ + return -1; + } + if (extract32(spsr, 0, 4) =3D=3D 1) { + /* return to EL0 with M[0] bit set */ + return -1; + } + return extract32(spsr, 2, 2); + } +} + +void HELPER(exception_return)(CPUARMState *env) +{ + int cur_el =3D arm_current_el(env); + unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); + uint32_t spsr =3D env->banked_spsr[spsr_idx]; + int new_el; + bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; + + aarch64_save_sp(env, cur_el); + + arm_clear_exclusive(env); + + /* We must squash the PSTATE.SS bit to zero unless both of the + * following hold: + * 1. debug exceptions are currently disabled + * 2. singlestep will be active in the EL we return to + * We check 1 here and 2 after we've done the pstate/cpsr write() to + * transition to the EL we're going to. + */ + if (arm_generate_debug_exceptions(env)) { + spsr &=3D ~PSTATE_SS; + } + + new_el =3D el_from_spsr(spsr); + if (new_el =3D=3D -1) { + goto illegal_return; + } + if (new_el > cur_el + || (new_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + /* Disallow return to an EL which is unimplemented or higher + * than the current one. + */ + goto illegal_return; + } + + if (new_el !=3D 0 && arm_el_is_aa64(env, new_el) !=3D return_to_aa64) { + /* Return to an EL which is configured for a different register wi= dth */ + goto illegal_return; + } + + if (new_el =3D=3D 2 && arm_is_secure_below_el3(env)) { + /* Return to the non-existent secure-EL2 */ + goto illegal_return; + } + + if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + goto illegal_return; + } + + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + if (!return_to_aa64) { + env->aarch64 =3D 0; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ + cpsr_write(env, spsr, ~0, CPSRWriteRaw); + if (!arm_singlestep_active(env)) { + env->uncached_cpsr &=3D ~PSTATE_SS; + } + aarch64_sync_64_to_32(env); + + if (spsr & CPSR_T) { + env->regs[15] =3D env->elr_el[cur_el] & ~0x1; + } else { + env->regs[15] =3D env->elr_el[cur_el] & ~0x3; + } + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch32 EL%d PC 0x%" PRIx32 "\n", + cur_el, new_el, env->regs[15]); + } else { + env->aarch64 =3D 1; + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &=3D ~PSTATE_SS; + } + aarch64_restore_sp(env, new_el); + env->pc =3D env->elr_el[cur_el]; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch64 EL%d PC 0x%" PRIx64 "\n", + cur_el, new_el, env->pc); + } + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); + + qemu_mutex_lock_iothread(); + arm_call_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + return; + +illegal_return: + /* Illegal return events of various kinds have architecturally + * mandated behaviour: + * restore NZCV and DAIF from SPSR_ELx + * set PSTATE.IL + * restore PC from ELR_ELx + * no change to exception level, execution state or stack pointer + */ + env->pstate |=3D PSTATE_IL; + env->pc =3D env->elr_el[cur_el]; + spsr &=3D PSTATE_NZCV | PSTATE_DAIF; + spsr |=3D pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &=3D ~PSTATE_SS; + } + qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " + "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc= ); +} + /* * Square Root and Reciprocal square root */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8b31c6a13b..c998eadfaa 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1029,161 +1029,6 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syn= drome) } } =20 -static int el_from_spsr(uint32_t spsr) -{ - /* Return the exception level that this SPSR is requesting a return to, - * or -1 if it is invalid (an illegal return) - */ - if (spsr & PSTATE_nRW) { - switch (spsr & CPSR_M) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_FIQ: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_SYS: - return 1; - case ARM_CPU_MODE_MON: - /* Returning to Mon from AArch64 is never possible, - * so this is an illegal return. - */ - default: - return -1; - } - } else { - if (extract32(spsr, 1, 1)) { - /* Return with reserved M[1] bit set */ - return -1; - } - if (extract32(spsr, 0, 4) =3D=3D 1) { - /* return to EL0 with M[0] bit set */ - return -1; - } - return extract32(spsr, 2, 2); - } -} - -void HELPER(exception_return)(CPUARMState *env) -{ - int cur_el =3D arm_current_el(env); - unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); - uint32_t spsr =3D env->banked_spsr[spsr_idx]; - int new_el; - bool return_to_aa64 =3D (spsr & PSTATE_nRW) =3D=3D 0; - - aarch64_save_sp(env, cur_el); - - arm_clear_exclusive(env); - - /* We must squash the PSTATE.SS bit to zero unless both of the - * following hold: - * 1. debug exceptions are currently disabled - * 2. singlestep will be active in the EL we return to - * We check 1 here and 2 after we've done the pstate/cpsr write() to - * transition to the EL we're going to. - */ - if (arm_generate_debug_exceptions(env)) { - spsr &=3D ~PSTATE_SS; - } - - new_el =3D el_from_spsr(spsr); - if (new_el =3D=3D -1) { - goto illegal_return; - } - if (new_el > cur_el - || (new_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2))) { - /* Disallow return to an EL which is unimplemented or higher - * than the current one. - */ - goto illegal_return; - } - - if (new_el !=3D 0 && arm_el_is_aa64(env, new_el) !=3D return_to_aa64) { - /* Return to an EL which is configured for a different register wi= dth */ - goto illegal_return; - } - - if (new_el =3D=3D 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - - if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - goto illegal_return; - } - - qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - if (!return_to_aa64) { - env->aarch64 =3D 0; - /* We do a raw CPSR write because aarch64_sync_64_to_32() - * will sort the register banks out for us, and we've already - * caught all the bad-mode cases in el_from_spsr(). - */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); - if (!arm_singlestep_active(env)) { - env->uncached_cpsr &=3D ~PSTATE_SS; - } - aarch64_sync_64_to_32(env); - - if (spsr & CPSR_T) { - env->regs[15] =3D env->elr_el[cur_el] & ~0x1; - } else { - env->regs[15] =3D env->elr_el[cur_el] & ~0x3; - } - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch32 EL%d PC 0x%" PRIx32 "\n", - cur_el, new_el, env->regs[15]); - } else { - env->aarch64 =3D 1; - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &=3D ~PSTATE_SS; - } - aarch64_restore_sp(env, new_el); - env->pc =3D env->elr_el[cur_el]; - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch64 EL%d PC 0x%" PRIx64 "\n", - cur_el, new_el, env->pc); - } - /* - * Note that cur_el can never be 0. If new_el is 0, then - * el0_a64 is return_to_aa64, else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); - - qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - return; - -illegal_return: - /* Illegal return events of various kinds have architecturally - * mandated behaviour: - * restore NZCV and DAIF from SPSR_ELx - * set PSTATE.IL - * restore PC from ELR_ELx - * no change to exception level, execution state or stack pointer - */ - env->pstate |=3D PSTATE_IL; - env->pc =3D env->elr_el[cur_el]; - spsr &=3D PSTATE_NZCV | PSTATE_DAIF; - spsr |=3D pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &=3D ~PSTATE_SS; - } - qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " - "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc= ); -} - /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987366246373.26912051875036; Tue, 8 Jan 2019 14:42:46 -0800 (PST) Received: from localhost ([127.0.0.1]:42383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh057-0001Pt-8H for importer@patchew.org; Tue, 08 Jan 2019 17:42:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzuz-0008Tw-F7 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzut-0004bH-KW for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:13 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:41596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzur-0004Yt-MG for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:11 -0500 Received: by mail-pf1-x430.google.com with SMTP id b7so2607721pfi.8 for ; Tue, 08 Jan 2019 14:32:06 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. 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X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 +- target/arm/helper-a64.c | 10 +++++----- target/arm/translate-a64.c | 7 ++++++- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 55299896c4..aff8d6c9f3 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,7 +86,7 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) =20 -DEF_HELPER_1(exception_return, void, env) +DEF_HELPER_2(exception_return, void, env, i64) =20 DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 66ff70dcdb..101fa6d3ea 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -925,7 +925,7 @@ static int el_from_spsr(uint32_t spsr) } } =20 -void HELPER(exception_return)(CPUARMState *env) +void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el =3D arm_current_el(env); unsigned int spsr_idx =3D aarch64_banked_spsr_index(cur_el); @@ -991,9 +991,9 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_sync_64_to_32(env); =20 if (spsr & CPSR_T) { - env->regs[15] =3D env->elr_el[cur_el] & ~0x1; + env->regs[15] =3D new_pc & ~0x1; } else { - env->regs[15] =3D env->elr_el[cur_el] & ~0x3; + env->regs[15] =3D new_pc & ~0x3; } qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env) env->pstate &=3D ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc =3D env->elr_el[cur_el]; + env->pc =3D new_pc; qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); @@ -1031,7 +1031,7 @@ illegal_return: * no change to exception level, execution state or stack pointer */ env->pstate |=3D PSTATE_IL; - env->pc =3D env->elr_el[cur_el]; + env->pc =3D new_pc; spsr &=3D PSTATE_NZCV | PSTATE_DAIF; spsr |=3D pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); pstate_write(env, spsr); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3f08db580b..2df2323646 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1981,6 +1981,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + TCGv_i64 dst; =20 opc =3D extract32(insn, 21, 4); op2 =3D extract32(insn, 16, 5); @@ -2011,7 +2012,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_helper_exception_return(cpu_env); + dst =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); + tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z8qLMJYEQtQI0+ZnJhB24wgZSIfyCc/5D6oRFz2V9go=; b=R3gXpTZSaiE8d5WYeOn4NMl16RDAmJb/j5qCZMxUSxnP5bBKR12WBx4637xdus7RZk Mpb2mq67BYTV0FMcFugQ8g04Iit8j1reCaX8W59X1YcLidTqQ1/7ue7vsjpjKjA5od7j z4jOAAw7XLEOXuWrDC3jdVBpW56TnxwoNRpwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z8qLMJYEQtQI0+ZnJhB24wgZSIfyCc/5D6oRFz2V9go=; b=EUGHbi5+G6L9Mp0pGTMj2X2U62V6HntYp+QeLwfOO9MDHVAJiPzBDAnsJxv1DwOvlM PVsyApPYcyT5iANk2K4busbudD7B6V0gNWY/fUSRBEhcCUTw7F2YDGUPBRE037ugU1MO IvseB2o5NeO/WdOLgbNusRb0Qgbw6vp4143W4UZWlVeYUPMccM+rtEW21oAVaVO9ltAF +DZL8IKIV6LFpMvAu+33EK6NLYgFgY7SGeITHAmRO8f7CrY09Dk5nF+PN+RpBQV5eB9v JGrRJdB3Ft4HWkIWmgsIoasJHuaA97/4tWFVuPvbKsE017ZK9Qtc1SpRrpl5YL04xIj2 /iZA== X-Gm-Message-State: AJcUukdGODhKFOBWrFbmfCcBSic1wGLbFbB1XUZHjoHTlMuoFp/2yacQ 624eTQRAznNR07TwYM6S5qjWprKebHc= X-Google-Smtp-Source: ALg8bN77o+K3/wjbhbE/sHM15bv/ckkQjMTGdocQmWojlLjcodACYbZOOGrsnJ2WthYlupQ5fQvr6g== X-Received: by 2002:a17:902:7107:: with SMTP id a7mr3575869pll.290.1546986727781; Tue, 08 Jan 2019 14:32:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:10 +1000 Message-Id: <20190108223129.5570-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 Subject: [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will enable PAuth decode in a subsequent patch. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 47 +++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2df2323646..e601753032 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1989,32 +1989,54 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) rn =3D extract32(insn, 5, 5); op4 =3D extract32(insn, 0, 5); =20 - if (op4 !=3D 0x0 || op3 !=3D 0x0 || op2 !=3D 0x1f) { - unallocated_encoding(s); - return; + if (op2 !=3D 0x1f) { + goto do_unallocated; } =20 switch (opc) { case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ - gen_a64_set_pc(s, cpu_reg(s, rn)); + switch (op3) { + case 0: + if (op4 !=3D 0) { + goto do_unallocated; + } + dst =3D cpu_reg(s, rn); + break; + + default: + goto do_unallocated; + } + + gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc =3D=3D 1) { tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } break; + case 4: /* ERET */ if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - return; + goto do_unallocated; + } + switch (op3) { + case 0: + if (op4 !=3D 0) { + goto do_unallocated; + } + dst =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + break; + + default: + goto do_unallocated; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - dst =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, - offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -2023,14 +2045,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return; + case 5: /* DRPS */ - if (rn !=3D 0x1f) { - unallocated_encoding(s); + if (op3 !=3D 0 || op4 !=3D 0 || rn !=3D 0x1f) { + goto do_unallocated; } else { unsupported_encoding(s, insn); } return; + default: + do_unallocated: unallocated_encoding(s); return; } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987560275433.75059922474327; Tue, 8 Jan 2019 14:46:00 -0800 (PST) Received: from localhost ([127.0.0.1]:43203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh089-0004dL-Qd for importer@patchew.org; Tue, 08 Jan 2019 17:45:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzv5-00009q-B0 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzv4-0004lD-D8 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:23 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34528) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzv3-0004b3-Gs for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:21 -0500 Received: by mail-pf1-x442.google.com with SMTP id h3so2625655pfg.1 for ; Tue, 08 Jan 2019 14:32:11 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WDCmraVytCVp2uFN73TTP/9xo07ZZ0ObLi7t4pJW3JA=; b=jXBE5C17wp/0FbJPVfp92h1OyAwVnbDKJzg4CA7KdrgYS0aF396XYH7OS4FoHiIw3O tmqxrC9mUL+MKx3OBGpsd/hcLEAHIZm/xxhmHT0EK75ZY1P4hZXOLEe6uxE5ObJpHDhx rVe1TTzylSkgXavjGoYqXEbaY816FY9m3eJfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WDCmraVytCVp2uFN73TTP/9xo07ZZ0ObLi7t4pJW3JA=; b=rHuhJ5K7HiYBPG1y8brVEhe5x3UbgKwBaktwfNKcvaAEi4Gl3fRrx/tC4qaRYlmy1G 7+IMFfWb6oWjwzekYZRbhnJ0cRceDbOhproyTz+1I14WfAJDWuj/LqxEtjyAY2GROT7V Mzcthk0tGuqJYeM8HrBPr+6Y/hR/62rUl6uz18/RCtnnOf8wXaYKHUYpO1rbAgDXqgY6 t/cicog1lSY+lS5tzsJec5m4K/lV943BqRkVMmEkahPi2+4Aakx5J4CTiBsg+vPvC5NF H3n47o+9+cg3UFS21P7CdhEcF8TPZpzfVQSGOpJHc3dUMr6Wlj9eyY0JBU0K+zCkkOKR Hl0g== X-Gm-Message-State: AJcUukdRj0O/tn85fDpze7HfeUkKHumwOxEBGfFPc1sBhP4u9qY6FTeE nJ3JnbRHB1UuxK/PWUi1xDn6Lqj33JI= X-Google-Smtp-Source: ALg8bN4LlN2e1ICkI68oRAou0tyU4si6uT1rQ77jIv5dW/8g3E28GBQyHvZJXregRoboRxAYMoRIHg== X-Received: by 2002:a62:2082:: with SMTP id m2mr3429485pfj.163.1546986730269; Tue, 08 Jan 2019 14:32:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:11 +1000 Message-Id: <20190108223129.5570-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e601753032..fa50003f0b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) { unsigned int opc, op2, op3, rn, op4; TCGv_i64 dst; + TCGv_i64 modifier; =20 opc =3D extract32(insn, 21, 4); op2 =3D extract32(insn, 16, 5); @@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) case 2: /* RET */ switch (op3) { case 0: + /* BR, BLR, RET */ if (op4 !=3D 0) { goto do_unallocated; } dst =3D cpu_reg(s, rn); break; =20 + case 2: + case 3: + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (opc =3D=3D 2) { + /* RETAA, RETAB */ + if (rn !=3D 0x1f || op4 !=3D 0x1f) { + goto do_unallocated; + } + rn =3D 30; + modifier =3D cpu_X[31]; + } else { + /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ + if (op4 !=3D 0x1f) { + goto do_unallocated; + } + modifier =3D new_tmp_a64_zero(s); + } + if (s->pauth_active) { + dst =3D new_tmp_a64(s); + if (op3 =3D=3D 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifie= r); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifie= r); + } + } else { + dst =3D cpu_reg(s, rn); + } + break; + default: goto do_unallocated; } @@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) } break; =20 + case 8: /* BRAA */ + case 9: /* BLRAA */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (op3 !=3D 2 || op3 !=3D 3) { + goto do_unallocated; + } + if (s->pauth_active) { + dst =3D new_tmp_a64(s); + modifier =3D cpu_reg_sp(s, op4); + if (op3 =3D=3D 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst =3D cpu_reg(s, rn); + } + gen_a64_set_pc(s, dst); + /* BLRAA also needs to load return address */ + if (opc =3D=3D 9) { + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + } + break; + case 4: /* ERET */ if (s->current_el =3D=3D 0) { goto do_unallocated; } switch (op3) { - case 0: + case 0: /* ERET */ if (op4 !=3D 0) { goto do_unallocated; } @@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) offsetof(CPUARMState, elr_el[s->current_el])); break; =20 + case 2: /* ERETAA */ + case 3: /* ERETAB */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (rn !=3D 0x1f || op4 !=3D 0x1f) { + goto do_unallocated; + } + dst =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + if (s->pauth_active) { + modifier =3D cpu_X[31]; + if (op3 =3D=3D 2) { + gen_helper_autia(dst, cpu_env, dst, modifier); + } else { + gen_helper_autib(dst, cpu_env, dst, modifier); + } + } + break; + default: goto do_unallocated; } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987560228979.9125899055837; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1DNhN8d8jnSLxAt0OunfVVewQ2O4L+Y8MHnesgNIMy4=; b=L5LtFTFlZsGzK5WpgpmYBFmenhtmlL86coAiOqKo/QqMhFZF0PnK7UIHe8Zyd55flN ksTnzYckT0VrF5b+ylxHmjwuFJODDTwJMOu4HIfsGO5TPyYV808sqjo6MRCDt6d3pCXl KU/21Vx+8nUafQt944yhukfPpe4f6YjWp0syk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1DNhN8d8jnSLxAt0OunfVVewQ2O4L+Y8MHnesgNIMy4=; b=S+qHL+LIqo+CcP0GBtvrYRzekbPztfsZTECFlYdScmRqYnVs0KpShVGlHBh9jMsYAC Pz+WIA0+ziuSSBwV429DDquzNdbn+ak9rC/QwYgzSCrWXwOf3XJv5TM9l8QZLbsBav+0 vQsXajzZLGKV8Wl+mEVTRgVQr1k03ghr+KwC8PyChXiEHT8DP07By3diVo5bO49J/3N5 0ZhfzhHmb4gVlUrE8r1PMOzy3e7h7CMAruHbHHvDr2sV+jR9tyW4ZV2yE0wlKHBRKE9E 8FYO8isk7bu4lMxkIPiuACn5UwlLEtzH/LBUKNi+epO1Wz5CGYCMKL96hdzT2TRYqaVn qYZQ== X-Gm-Message-State: AJcUukfOv/mZOcItNBhdwxS3svkAxCWOufMC9jad1Qsq/1V6bnoQUIrZ 0Uj/VcvqoYiCojWQBkXm9JMWGF3E/9E= X-Google-Smtp-Source: ALg8bN61lRuqfXL6flyjg6Z3iOvG5OdrfR6kmqA1JOciMpVTYAPNTUsUgWEOdAWvFX3UNpwtv4KxUQ== X-Received: by 2002:a63:2a4a:: with SMTP id q71mr3151394pgq.374.1546986733032; Tue, 08 Jan 2019 14:32:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:12 +1000 Message-Id: <20190108223129.5570-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Use do_gpr_ld; fix sextend typo; iss_valid only for !wback. --- target/arm/translate-a64.c | 60 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fa50003f0b..a4dfdf5836 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3146,6 +3146,63 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, s->be_data | size | MO_ALIGN); } =20 +/* PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+------------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn =3D extract32(insn, 5, 5); + bool is_wback =3D extract32(insn, 11, 1); + bool use_key_a =3D !extract32(insn, 23, 1); + int offset; + TCGv_i64 tcg_addr, tcg_rt; + + if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset =3D sextract32(offset << size, 0, 10 + size); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt =3D cpu_reg(s, rt); + + do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, + /* extend */ false, /* iss_valid */ !is_wback, + /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3171,6 +3228,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987764140796.6035750074011; Tue, 8 Jan 2019 14:49:24 -0800 (PST) Received: from localhost ([127.0.0.1]:44055 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0BX-000844-3q for importer@patchew.org; Tue, 08 Jan 2019 17:49:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzv7-0000Ch-AI for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzv5-0004mk-8d for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:25 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45110) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzv4-0004fC-KU for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:22 -0500 Received: by mail-pf1-x443.google.com with SMTP id g62so2595014pfd.12 for ; Tue, 08 Jan 2019 14:32:16 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NXvQI4SDFPXeWp0pGzcoDK8YDYSgU/rnRAlnBVBgc8Q=; b=kV6+cR9qojlCr2T+0XAYE0jTKLirEQLs5q+HbezOpDejbDOUjRQTVezJOXzOe3ZPkN BU5LiLQdheF9LYpDjb4iHyVBiOy5LePjJdMXklfBPdQ8xbU1TXElSQakQ9kTKEf7O8jD 3pVgQVOb+ylk600op1wfspah5k+0rWlqNFe2M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NXvQI4SDFPXeWp0pGzcoDK8YDYSgU/rnRAlnBVBgc8Q=; b=R4O+6CoNZY3HHGeb+WxLxMTnXylU5+wVmB4e+7wBPVO+lMFH5jgkTwNb5FjnPdK/S1 GRpGs2vHikFxgnzU0Zutazyr2xd3+VQRe7aYEq0v5e1qRHBfdTBv79Vn5OQmF1Tjq+3e 9l1O2PjRf4WDKyqlK30NUX0mQ3iRs8D8PlTLhlYHNI8Gz//hK2l7E2RbOyVrYNxDpP4U iPICgCSHQ+kGkSHhGGslTzCPUar308WgyhrCOpd0IpFQDxcpiEnvUW+nJfgVQbyx1ZLv lSzEKUjULG2uj71rtYbrj5Vaefvd4Nq30I9DQYvItsEJ9HVgGmzoBLAKBO/FckZZF0MJ hDjQ== X-Gm-Message-State: AJcUukegq5BlR60Bz2jBgGTZzZsFxLHq5hQhz2XTlhReR5qAsv6VTOcl jsZILFdL7GPE0M4jFv4mfXhX0ziZNVg= X-Google-Smtp-Source: ALg8bN7U722NskIW1AXd/zsUeT3btaWUJLP0mKxQoE/DnYEFH8POwFliZY48NlR6dGaGnYVjUZ+87Q== X-Received: by 2002:a62:d448:: with SMTP id u8mr3517798pfl.105.1546986735578; Tue, 08 Jan 2019 14:32:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:13 +1000 Message-Id: <20190108223129.5570-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 15/31] target/arm: Move cpu_mmu_index out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This function is, or will shortly become, too big to inline. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++++---------------------------------------- target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9ad7b2d11e..eb83a71b67 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2741,54 +2741,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_i= dx) } =20 /* Return the MMU index for a v7M CPU in the specified security and - * privilege state + * privilege state. */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState = *env, - bool secstat= e, - bool priv) -{ - ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |=3D ARM_MMU_IDX_M_PRIV; - } - - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |=3D ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |=3D ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); =20 /* Return the MMU index for a v7M CPU in the specified security state */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, - bool secstate) -{ - bool priv =3D arm_current_el(env) !=3D 0; - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 /* Determine the current mmu_idx to use for normal loads/stores */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - int el =3D arm_current_el(env); - - if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, env->v7m.s= ecure); - - return arm_to_core_mmu_idx(mmu_idx); - } - - if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); - } - return el; -} +int cpu_mmu_index(CPUARMState *env, bool ifetch); =20 /* Indexes used when registering address spaces with cpu_address_space_ini= t */ typedef enum ARMASIdx { diff --git a/target/arm/helper.c b/target/arm/helper.c index f23555b1dc..56d0b60b74 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |=3D ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |=3D ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |=3D ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv =3D arm_current_el(env) !=3D 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el =3D arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, env->v7m.s= ecure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987392618636.4272191997742; Tue, 8 Jan 2019 14:43:12 -0800 (PST) Received: from localhost ([127.0.0.1]:42489 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh05X-0001oo-H7 for importer@patchew.org; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/zabiqBD3w7s8c81oBx5z5thZaUzr5Ml+9EbpNixrdM=; b=d7XNEfIv6/yYZfm2/6ExFE2XJdzZsGWCDY3nnJr153uZI+97A5w1Ti3UADl9FaVMrW bh6bI1x+aZPsBKn7zwTsOaCDsvxV7IWjvhts7t2SY80et7X6pCXxdFo9HEW+j+F4R+8R ElzQwxh9xRoyFKamu86LvZUCCDTGaGlrnFJwA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/zabiqBD3w7s8c81oBx5z5thZaUzr5Ml+9EbpNixrdM=; b=gKXPv38l4NnjcQ0v+KueCVja4xRs5YBlvpFoPwYl7eqhJuwYZwZT6t5LMeYQEmQ3/Q +nXOIYVxd27NLP9LszS38Y6kES9ctnEy5R2VUUZ2ucYwo9mALkQ7OVD57dUDO5R1yR7d D9snvmngLFVnQvwSdxe+4T5bCWUApwSDFY+gyyj3FfDALwUbU4GlCjPuZ0oaT/08EeIe sII2bXzKab56yvS1PGWyASHIWD6QHSoE/byMlUA5KPw7PfpHpLBJlU0Yas5nz3YNhRNY KaQbyvjByvnvQXTdgBeAcF3jMl8++QZMaweJJsyxYnNFYzvbZ7zdA90b8W3Wdv7/xnTI Ud0g== X-Gm-Message-State: AJcUuke3mQoeRz5WhI41n9H3ut5bqx/l3nl/mhIdKnn/PEv/8DewAHss VnP6xJuAKCQDQowKaLSJKTMJB28ssaU= X-Google-Smtp-Source: ALg8bN4034DkosH1NAqxnGNgnGLEbEJaTpjO20vk+rIpIPZk1SwgTE/WmYrE5/0hW7OLmnuT0w9TuA== X-Received: by 2002:a62:47d9:: with SMTP id p86mr3431638pfi.95.1546986738053; Tue, 08 Jan 2019 14:32:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:14 +1000 Message-Id: <20190108223129.5570-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pattern ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Move arm_mmu_idx declaration to internals.h. --- target/arm/cpu.h | 9 ++++++++- target/arm/internals.h | 8 ++++++++ target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index eb83a71b67..c1d511f274 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2749,7 +2749,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUA= RMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 -/* Determine the current mmu_idx to use for normal loads/stores */ +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ int cpu_mmu_index(CPUARMState *env, bool ifetch); =20 /* Indexes used when registering address spaces with cpu_address_space_ini= t */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 0ed20c03cc..89f3b122a4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -919,4 +919,12 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_mmu_idx: + * @env: The cpu environment + * + * Return the full ARMMMUIdx for the current translation regime. + */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 56d0b60b74..ba6733c4f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32= _t lr, bool dotailchain, limit =3D env->v7m.msplim[M_REG_S]; } } else { - mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx =3D arm_mmu_idx(env); frame_sp_p =3D &env->regs[13]; limit =3D v7m_sp_limit(env); } @@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; uint32_t xpsr =3D xpsr_read(env); uint32_t frameptr =3D env->regs[13]; - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi =3D {}; - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 *attrs =3D (MemTxAttrs) {}; =20 @@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMStat= e *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } =20 -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el =3D arm_current_el(env); + int el; =20 if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, env->v7m.s= ecure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 + el =3D arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } =20 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); int current_el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, current_el); uint32_t flags =3D 0; --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XTiEnwJBlAE8O18axOe03GoQvcEB4gWvYODIP3nVaNY=; b=Veg11HCzEW8WRI1bc6Eik6grAS9diAQeqn5EJ4aHSs2CedP4Zen95Mg3+0j3dVcjIL OFh0etmeU3Y6u9V/WsfNJYYLS4YRuWLaWNCHWSrvh6+Zxyc79z8iqz9G5PP+VOvAE/pM /qt4n1eQkXlsJgBSJ8lggMfkwdly8mbpeJdrg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XTiEnwJBlAE8O18axOe03GoQvcEB4gWvYODIP3nVaNY=; b=LSV095JshuezQPGycQRC1Ia8Tf1YkQxx0Tjjyx8JeVka2U73UAL1nygBRPb/ZQSv7d mvu1TVEg+IUr7cXf4xBq6ECOSV0spBPr4fhq2yNUW3t1Wd6erNkFOjveBda0nIgaKWQs AjAdMvPUk09dksw4aYlt8lYHIJCNDWvtXSSNTlqx+EPsJnkXjHGvZX5Kf9Lj4GdXEafI ro8+Ht1tjlr5IV+asEgY6xavxO1Gbr/90SxilJ+QOvHsJLjZRCdLw8pQGYgsatxwsuMo dxuQ4TVBM/YxjIKj3hLMsTJLxeQZuGf2K6n/SZ82DXkt6B/8BFz86aPDR5HEmOwhlhbb 2X5Q== X-Gm-Message-State: AJcUukeK9dAoPmq+EYaZaFetX/lkJWEkD94Rig2xOS9+/xdzi7D9K5oi l3CsD+O8scOB2g9QJ3dBmNFzzIzq4J0= X-Google-Smtp-Source: ALg8bN6UeiAZCJK75/rmV2mMbMFpkzSj4T/wIB/OLIfEMORLV7oGK/ObgC12hRW6EOgEUeh4A3OSzQ== X-Received: by 2002:a63:1013:: with SMTP id f19mr3194300pgl.38.1546986740656; Tue, 08 Jan 2019 14:32:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:15 +1000 Message-Id: <20190108223129.5570-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 17/31] target/arm: Introduce arm_stage1_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While we could expose stage_1_mmu_idx, the combination is probably going to be more useful. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 +++++++++++++++ target/arm/helper.c | 7 +++++++ 2 files changed, 22 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 89f3b122a4..248fdf7a3c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -927,4 +927,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu); */ ARMMMUIdx arm_mmu_idx(CPUARMState *env); =20 +/** + * arm_stage1_mmu_idx: + * @env: The cpu environment + * + * Return the ARMMMUIdx for the stage1 traversal for the current regime. + */ +#ifdef CONFIG_USER_ONLY +static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return ARMMMUIdx_S1NSE0; +} +#else +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index ba6733c4f1..4af8abd18f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12998,6 +12998,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch) return arm_to_core_mmu_idx(arm_mmu_idx(env)); } =20 +#ifndef CONFIG_USER_ONLY +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return stage_1_mmu_idx(arm_mmu_idx(env)); +} +#endif + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987579224558.9813431792041; Tue, 8 Jan 2019 14:46:19 -0800 (PST) Received: from localhost ([127.0.0.1]:43295 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh08S-00050z-8g for importer@patchew.org; Tue, 08 Jan 2019 17:46:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52810) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvA-0000J3-U0 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzv9-0004rG-BJ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:28 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:33304) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzv7-0004o2-T1 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:27 -0500 Received: by mail-pg1-x543.google.com with SMTP id z11so2376064pgu.0 for ; Tue, 08 Jan 2019 14:32:24 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5Y1f2Ah2ro2iLFV8pn6+8bjx8cENN0ztZ1gZEE2M3yw=; b=E4zDDBoxwm9GmotDtDzp/GVjqPkhO/PWIoZJxouX4VMVTGkxqaCrWz7SCnkqOUV4WN SsmlHibpvK/BwJ+fxJ9fSck7PKkRxHA03UiSFSMtZlaa+9JC4+jeTBpx8o/J5ht0gG8Q 5A2lPI6B7ihV/ogMbbV91nLpmAIty7bASAClk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5Y1f2Ah2ro2iLFV8pn6+8bjx8cENN0ztZ1gZEE2M3yw=; b=n4CQ5tHVXCSVPbmctymCsk8TpdeOH1W8oa3aCD8CONufpZcekOPXsDUVhRK+Yv4frv EAOsgIsLjBXeGpKvIAS1jGAK0m70XTeu36PQiwG8W5y6aWHbcJdX3FgfeiqF+UAdtWn2 uV2XxZpkAL9zNQfygPBOf7GkBVarmWDC92qM18tuKasN2G3F/ykoVnwmNuZOzE3PXt6f gl8FSztY2USyKrIrcaPmLsLmlkbxcOZRcCabSwmCeg1FTx1b7ZvGnSzrqvcnN7/YJvng 7SUFfxuR8fKBIEbpOs5qt74yqUSlkNxOpcD75brqw3XEb2vwMTskx9z5Ivny7IfoifE8 GlCQ== X-Gm-Message-State: AJcUukckAhnwR3xV+h88HlbDvD89xDnaoyXX+No4eaO3B3/Mg/1KbqD0 mH3BuErt0lzNZF1FhHFGUFAvTJ/Ghr8= X-Google-Smtp-Source: ALg8bN5UV13B7KV3hhS31TXzqB8ZopFUlIjqM/tShK6mGE5VT5wE1isTkmZNKWI8UxLPeLpHXueSLg== X-Received: by 2002:a63:f552:: with SMTP id e18mr3182248pgk.239.1546986743262; Tue, 08 Jan 2019 14:32:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:16 +1000 Message-Id: <20190108223129.5570-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 18/31] target/arm: Create ARMVAParameters and helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell ---- v2: Incorporate feedback wrt VTCR, HTCR, and more. v3: Remove TBID, HA, HD from this patch. --- target/arm/internals.h | 14 +++ target/arm/helper.c | 275 ++++++++++++++++++++++------------------- 2 files changed, 161 insertions(+), 128 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 248fdf7a3c..fdda2c866a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -942,4 +942,18 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState= *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif =20 +/* + * Parameters of a given virtual address, as extracted from the + * translation control register (TCR) for a given regime. + */ +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 4af8abd18f..5ee8761111 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,6 +9744,122 @@ static uint8_t convert_stage2_attrs(CPUARMState *en= v, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } =20 +static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el =3D regime_el(env, mmu_idx); + bool tbi, epd, hpd, using16k, using64k; + int select, tsz; + + /* Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select =3D extract64(va, 55, 1); + + if (el > 1) { + tsz =3D extract32(tcr, 0, 6); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + /* VTCR_EL2 */ + tbi =3D hpd =3D false; + } else { + tbi =3D extract32(tcr, 20, 1); + hpd =3D extract32(tcr, 24, 1); + } + epd =3D false; + } else if (!select) { + tsz =3D extract32(tcr, 0, 6); + epd =3D extract32(tcr, 7, 1); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + tbi =3D extract64(tcr, 37, 1); + hpd =3D extract64(tcr, 41, 1); + } else { + int tg =3D extract32(tcr, 30, 2); + using16k =3D tg =3D=3D 1; + using64k =3D tg =3D=3D 3; + tsz =3D extract32(tcr, 16, 6); + epd =3D extract32(tcr, 23, 1); + tbi =3D extract64(tcr, 38, 1); + hpd =3D extract64(tcr, 42, 1); + } + tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + + return (ARMVAParameters) { + .tsz =3D tsz, + .select =3D select, + .tbi =3D tbi, + .epd =3D epd, + .hpd =3D hpd, + .using16k =3D using16k, + .using64k =3D using64k, + }; +} + +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el =3D regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + /* VTCR */ + bool sext =3D extract32(tcr, 4, 1); + bool sign =3D extract32(tcr, 3, 1); + + /* If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign !=3D sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz =3D sextract32(tcr, 0, 4) + 8; + select =3D 0; + hpd =3D false; + epd =3D false; + } else if (el =3D=3D 2) { + /* HTCR */ + tsz =3D extract32(tcr, 0, 3); + select =3D 0; + hpd =3D extract64(tcr, 24, 1); + epd =3D false; + } else { + int t0sz =3D extract32(tcr, 0, 3); + int t1sz =3D extract32(tcr, 16, 3); + + if (t1sz =3D=3D 0) { + select =3D va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select =3D va >=3D ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz =3D t0sz; + epd =3D extract32(tcr, 7, 1); + hpd =3D extract64(tcr, 41, 1); + } else { + tsz =3D t1sz; + epd =3D extract32(tcr, 23, 1); + hpd =3D extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &=3D extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz =3D tsz, + .select =3D select, + .epd =3D epd, + .hpd =3D hpd, + }; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, @@ -9755,26 +9871,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type =3D ARMFault_Translation; uint32_t level; - uint32_t epd =3D 0; - int32_t t0sz, t1sz; - uint32_t tg; + ARMVAParameters param; uint64_t ttbr; - int ttbr_select; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + target_ulong page_size, top_bits; uint32_t attrs; - int32_t stride =3D 9; - int32_t addrsize; - int inputsize; - int32_t tbi =3D 0; + int32_t stride; + int addrsize, inputsize; TCR *tcr =3D regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); - bool ttbr1_valid =3D true; + bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); - bool hpd =3D false; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9783,91 +9893,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, * support for those page table walks. */ if (aarch64) { + param =3D aa64_va_parameters(env, address, mmu_idx, + access_type !=3D MMU_INST_FETCH); level =3D 0; - addrsize =3D 64; - if (el > 1) { - if (mmu_idx !=3D ARMMMUIdx_S2NS) { - tbi =3D extract64(tcr->raw_tcr, 20, 1); - } - } else { - if (extract64(address, 55, 1)) { - tbi =3D extract64(tcr->raw_tcr, 38, 1); - } else { - tbi =3D extract64(tcr->raw_tcr, 37, 1); - } - } - tbi *=3D 8; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark = it * invalid. */ - if (el > 1) { - ttbr1_valid =3D false; - } + ttbr1_valid =3D (el < 2); + addrsize =3D 64 - 8 * param.tbi; + inputsize =3D 64 - param.tsz; } else { + param =3D aa32_va_parameters(env, address, mmu_idx); level =3D 1; - addrsize =3D 32; /* There is no TTBR1 for EL2 */ - if (el =3D=3D 2) { - ttbr1_valid =3D false; - } + ttbr1_valid =3D (el !=3D 2); + addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_S2NS ? 40 : 32); + inputsize =3D addrsize - param.tsz; } =20 - /* Determine whether this address is in the region controlled by - * TTBR0 or TTBR1 (or if it is in neither region and should fault). - * This is a Non-secure PL0/1 stage 1 translation, so controlled by - * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: + /* We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. + * Extract the top bits and verify that they all match select. */ - if (aarch64) { - /* AArch64 translation. */ - t0sz =3D extract32(tcr->raw_tcr, 0, 6); - t0sz =3D MIN(t0sz, 39); - t0sz =3D MAX(t0sz, 16); - } else if (mmu_idx !=3D ARMMMUIdx_S2NS) { - /* AArch32 stage 1 translation. */ - t0sz =3D extract32(tcr->raw_tcr, 0, 3); - } else { - /* AArch32 stage 2 translation. */ - bool sext =3D extract32(tcr->raw_tcr, 4, 1); - bool sign =3D extract32(tcr->raw_tcr, 3, 1); - /* Address size is 40-bit for a stage 2 translation, - * and t0sz can be negative (from -8 to 7), - * so we need to adjust it to use the TTBR selecting logic below. - */ - addrsize =3D 40; - t0sz =3D sextract32(tcr->raw_tcr, 0, 4) + 8; - - /* If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. */ - if (sign !=3D sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - } - t1sz =3D extract32(tcr->raw_tcr, 16, 6); - if (aarch64) { - t1sz =3D MIN(t1sz, 39); - t1sz =3D MAX(t1sz, 16); - } - if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { - /* there is a ttbr0 region and we are in it (high bits all zero) */ - ttbr_select =3D 0; - } else if (ttbr1_valid && t1sz && - !extract64(~address, addrsize - t1sz, t1sz - tbi)) { - /* there is a ttbr1 region and we are in it (high bits all one) */ - ttbr_select =3D 1; - } else if (!t0sz) { - /* ttbr0 region is "everything not in the ttbr1 region" */ - ttbr_select =3D 0; - } else if (!t1sz && ttbr1_valid) { - /* ttbr1 region is "everything not in the ttbr0 region" */ - ttbr_select =3D 1; - } else { - /* in the gap between the two regions, this is a Translation fault= */ + top_bits =3D sextract64(address, inputsize, addrsize - inputsize); + if (-top_bits !=3D param.select || (param.select && !ttbr1_valid)) { + /* In the gap between the two regions, this is a Translation fault= */ fault_type =3D ARMFault_Translation; goto do_fault; } =20 + if (param.using64k) { + stride =3D 13; + } else if (param.using16k) { + stride =3D 11; + } else { + stride =3D 9; + } + /* Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the @@ -9875,56 +9937,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ - if (ttbr_select =3D=3D 0) { - ttbr =3D regime_ttbr(env, mmu_idx, 0); - if (el < 2) { - epd =3D extract32(tcr->raw_tcr, 7, 1); - } - inputsize =3D addrsize - t0sz; - - tg =3D extract32(tcr->raw_tcr, 14, 2); - if (tg =3D=3D 1) { /* 64KB pages */ - stride =3D 13; - } - if (tg =3D=3D 2) { /* 16KB pages */ - stride =3D 11; - } - if (aarch64 && el > 1) { - hpd =3D extract64(tcr->raw_tcr, 24, 1); - } else { - hpd =3D extract64(tcr->raw_tcr, 41, 1); - } - if (!aarch64) { - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &=3D extract64(tcr->raw_tcr, 6, 1); - } - } else { - /* We should only be here if TTBR1 is valid */ - assert(ttbr1_valid); - - ttbr =3D regime_ttbr(env, mmu_idx, 1); - epd =3D extract32(tcr->raw_tcr, 23, 1); - inputsize =3D addrsize - t1sz; - - tg =3D extract32(tcr->raw_tcr, 30, 2); - if (tg =3D=3D 3) { /* 64KB pages */ - stride =3D 13; - } - if (tg =3D=3D 1) { /* 16KB pages */ - stride =3D 11; - } - hpd =3D extract64(tcr->raw_tcr, 42, 1); - if (!aarch64) { - /* For aarch32, hpd1 is not enabled without t2e as well. */ - hpd &=3D extract64(tcr->raw_tcr, 6, 1); - } - } + ttbr =3D regime_ttbr(env, mmu_idx, param.select); =20 /* Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ =20 - if (epd) { + if (param.epd) { /* Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. */ @@ -10037,7 +10056,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, } /* Merge in attributes from table descriptors */ attrs |=3D nstable << 3; /* NS */ - if (hpd) { + if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; } --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987959062552.3541886120041; Tue, 8 Jan 2019 14:52:39 -0800 (PST) Received: from localhost ([127.0.0.1]:44879 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0Ef-0002pP-Ul for importer@patchew.org; Tue, 08 Jan 2019 17:52:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvA-0000IT-Fo for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzv9-0004rb-GZ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:28 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:41155) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzv9-0004q7-AT for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:27 -0500 Received: by mail-pg1-x541.google.com with SMTP id m1so2357065pgq.8 for ; Tue, 08 Jan 2019 14:32:26 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wmwmyBe+39serfWjlr1w69S1eK6hJM8LpCs3XyG58Yg=; b=HEM+oTc4ZTBKxIY0LLL+TKW3jY0vgBBixo6iWcpy6ms+Qy08edwdCZZapdYQAe0dKA j/04ltZAISNFx4YYoQvzCNTaUPiXfENHHMCIzfahPtLgk5TtPlzrrxjzXD0PBgIxvBiM aRzss6vvw1H3MGKhExVBbkqElAI5f3xF0GxvM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wmwmyBe+39serfWjlr1w69S1eK6hJM8LpCs3XyG58Yg=; b=YQurFRnw8XGePXMdp0ijXVe0t1LwIzRucb5Ft72DXkAr0+ZDgM0qpJf0jq5u2tpquy oKY3dM3skON/gy5DmbHuivojCgEyelciYUiJPqhY4dp0IcCfbUoYDaD9OZA1UnhpzqKW CpP2ah+KLPZal2/OVnlOQc3BCfHKngF1k30Rg/8gr7XkPBFNmJf34MbtF2zQdi7quapL Xmhig22dbEw3Glrudhfc2JMFUui8U8FXRzdV+scLPLzoyKZmDuM1trrYe0WKiqsnQzc+ gMHBBDYniqdWyJU6W3QI9IJIsR3OiHD14rJtGPHlnUzOkSbz+bUd3CYJlk5ubYrNCTok KCWg== X-Gm-Message-State: AJcUukcBc4EDiepkZgw784zq4yzV4lCu+mOKZzGMoCgXVEWSqEpTAIeP bNbW4g8yXzM0LFo8tbqGI2bXK734zb8= X-Google-Smtp-Source: ALg8bN5YXmx7EkDiiRNttRCqitUgVWopGsUIuuGbB6kYbfD4AL9sMYtka6zYs+Db5DlecYUDgZ5NEg== X-Received: by 2002:a62:3141:: with SMTP id x62mr3510607pfx.12.1546986745808; Tue, 08 Jan 2019 14:32:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:17 +1000 Message-Id: <20190108223129.5570-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 19/31] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell ---- v3: New, split out of a later patch set. --- target/arm/cpu.h | 3 +-- target/arm/translate.h | 3 +-- target/arm/helper.c | 5 ++--- target/arm/translate-a64.c | 13 +++++++------ 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1d511f274..ea9b8ec4a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2979,8 +2979,7 @@ FIELD(TBFLAG_A32, HANDLER, 21, 1) FIELD(TBFLAG_A32, STACKCHECK, 22, 1) =20 /* Bit usage when in AArch64 state */ -FIELD(TBFLAG_A64, TBI0, 0, 1) -FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) diff --git a/target/arm/translate.h b/target/arm/translate.h index d8a8bb4e9c..bb37d35741 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,8 +26,7 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */ - bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ee8761111..f934c80c28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13038,10 +13038,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI0, + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, + (arm_regime_tbi1(env, mmu_idx) << 1) | arm_regime_tbi0(env, mmu_idx)); - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI1, - arm_regime_tbi1(env, mmu_idx)); =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a4dfdf5836..ee92533469 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -276,13 +276,15 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + /* Note that TBII is TBI1:TBI0. */ + int tbi =3D s->tbii; =20 if (s->current_el <=3D 1) { /* Test if NEITHER or BOTH TBI values are set. If so, no need to * examine bit 55 of address, can just generate code. * If mixed, then test via generated code */ - if (s->tbi0 && s->tbi1) { + if (tbi =3D=3D 3) { TCGv_i64 tmp_reg =3D tcg_temp_new_i64(); /* Both bits set, sign extension from bit 55 into [63:56] will * cover both cases @@ -290,7 +292,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) tcg_gen_shli_i64(tmp_reg, src, 8); tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { + } else if (tbi =3D=3D 0) { /* Neither bit set, just load it as-is */ tcg_gen_mov_i64(cpu_pc, src); } else { @@ -300,7 +302,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) =20 tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); =20 - if (s->tbi0) { + if (tbi =3D=3D 1) { /* tbi0=3D=3D1, tbi1=3D=3D0, so 0-fill upper byte if bit 5= 5 =3D 0 */ tcg_gen_andi_i64(tcg_tmpval, src, 0x00FFFFFFFFFFFFFFull); @@ -318,7 +320,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) tcg_temp_free_i64(tcg_tmpval); } } else { /* EL > 1 */ - if (s->tbi0) { + if (tbi !=3D 0) { /* Force tag byte to all zero */ tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); } else { @@ -13806,8 +13808,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->condexec_cond =3D 0; core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); - dc->tbi0 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); - dc->tbi1 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); + dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987794880441.5814086870407; Tue, 8 Jan 2019 14:49:54 -0800 (PST) Received: from localhost ([127.0.0.1]:44185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0C1-00007N-Qt for importer@patchew.org; Tue, 08 Jan 2019 17:49:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvC-0000LZ-Fa for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvB-0004ue-OU for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:30 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:42419) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvB-0004ts-Iv for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:29 -0500 Received: by mail-pl1-x642.google.com with SMTP id y1so2559686plp.9 for ; Tue, 08 Jan 2019 14:32:29 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HtgD2kb0Tk4a5mvvgc/yTa4iLNXqbugMtAKVtQjNC/Y=; b=W/gcyjNTMpSJSCNGPMjfy1gRASXkpVNNpsxZ91KQPRAiPcD3xEe6H1TeFva2V8/vR/ JopoWG1vqgLRzHW25ik/F+5L5jpPC5REHThunmYbZ0t2wHX8PSC2ak0w5SHGatam25be PkJsaLvoH+RhOkZDv247k44IRpjro5CxZvQ9k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HtgD2kb0Tk4a5mvvgc/yTa4iLNXqbugMtAKVtQjNC/Y=; b=dO/VOUZBswzmP/bhJc25LCrXTW7rnkDtCR+Ypbn2MawdG+BbmuIV8mFhVh2y36UkV4 eT8cNo9zTYE49JGp4a7+zUeyKtQkyrMW0xi8wWoMo5hqVvPJgbI+OOfwIPKk1dt75Irt 02xy/5Y/FhJ23MiMFcID9iGwRLtY8EpSyQ1B/pFG+EZb/G+aN4kBmVSh3oTPRLfJaUaj 4/W0PxhaHMjoFoo180k/4AbeEOBxH4P9WhGgfcd4t16Ut9nQrngz8/mujCmMCvO9pESj yFz+KMz/KFhjo7YSax3TqUIjSL4+pEtZ7vif32IX+KdVnK4h7qWdDlP+7D9mKfo7AxAH ES5A== X-Gm-Message-State: AJcUukew5EIjOLfvnzmT2R4k0URhwAyTfWfB/LAcqnZPiro3NRUrayEe /+Pgz1aNYgN7mlj89hmd+IzjkkaOrPU= X-Google-Smtp-Source: ALg8bN4JuscTo8xoq8MfRB6ZFP3udIoXC3+civN+ApZlOQrOCYwImNchQZPE1HZEs9EjzEWblH8jFA== X-Received: by 2002:a17:902:9a81:: with SMTP id w1mr3434700plp.19.1546986748327; Tue, 08 Jan 2019 14:32:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:18 +1000 Message-Id: <20190108223129.5570-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 20/31] target/arm: Export aa64_va_parameters to internals.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fdda2c866a..82cf685695 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -956,4 +956,21 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; =20 +#ifdef CONFIG_USER_ONLY +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool d= ata) +{ + return (ARMVAParameters) { + /* 48-bit address space */ + .tsz =3D 16, + /* We can't handle tagged addresses properly in user-only mode */ + .tbi =3D false, + }; +} +#else +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f934c80c28..f4538c9f82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,8 +9744,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env,= uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } =20 -static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el =3D regime_el(env, mmu_idx); --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546988135064407.8882801188088; Tue, 8 Jan 2019 14:55:35 -0800 (PST) Received: from localhost ([127.0.0.1]:45661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0HW-0005r3-0P for importer@patchew.org; Tue, 08 Jan 2019 17:55:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvF-0000P5-9e for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvE-0004xk-He for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:33 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45183) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvE-0004x5-By for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:32 -0500 Received: by mail-pg1-x541.google.com with SMTP id y4so2343324pgc.12 for ; Tue, 08 Jan 2019 14:32:32 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jm0q4VrYesXT+1aKV7gHpLk65YgMU1hEIfu+1DhEv/c=; b=WMtx8eMW2AHj0ZMaV3Cpc/+FQw6m91bFOE7+VuwQIl+sbqjLq9+o25PqWPdQyr+qut 1ZEMQ3IsimLdDqEDi0f6J6CefAl7x6OVDUoWmB719JGQ6mb5/74XWvAva73HUC5RNbP3 nbMayOMZMV91W1PFJS4PeCbFKRXmeTSuuWqdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jm0q4VrYesXT+1aKV7gHpLk65YgMU1hEIfu+1DhEv/c=; b=M0dkomZmrQuDc09HK7Fda7tQypR4aPHizkhSSZGN1CkDl0kLW55fvZ9dRONC+j0Ppn JLWNOdQyZQVmD4Wtd7UpLN0jnm/PHQRhBM08kyiZZnC1Yk1TR8LFzZFbSWY20agmNO5j ocA2axPI6C9NEPzRSLtGxEOsExlvtvedACztQqaw8O7k/kwODSBMTm0JqGs2BY+0MyKO 6QalWTHaUOSD1B1f6qvZiuRbf4barXVO85PsnzxtcrrZT50lXO8KqGStjAPNL+RVu6Og SwTrNxNPOPOpVifcIEboPT2VNs8NzDpqSQ8070fhaYvTCzR+LFn92PGBQojlxCorzCtp BJ7Q== X-Gm-Message-State: AJcUukex0H/EVsJ8HbxZLVW/jp/Hn7XbrkInxd/Ao0mBQBsHuHV4R9lL jb+YrX2iyNj6geSzoXVl6NoBX2xODo8= X-Google-Smtp-Source: ALg8bN5KutrBPgPLVShQsk7oCQt7K9jioLYqnUa+xmD4jIUgkRdGRwHUTfzWfsNkHrdR55ovZfvEkg== X-Received: by 2002:a63:2d46:: with SMTP id t67mr3216839pgt.140.1546986751013; Tue, 08 Jan 2019 14:32:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:19 +1000 Message-Id: <20190108223129.5570-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will want to check TBI for I and D simultaneously. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 15 ++++++++++++--- target/arm/helper.c | 10 ++++++++-- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 82cf685695..acd99b579c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -957,9 +957,9 @@ typedef struct ARMVAParameters { } ARMVAParameters; =20 #ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool d= ata) +static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx) { return (ARMVAParameters) { /* 48-bit address space */ @@ -968,7 +968,16 @@ static inline ARMVAParameters aa64_va_parameters(CPUAR= MState *env, .tbi =3D false, }; } + +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool d= ata) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} #else +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f4538c9f82..28322ae109 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,8 +9744,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env,= uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } =20 -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el =3D regime_el(env, mmu_idx); @@ -9799,6 +9799,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, }; } =20 +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546988309003297.04762217465895; Tue, 8 Jan 2019 14:58:29 -0800 (PST) Received: from localhost ([127.0.0.1]:46505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0KK-0000d7-0a for importer@patchew.org; Tue, 08 Jan 2019 17:58:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvH-0000RG-Qa for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvH-00050K-0g for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:35 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvG-0004zS-QW for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:34 -0500 Received: by mail-pf1-x441.google.com with SMTP id c123so2630570pfb.0 for ; Tue, 08 Jan 2019 14:32:34 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y+pdCEdbsU3nNMbRtt2E6v/yS6MnA/Ob8unhe6A5OEI=; b=D/9zyi+kGlPQG0+qzVrztVcZXsKMlhFoLRoTPvLcaXTZnDCnGJqCpPtG/KdiPq29ny O9WRD5tJCKoeWkEDZcR08+ge/y5R4zc6nmaxHlEksSzdENJ82Hl20AtNdyJII2PmqIve PgXADgRbIBhUBKh1qDxoEvBVKrzZ/+CSQj7J8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y+pdCEdbsU3nNMbRtt2E6v/yS6MnA/Ob8unhe6A5OEI=; b=c3Z/bQ9cAWbiOU6pskqDPYts5+kTadKracYO5ObVDXbksSL0GmLZUcuYrA5PQquRpJ GWhoiR+U5SaGMLxI2wouO8WfBmwl2H8nlhbq47UNSgvJiHKmZlI59egel5rpkjc5Pn9Y 5lruM/tQVp+35Tmf5g/9y+xOLa0xcW7VLAfJ2QFq1dlPYPfnfrnv9obcsQz4OXKvd/Lk Q+dV82xJSPOpE2f+kqxs/Zs8TnL03Kq3gHdS57LLWM1RKMD3VkgKX0dSohY4i3AHvNMz lDhMG8qKY5faRhcBJQqR+Vk1RHcQT29Qx+uP+fZ/+adWaxqbQHXfAqE/zWaowqYfLya1 8sTQ== X-Gm-Message-State: AJcUukc9aFGNANEjii+NG2QsJBoTjKAJhIhF1ytx/n4cO5ne57qOA7J9 pOlexK2NfMNzG9tYFZUhqJWWlA7SGgE= X-Google-Smtp-Source: ALg8bN5juqOmZ5iP5hWTVi70Pyi/1Bil8cR8/uwOGXS/pEGR4N94OIhHrlyW2fOAy1HrnKCFsZ7doA== X-Received: by 2002:a62:140a:: with SMTP id 10mr3444846pfu.157.1546986753592; Tue, 08 Jan 2019 14:32:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:20 +1000 Message-Id: <20190108223129.5570-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 22/31] target/arm: Decode TBID from TCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use TBID in aa64_va_parameters depending on the data parameter. This automatically updates all existing users of the function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 1 + target/arm/helper.c | 14 +++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index acd99b579c..a6fd4582b2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -950,6 +950,7 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; + bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28322ae109..cc3c0d47c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9749,7 +9749,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el =3D regime_el(env, mmu_idx); - bool tbi, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 /* Bit 55 is always between the two regions, and is canonical for @@ -9763,10 +9763,11 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi =3D hpd =3D false; + tbi =3D tbid =3D hpd =3D false; } else { tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); + tbid =3D extract32(tcr, 29, 1); } epd =3D false; } else if (!select) { @@ -9776,6 +9777,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, using16k =3D extract32(tcr, 15, 1); tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); + tbid =3D extract64(tcr, 51, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; @@ -9784,6 +9786,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, epd =3D extract32(tcr, 23, 1); tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); + tbid =3D extract64(tcr, 52, 1); } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -9792,6 +9795,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, .tsz =3D tsz, .select =3D select, .tbi =3D tbi, + .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, .using16k =3D using16k, @@ -9802,7 +9806,11 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState = *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - return aa64_va_parameters_both(env, va, mmu_idx); + ARMVAParameters ret =3D aa64_va_parameters_both(env, va, mmu_idx); + + /* Present TBI as a composite with TBID. */ + ret.tbi &=3D (data || !ret.tbid); + return ret; } =20 static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154698727665217.329060885483955; Tue, 8 Jan 2019 14:41:16 -0800 (PST) Received: from localhost ([127.0.0.1]:41983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh03f-0008HV-Ga for importer@patchew.org; Tue, 08 Jan 2019 17:41:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvK-0000UT-DE for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvJ-00053Y-F8 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:38 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38112) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvJ-00052m-8M for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:37 -0500 Received: by mail-pl1-x643.google.com with SMTP id e5so2564207plb.5 for ; Tue, 08 Jan 2019 14:32:37 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x4CNbPTPbLbD5OUpnvxNmBSc1i8+hDI/XOOOW1xKo9M=; b=bh2NdUAuWjlPasMBVlhc2XOTtxmAr91Vd6TxMNxGLB5e31n2gVatzFpxnanUd9TU3g JtvnQQrtUAaDo9AooSw9B/FUrHGCX0UgeycdLN0nuEGxu6g+8LK8QSDi5E5JanPaWJ43 XzPRuC/t3+2dz/psBojt9191xQvqSg2vvmvjM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x4CNbPTPbLbD5OUpnvxNmBSc1i8+hDI/XOOOW1xKo9M=; b=dJ2eoXoN6CNgb9BqPcSNq0xOJDihgriQw7aCF1RpW8NT0es/5wpa67XOT3MgL8pOBn yP3ZnUsfvaX1KXuJkVUmcGFAz5AIJ0yp3YqBY52x1d1p6Y6x5ko7SYWvjdmn/c14/+Vv bZFve8ab0PKOjOU582jvC3IXDkj8PcKbHV+iOEv5aQcDnlNq20XBJVaHBWvd58g3DMyL htclL+Ula3E45GxJc6xROQq5EyeVwkrj9WhKv85uE1m5pHKWoU8TgCKn57yymloeECiv jVsrziqPlSgtoMTubBHr7HF28t2QM2nCMW51GfSuPNOZiAo3rUBhzj/pSuh3N2xS2aOf CG9Q== X-Gm-Message-State: AJcUukdDoo1JQmWrBp+1CFrG0+h7antoqgs0DRPG6tG6+IQPpCMnSP+Z 9sXneYnXa5FB3pCye65mYEuLhEoe0CY= X-Google-Smtp-Source: ALg8bN6egf05w1YlSpV8w1zlt0NQ0aAsv+lYG/dYgc5E/5rcqDfSLUH/xDuqvp583oShsgy6Bgiv2A== X-Received: by 2002:a17:902:2bc5:: with SMTP id l63mr3618103plb.107.1546986755992; Tue, 08 Jan 2019 14:32:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:21 +1000 Message-Id: <20190108223129.5570-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 23/31] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use aa64_va_parameters_both and compute both tbii and tbid. Merged back from a later patch set. --- target/arm/cpu.h | 35 ----------------------- target/arm/helper.c | 70 ++++++++++++++++----------------------------- 2 files changed, 24 insertions(+), 81 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea9b8ec4a1..8512ca3552 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3015,41 +3015,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *e= nv) } #endif =20 -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index cc3c0d47c8..e610155166 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mm= u_idx) return mmu_idx; } =20 -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13051,10 +13009,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - /* Get control bits for tagged addresses */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, - (arm_regime_tbi1(env, mmu_idx) << 1) | - arm_regime_tbi0(env, mmu_idx)); + +#ifndef CONFIG_USER_ONLY + /* + * Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + { + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + int tbii, tbid; + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, st= age1); + tbid =3D (p1.tbi << 1) | p0.tbi; + tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid =3D p0.tbi; + tbii =3D tbid & !p0.tbid; + } + + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + } +#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987962417966.4425113481889; Tue, 8 Jan 2019 14:52:42 -0800 (PST) Received: from localhost ([127.0.0.1]:44893 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0Ej-0002tQ-D6 for importer@patchew.org; Tue, 08 Jan 2019 17:52:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvM-0000XJ-U7 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvM-00058E-4N for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:40 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:43739) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvL-000566-VF for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:40 -0500 Received: by mail-pf1-x441.google.com with SMTP id w73so2598965pfk.10 for ; Tue, 08 Jan 2019 14:32:39 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mg19AKP3OnF6DGhhumbtnC9AwmLPjVNrmPOLEIDNGYE=; b=HjSM/PXym7fby4wIImpBNu78npnJohRW1tov/pyU9JZagm7ZabIiqjLD5xmPTgObnj w49BEGqYRBF4KgdnsJvJTLAXLobB43Yaz6PZzYf1w7Ys8j1WnuO9pP10BeJTmsKEJ1g0 HDTbJxhhbqSYR9kKy+aQle/XJjbzh6jkojPx0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mg19AKP3OnF6DGhhumbtnC9AwmLPjVNrmPOLEIDNGYE=; b=b4rIPs1DuhSBYiL8bVMXQUlRRnpPFJiH4bz+9eiGeaRHxk1eKVwVTqTPP2LswcnaQR VtG279FVHisFYVbU4Gt1BIJCrUB6aQmhMkBZ0jAE1ZLc4JcXlbPn4NNIwKk/HrDS5cI9 lfiv9Jrkq1r+Qlz5lnQYFQ5QERn8/rsUFOPw54Xo/HNNzg6OxTsXVE39pfRac0yBjx5+ uc5GbsYMfas5X+pgPjUlm8c7zEVpHpRM/6/9cxoZ521F0qEipFo8WBIMJIhdhqYkMJuo vdCTaSPv47GrBT1nyrqxpZ1//kKtEG/Ywd2lM9Tg8yFG63ZxqtGb0CjQQmz+y8TSFiSY wEtw== X-Gm-Message-State: AJcUukc9NLI3/b3qpezxATNGpw37rg+rj06VwUJh+Sw9Z15vrlqb9lQP MSxQxlL27F0huc5nGXy+QplO6JTegGw= X-Google-Smtp-Source: ALg8bN72Or+VdbFJ/cvQY14fqIwrywiHHTkj1Hyyb7DJPCqWH2rtSsJQJW/Rqks/I4+ZEJ7JsrshcA== X-Received: by 2002:a63:7c6:: with SMTP id 189mr3210108pgh.129.1546986758624; Tue, 08 Jan 2019 14:32:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:22 +1000 Message-Id: <20190108223129.5570-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 24/31] target/arm: Implement pauth_strip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 902f68a24c..e02376a2d0 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -38,6 +38,15 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t = ptr, uint64_t modifier, g_assert_not_reached(); /* FIXME */ } =20 +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t extfield =3D -param.select; + int bot_pac_bit =3D 64 - param.tsz; + int top_pac_bit =3D 64 - 8 * param.tbi; + + return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield= ); +} + static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifi= er, ARMPACKey *key, bool data, int keynumber) { @@ -46,7 +55,10 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t pt= r, uint64_t modifier, =20 static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_original_ptr(ptr, param); } =20 static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987451101437.9897260858895; Tue, 8 Jan 2019 14:44:11 -0800 (PST) Received: from localhost ([127.0.0.1]:42731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh06U-0002qH-3r for importer@patchew.org; Tue, 08 Jan 2019 17:44:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvP-0000ZR-KX for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvO-0005CT-Re for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:43 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33306) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvO-0005BH-Jf for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:42 -0500 Received: by mail-pg1-x544.google.com with SMTP id z11so2376357pgu.0 for ; Tue, 08 Jan 2019 14:32:42 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=01IO6/Fjvs90ItdmEEqL8n0fmAXQds5N0LRFVoEcyAc=; b=H2LfJaneF5DOwovLhZn4aPomZxKe+nds1fXmoL0ADWQbBLRPYtdL5NrxE/Rv7CCj2v IczOKLU/thgB1aj0L4PNvIqQrrnKu0i8720ESIrS/W6/4idfpt/7vNXE1W/PL+JlB8kt 1PUTifBFrjs33fFQb3mEYWwLpNRIdoR9TWLxU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=01IO6/Fjvs90ItdmEEqL8n0fmAXQds5N0LRFVoEcyAc=; b=Te1KFjx1txZ0mZLs/JpF6OTbU2Z41z+z2DlePMKK2ngVZ84V+NhADN9sSGaV/xkjBI Ii5FEKwEPXJ+03lSMSCXrvZQGY1oTp016WipT/ClJ8+lFGAEX62HAeNPQNWuySF5eStX iC+jgbZbnBHSYposjtMSDpEd5FIJPRW6/oEz+nC9mjncgcG2Fxqtxh7YmjROEGk66nnh qEh1aXK3q/G6dT4OTR114/v4vSe9MLQvXmYTbpJwUu2KvBS9+YE7HK911H9n9Tbf0KLg UM0MRJhVcDSyVaiMnrrnEKUBxxG16KlzcwSqrSEYOf9BJQkG1td/dkGuWrwan/cOkVGi T86w== X-Gm-Message-State: AJcUukfkHom/abEIlMUteCIagYtrPx9jLcllzVwIcLacggFEF5Ibv1YT pC9D7sc6uUy8YQa7apY4px7z6ZvlpUg= X-Google-Smtp-Source: ALg8bN7+MZfqABGjw9auYE+6pWcYlGb2ST1RdgvElTASv102Wtfa5bcXtcNoBTWs99xz/SImeX9Aqg== X-Received: by 2002:a63:580a:: with SMTP id m10mr3111075pgb.332.1546986761167; Tue, 08 Jan 2019 14:32:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:23 +1000 Message-Id: <20190108223129.5570-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 25/31] target/arm: Implement pauth_auth X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index e02376a2d0..fa7707e0bf 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -50,7 +50,26 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAPa= rameters param) static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifi= er, ARMPACKey *key, bool data, int keynumber) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx, data); + int bot_bit, top_bit; + uint64_t pac, orig_ptr, test; + + orig_ptr =3D pauth_original_ptr(ptr, param); + pac =3D pauth_computepac(orig_ptr, modifier, *key); + bot_bit =3D 64 - param.tsz; + top_bit =3D 64 - 8 * param.tbi; + + test =3D (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); + if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { + int error_code =3D (keynumber << 1) | (keynumber ^ 1); + if (param.tbi) { + return deposit64(ptr, 53, 2, error_code); + } else { + return deposit64(ptr, 61, 2, error_code); + } + } + return orig_ptr; } =20 static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987652819691.784499389012; Tue, 8 Jan 2019 14:47:32 -0800 (PST) Received: from localhost ([127.0.0.1]:43564 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh09j-000649-NH for importer@patchew.org; Tue, 08 Jan 2019 17:47:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvX-0000gq-IY for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvU-0005IM-30 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:49 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:44978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvS-0005Ee-MJ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:46 -0500 Received: by mail-pl1-x62b.google.com with SMTP id e11so2559099plt.11 for ; Tue, 08 Jan 2019 14:32:45 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m+Zcu5dZ/zmIPm21/MzZiFGJp7J+d+OfEJPTnePaGgs=; b=F+F+/Iry66hFS6DrVr0R1IQXHTWtE3wetOnVMr+DytvwsAK/RtXaBh+CzsgJZG1uG6 n+M97TaXIhQ3jyx1vS40/i2S0/6/8y7u4EaRVYa376PETDIZnaW1O9DzN5fBuh16FMVB H8uYn3KTknfIjY9J8gLR8ywer/FN3iH35droo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m+Zcu5dZ/zmIPm21/MzZiFGJp7J+d+OfEJPTnePaGgs=; b=lUNOE/pylAJZ42tTX3AXs6qQF7ulO1TnnH6d+DusDuitDmli5NBxQNYjgPnBt30ZsA ngs1AfrkyXtuji17rcTOut9fNd/o8esKtwl4Bl9DeykW6YsHRT+SCAOmJRL5P7zuNF2z 30gjEW9NMGS2zS5KsJfQODIZOHpy7dUkjMJnfZqP6MN7Haul3ZXZPscx8+YgyEW29dd1 MMsE6r23ECeuZ0UDZaZFznEFG4w1NGw3y2JOYS8UZNsAxOHKj7sh+j7jkwRSi7++YbNA Fm1l+65sXgB0FDavrjw1E3P03928uuzFiB4/49nHNvj281jFiRA1pJsp9iRuFWgSwd4Z RyNQ== X-Gm-Message-State: AJcUukfMclEQMOxWVw3BoQ3JWl2CMAAIDAO2VlfrvxiygtRMqSQ+tS92 xWaH1gJuRnnCvbCvYadWNomoFR167SQ= X-Google-Smtp-Source: ALg8bN7K4MMT/r13UoQameAuNQAOm1mRhqi8yt+SOv/+dC6CmtvbB+RQOq5WAxcXY3xoBpoPB8OFtw== X-Received: by 2002:a17:902:f24:: with SMTP id 33mr3614190ply.65.1546986763736; Tue, 08 Jan 2019 14:32:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:24 +1000 Message-Id: <20190108223129.5570-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH v3 26/31] target/arm: Implement pauth_addpac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Use MAKE_64BIT_MASK one more place. --- target/arm/pauth_helper.c | 42 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index fa7707e0bf..bc89dd8c11 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -35,7 +35,47 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t= modifier, static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modi= fier, ARMPACKey *key, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx, data); + uint64_t pac, ext_ptr, ext, test; + int bot_bit, top_bit; + + /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ + if (param.tbi) { + ext =3D sextract64(ptr, 55, 1); + } else { + ext =3D sextract64(ptr, 63, 1); + } + + /* Build a pointer with known good extension bits. */ + top_bit =3D 64 - 8 * param.tbi; + bot_bit =3D 64 - param.tsz; + ext_ptr =3D deposit64(ptr, bot_bit, top_bit - bot_bit, ext); + + pac =3D pauth_computepac(ext_ptr, modifier, *key); + + /* + * Check if the ptr has good extension bits and corrupt the + * pointer authentication code if not. + */ + test =3D sextract64(ptr, bot_bit, top_bit - bot_bit); + if (test !=3D 0 && test !=3D -1) { + pac ^=3D MAKE_64BIT_MASK(top_bit - 1, 1); + } + + /* + * Preserve the determination between upper and lower at bit 55, + * and insert pointer authentication code. + */ + if (param.tbi) { + ptr &=3D ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); + pac &=3D MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); + } else { + ptr &=3D MAKE_64BIT_MASK(0, bot_bit); + pac &=3D ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit)); + } + ext &=3D MAKE_64BIT_MASK(55, 1); + return pac | ext | ptr; } =20 static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154698814305085.80688056487611; Tue, 8 Jan 2019 14:55:43 -0800 (PST) Received: from localhost ([127.0.0.1]:45703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0Hd-0005wi-UG for importer@patchew.org; Tue, 08 Jan 2019 17:55:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53083) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvZ-0000jN-JN for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzvX-0005L6-Lf for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:53 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:46783) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzvV-0005Hy-39 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:49 -0500 Received: by mail-pg1-x544.google.com with SMTP id w7so2341383pgp.13 for ; Tue, 08 Jan 2019 14:32:47 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TVFC2GnajrDi6vJcNao7tzlaxbm1uciSrDAJDzmWUhc=; b=A5JIwu+pyzJ3BqLvQ6ru+ifXw28m5YgYAZTpsByI2hsP5NS8WmrKMyUvZEakVJJUYi FdMJ8s3MMXzFpNiw7q2y8iHeK/MKZZ+jWqPA8Ruov+MmVEAbXUvmGgmv90E2rM6/kxVy xe2OT6XRcK6lYHkF7Fl2qRx61Rksuh77HFM1w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TVFC2GnajrDi6vJcNao7tzlaxbm1uciSrDAJDzmWUhc=; b=mpYC5HE5LcDD7u2AFCo4EBy0RietOgEgEO0upVtZ41Tdc5bNi/Q5Vgf3a1a0rVU6Yg JDgkekZtFqMNGL1uw3sQOtAPh4ju+J9IX/HDuMMM6+UC78Y/PCENDWyXX7xOvxPjeDnI Zsfe/9ElRsmZKwlrPid2xsQ7D4T7ONByOMgWWkJvfEmJ5b/yGl85+nQc421DztCiHCH5 ooqm+SFxD9jf2Vrj5JKrDG7yCm8fQDX+slHUJJA3ODVs+sVHHDRP+q6TKYAz6zgNQOUk SMi/90EYwCG/dQGGXJ4ZdSpTkvYdOqzIhbtkhdAB+R5Qq8E0io8PDi6ePz+v6M4LKtZt wPfQ== X-Gm-Message-State: AJcUukfFc4PvW9flttOgkMWUhplzVhuKNIKGO/qD329AGxzguubAXySi oJ1NFPDOhBBbzZAK1fFhNEQdPIgNeL4= X-Google-Smtp-Source: ALg8bN6y8lu+BiTJap6P3arTuLJ0kuGV/FJXLLO59Spy0inwe6h27xRM+8eI5cyx/yDub/vS6xovQg== X-Received: by 2002:a63:e655:: with SMTP id p21mr3139069pgj.70.1546986766407; Tue, 08 Jan 2019 14:32:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:25 +1000 Message-Id: <20190108223129.5570-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 27/31] target/arm: Implement pauth_computepac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 241 +++++++++++++++++++++++++++++++++++++- 1 file changed, 240 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index bc89dd8c11..bc0c9b84e7 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -26,10 +26,249 @@ #include "tcg/tcg-gvec-desc.h" =20 =20 +static uint64_t pac_cell_shuffle(uint64_t i) +{ + uint64_t o =3D 0; + + o |=3D extract64(i, 52, 4); + o |=3D extract64(i, 24, 4) << 4; + o |=3D extract64(i, 44, 4) << 8; + o |=3D extract64(i, 0, 4) << 12; + + o |=3D extract64(i, 28, 4) << 16; + o |=3D extract64(i, 48, 4) << 20; + o |=3D extract64(i, 4, 4) << 24; + o |=3D extract64(i, 40, 4) << 28; + + o |=3D extract64(i, 32, 4) << 32; + o |=3D extract64(i, 12, 4) << 36; + o |=3D extract64(i, 56, 4) << 40; + o |=3D extract64(i, 20, 4) << 44; + + o |=3D extract64(i, 8, 4) << 48; + o |=3D extract64(i, 36, 4) << 52; + o |=3D extract64(i, 16, 4) << 56; + o |=3D extract64(i, 60, 4) << 60; + + return o; +} + +static uint64_t pac_cell_inv_shuffle(uint64_t i) +{ + uint64_t o =3D 0; + + o |=3D extract64(i, 12, 4); + o |=3D extract64(i, 24, 4) << 4; + o |=3D extract64(i, 48, 4) << 8; + o |=3D extract64(i, 36, 4) << 12; + + o |=3D extract64(i, 56, 4) << 16; + o |=3D extract64(i, 44, 4) << 20; + o |=3D extract64(i, 4, 4) << 24; + o |=3D extract64(i, 16, 4) << 28; + + o |=3D i & MAKE_64BIT_MASK(32, 4); + o |=3D extract64(i, 52, 4) << 36; + o |=3D extract64(i, 28, 4) << 40; + o |=3D extract64(i, 8, 4) << 44; + + o |=3D extract64(i, 20, 4) << 48; + o |=3D extract64(i, 0, 4) << 52; + o |=3D extract64(i, 40, 4) << 56; + o |=3D i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_sub(uint64_t i) +{ + static const uint8_t sub[16] =3D { + 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe, + 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa, + }; + uint64_t o =3D 0; + int b; + + for (b =3D 0; b < 64; b +=3D 16) { + o |=3D (uint64_t)sub[(i >> b) & 0xf] << b; + } + return o; +} + +static uint64_t pac_inv_sub(uint64_t i) +{ + static const uint8_t inv_sub[16] =3D { + 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9, + 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3, + }; + uint64_t o =3D 0; + int b; + + for (b =3D 0; b < 64; b +=3D 16) { + o |=3D (uint64_t)inv_sub[(i >> b) & 0xf] << b; + } + return o; +} + +static int rot_cell(int cell, int n) +{ + /* 4-bit rotate left by n. */ + cell |=3D cell << 4; + return extract32(cell, 4 - n, 4); +} + +static uint64_t pac_mult(uint64_t i) +{ + uint64_t o =3D 0; + int b; + + for (b =3D 0; b < 4 * 4; b +=3D 4) { + int i0, i4, i8, ic, t0, t1, t2, t3; + + i0 =3D extract64(i, b, 4); + i4 =3D extract64(i, b + 4 * 4, 4); + i8 =3D extract64(i, b + 8 * 4, 4); + ic =3D extract64(i, b + 12 * 4, 4); + + t0 =3D rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1); + t1 =3D rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2); + t2 =3D rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1); + t3 =3D rot_cell(ic, 1) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1); + + o |=3D (uint64_t)t3 << b; + o |=3D (uint64_t)t2 << (b + 4 * 4); + o |=3D (uint64_t)t1 << (b + 8 * 4); + o |=3D (uint64_t)t0 << (b + 12 * 4); + } + return o; +} + +static uint64_t tweak_cell_rot(uint64_t cell) +{ + return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3); +} + +static uint64_t tweak_shuffle(uint64_t i) +{ + uint64_t o =3D 0; + + o |=3D extract64(i, 16, 4) << 0; + o |=3D extract64(i, 20, 4) << 4; + o |=3D tweak_cell_rot(extract64(i, 24, 4)) << 8; + o |=3D extract64(i, 28, 4) << 12; + + o |=3D tweak_cell_rot(extract64(i, 44, 4)) << 16; + o |=3D extract64(i, 8, 4) << 20; + o |=3D extract64(i, 12, 4) << 24; + o |=3D tweak_cell_rot(extract64(i, 32, 4)) << 28; + + o |=3D extract64(i, 48, 4) << 32; + o |=3D extract64(i, 52, 4) << 36; + o |=3D extract64(i, 56, 4) << 40; + o |=3D tweak_cell_rot(extract64(i, 60, 4)) << 44; + + o |=3D tweak_cell_rot(extract64(i, 0, 4)) << 48; + o |=3D extract64(i, 4, 4) << 52; + o |=3D tweak_cell_rot(extract64(i, 40, 4)) << 56; + o |=3D tweak_cell_rot(extract64(i, 36, 4)) << 60; + + return o; +} + +static uint64_t tweak_cell_inv_rot(uint64_t cell) +{ + return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3)); +} + +static uint64_t tweak_inv_shuffle(uint64_t i) +{ + uint64_t o =3D 0; + + o |=3D tweak_cell_inv_rot(extract64(i, 48, 4)); + o |=3D extract64(i, 52, 4) << 4; + o |=3D extract64(i, 20, 4) << 8; + o |=3D extract64(i, 24, 4) << 12; + + o |=3D extract64(i, 0, 4) << 16; + o |=3D extract64(i, 4, 4) << 20; + o |=3D tweak_cell_inv_rot(extract64(i, 8, 4)) << 24; + o |=3D extract64(i, 12, 4) << 28; + + o |=3D tweak_cell_inv_rot(extract64(i, 28, 4)) << 32; + o |=3D tweak_cell_inv_rot(extract64(i, 60, 4)) << 36; + o |=3D tweak_cell_inv_rot(extract64(i, 56, 4)) << 40; + o |=3D tweak_cell_inv_rot(extract64(i, 16, 4)) << 44; + + o |=3D extract64(i, 32, 4) << 48; + o |=3D extract64(i, 36, 4) << 52; + o |=3D extract64(i, 40, 4) << 56; + o |=3D tweak_cell_inv_rot(extract64(i, 44, 4)) << 60; + + return o; +} + static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, ARMPACKey key) { - g_assert_not_reached(); /* FIXME */ + static const uint64_t RC[5] =3D { + 0x0000000000000000ull, + 0x13198A2E03707344ull, + 0xA4093822299F31D0ull, + 0x082EFA98EC4E6C89ull, + 0x452821E638D01377ull, + }; + const uint64_t alpha =3D 0xC0AC29B7C97C50DDull; + /* Note that in the ARM pseudocode, key0 contains bits <127:64> + * and key1 contains bits <63:0> of the 128-bit key. + */ + uint64_t key0 =3D key.hi, key1 =3D key.lo; + uint64_t workingval, runningmod, roundkey, modk0; + int i; + + modk0 =3D (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63)); + runningmod =3D modifier; + workingval =3D data ^ key0; + + for (i =3D 0; i <=3D 4; ++i) { + roundkey =3D key1 ^ runningmod; + workingval ^=3D roundkey; + workingval ^=3D RC[i]; + if (i > 0) { + workingval =3D pac_cell_shuffle(workingval); + workingval =3D pac_mult(workingval); + } + workingval =3D pac_sub(workingval); + runningmod =3D tweak_shuffle(runningmod); + } + roundkey =3D modk0 ^ runningmod; + workingval ^=3D roundkey; + workingval =3D pac_cell_shuffle(workingval); + workingval =3D pac_mult(workingval); + workingval =3D pac_sub(workingval); + workingval =3D pac_cell_shuffle(workingval); + workingval =3D pac_mult(workingval); + workingval ^=3D key1; + workingval =3D pac_cell_inv_shuffle(workingval); + workingval =3D pac_inv_sub(workingval); + workingval =3D pac_mult(workingval); + workingval =3D pac_cell_inv_shuffle(workingval); + workingval ^=3D key0; + workingval ^=3D runningmod; + for (i =3D 0; i <=3D 4; ++i) { + workingval =3D pac_inv_sub(workingval); + if (i < 4) { + workingval =3D pac_mult(workingval); + workingval =3D pac_cell_inv_shuffle(workingval); + } + runningmod =3D tweak_inv_shuffle(runningmod); + roundkey =3D key1 ^ runningmod; + workingval ^=3D RC[4-i]; + workingval ^=3D roundkey; + workingval ^=3D alpha; + } + workingval ^=3D modk0; + + return workingval; } =20 static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modi= fier, --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cgtR9AcclT/6PUb+U3TOK7K77PPNIIjwkFK/abHOz38=; b=GhjQtssPFwPTmYISib19M/WsSU9Jx3GNafPOLF2k5UMen3pcLkzI7849tGvou/D2k5 RQ4a+H7EBKSws0q0idkzbRlPIpQgeSMjFxtkLfaD34mYxkSUEDoR1mx/nxA1T4vTpcym gHZXLOfEE/1m6YnnZlY58m7e525R87zfGW0Wk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cgtR9AcclT/6PUb+U3TOK7K77PPNIIjwkFK/abHOz38=; b=TyLxWPgTcfHTpBZVF5wz+IlPo2w0ul7xa8UozQjG6k4GDvq6arFUFzsXg77V6WJCfs 0ymW1GuyS0Jtdf1LA3/dpt/p2KAAICkygTKjFagqUfD66ydLVFGF3NFu4h5tYHNpZm13 npWupsmUuGqBo/hAO7NsxhMCzpQ/YO7ip7R7CraZ0s1C0Xmx51QibtX0mX7YAVJeVt5s BobDTUxrGXl9tRxWj5eBnnSpFBa88sFtL4vPUe4nhqp7TnZfqJHVkVI7qW9KImhzFZyg sFhW13sWouB2qpvslBW3zKEmERNzNDna1S20VNa+xCLvtNLyEhvJDcYDsdxtRHGbqwjT XObw== X-Gm-Message-State: AJcUukcxFxPko/XdpAlas6IdKYA6Po8MW0KdLriFncnacPfj5wIwxL6O OaemXunq3scVTvrDHORB0GgGg9epcEo= X-Google-Smtp-Source: ALg8bN5xCKRJ9VwHIHU1QTGw7jwBes+eWS6r+M7KrIucrt/v6+0JTcG9Xqn7Ug3a9vme13V7XnTyyA== X-Received: by 2002:a65:65c9:: with SMTP id y9mr3229495pgv.438.1546986769084; Tue, 08 Jan 2019 14:32:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:26 +1000 Message-Id: <20190108223129.5570-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 28/31] target/arm: Add PAuth system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Fix typos. --- target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index e610155166..0e1bf521ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5061,6 +5061,70 @@ static CPAccessResult access_lor_other(CPUARMState *= env, return access_lor_ns(env); } =20 +#ifdef TARGET_AARCH64 +static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_APK)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_APK)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo pauth_reginfo[] =3D { + { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apda_key.lo) }, + { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apda_key.hi) }, + { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apdb_key.lo) }, + { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apdb_key.hi) }, + { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apga_key.lo) }, + { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apga_key.hi) }, + { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apia_key.lo) }, + { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apia_key.hi) }, + { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apib_key.lo) }, + { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, apib_key.hi) }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5845,6 +5909,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); } } + +#ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_pauth, cpu)) { + define_arm_cp_regs(cpu, pauth_reginfo); + } +#endif } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546987981576495.91123505459905; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9pMhAJaZppv83OJ/WEZU7HzfgmZ4OshNKmGIx2Wtdqk=; b=Wp0B3d5roDAwda1CJ9ivoJuYp1/l9X3aXe0k5aBB+SkmvoDn9ycgZJWvjfHzPuywj2 WKmnsIOc9y7EqKMkIW56gwfZKVlnwAYEzhglhN5LcTZPxUBdwwJwE7Xa8UmmapmkqwLD hYKgcnHy6JDuy/qp9UZfJir3/Ly3Cc2DHERsU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9pMhAJaZppv83OJ/WEZU7HzfgmZ4OshNKmGIx2Wtdqk=; b=Uu205Sm85+2j3/V0G+O1vuhED4LGaydTvN12e4KcUwhzvvr43P3/E9GE1WQ6y2YYb7 7hemR1WJVTj6K24bqGm3MdqA/yNEedynxx0qJ/W/NnRA8NZws6uu32DgfG3Oa6Dz0Dzz 4kUkn+xLs74Kb9t+r7Rp5VN/VBapGeTU0PVbsCo0O7RIORDaB3aqZyKWKFTc43O3lEHk dFWU1ZdF8Wg02+hsS9Gq0vT54pXw8Ycp8p7BF5tRK620+vj5GjcvZ98dJh0F1wJAjxlK +B0+PQKgk/uHjG9f9igNbTnM1OzQMHCIXto0zuID8WWHrdULUA42VQGW5eSyD34aRoWk LU5g== X-Gm-Message-State: AJcUukcS/s9twbZEbe/8WfTtXW/h0RGYU4X5Z1k7P+fKUSP023lXkzco X9EgtHDVlxAcQ1e94sd+uXpYI3oC1Mg= X-Google-Smtp-Source: ALg8bN792hM1NuD/0CsDPX2bRxFh5OgtXbq+OSS6aH6QgHXEBQgkSnfR/WW/+ZlielUCfUjTM4Sk9A== X-Received: by 2002:a63:d34a:: with SMTP id u10mr3184618pgi.301.1546986771674; Tue, 08 Jan 2019 14:32:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:27 +1000 Message-Id: <20190108223129.5570-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 29/31] target/arm: Enable PAuth for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4b544a1c58..1974f1aeb7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -316,6 +316,10 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected o= nly */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546988333316369.52639800995166; Tue, 8 Jan 2019 14:58:53 -0800 (PST) Received: from localhost ([127.0.0.1]:46625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0Ki-00015b-6b for importer@patchew.org; Tue, 08 Jan 2019 17:58:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvf-0000rS-JJ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:33:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggzve-0005UP-I0 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:59 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:44814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggzve-0005Og-BJ for qemu-devel@nongnu.org; Tue, 08 Jan 2019 17:32:58 -0500 Received: by mail-pg1-x543.google.com with SMTP id t13so2346827pgr.11 for ; Tue, 08 Jan 2019 14:32:55 -0800 (PST) Received: from cloudburst.lan (2001-44b8-2176-c800-8cc6-2630-7d99-5ef1.static.ipv6.internode.on.net. [2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SsMK15voUNz/4OMQjnv/6CxVykvnZyFEz9xWDCHBxbE=; b=RFtKkgTFjr71uo+I4TXeaiIYlJwXNkaJwrXFyoVxmgjqY8ENZRQWkLv47bB08jBgPp uSES5q5NH+nFc9xe8VsTJR30eXdriThyVY8awbUMKaEbhvKi3DYrsINCdsTqHWicMHQO NQ5TeT+CofqKSLBNMqnIQW7Txdi7r9LSqgojU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SsMK15voUNz/4OMQjnv/6CxVykvnZyFEz9xWDCHBxbE=; b=OeniCEeSWc8iZeLojj4zrQT4BsfZON0z9PVc3sSZTuQU5wns4en77nCqtVNNYnnVx6 41P4TL/FusAQaVZ9HbgrBd26taDn3G3ZS7AyPsWJtBPWbUIyhigFmBg0LWVY7FCmiCDO BK7g1WOBVJL3ks/BBeg1rzevZTO7bE2lm0WmQ5D00XKXGGBsQQEAe63BTJoN6uJWm6Hj 1FrkiwfoTEtQQZhFs6AUPIix8I31g6T0vb4lwL9bjbD4l7E/yrxjSL1czojUhWZL8gxV FV1OMkH5SbtuCgG3SD0cjEIhsuIVbox3yjdY5cH1gRcLnRh1sKM5OA50umaawqfDVzFz MIWA== X-Gm-Message-State: AJcUukd6VkOsOVuJ+XdY83V//ZHuAxc0ZvOEL5KhbvAhZXFvagUXyplE CXwe5SBIwkumyQ1jwRVL2AcS/Dnj93o= X-Google-Smtp-Source: ALg8bN5Sug1ZjRLNG7l9S4zIRbWgotaQ4yrh+BNZf12lsBf0N8bA5ovT5zfLvg+nk1mIOTiS41tY3A== X-Received: by 2002:a63:2d46:: with SMTP id t67mr3217956pgt.140.1546986774304; Tue, 08 Jan 2019 14:32:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:28 +1000 Message-Id: <20190108223129.5570-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4c4e9e169e..14bc24a35a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -162,6 +162,9 @@ static void arm_cpu_reset(CPUState *s) env->pstate =3D PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |=3D SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |=3D HCR_API; + env->cp15.scr_el3 |=3D SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1974f1aeb7..d0de0d5dcf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -285,6 +285,38 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v= , const char *name, error_propagate(errp, err); } =20 +#ifdef CONFIG_USER_ONLY +static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + const uint64_t *bit =3D opaque; + bool enabled =3D (cpu->env.cp15.sctlr_el[1] & *bit) !=3D 0; + + visit_type_bool(v, name, &enabled, errp); +} + +static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + Error *err =3D NULL; + const uint64_t *bit =3D opaque; + bool enabled; + + visit_type_bool(v, name, &enabled, errp); + + if (!err) { + if (enabled) { + cpu->env.cp15.sctlr_el[1] |=3D *bit; + } else { + cpu->env.cp15.sctlr_el[1] &=3D ~*bit; + } + } + error_propagate(errp, err); +} +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -360,6 +392,34 @@ static void aarch64_max_initfn(Object *obj) */ cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ + + /* + * Note that Linux will enable enable all of the keys at once. + * But doing it this way will allow experimentation beyond that. + */ + { + static const uint64_t apia_bit =3D SCTLR_EnIA; + static const uint64_t apib_bit =3D SCTLR_EnIB; + static const uint64_t apda_bit =3D SCTLR_EnDA; + static const uint64_t apdb_bit =3D SCTLR_EnDB; + + object_property_add(obj, "apia", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apia_bit, &error_fatal); + object_property_add(obj, "apib", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apib_bit, &error_fatal); + object_property_add(obj, "apda", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apda_bit, &error_fatal); + object_property_add(obj, "apdb", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apdb_bit, &error_fatal); + + /* Enable all PAC keys by default. */ + cpu->env.cp15.sctlr_el[1] |=3D SCTLR_EnIA | SCTLR_EnIB; + cpu->env.cp15.sctlr_el[1] |=3D SCTLR_EnDA | SCTLR_EnDB; + } #endif =20 cpu->sve_max_vq =3D ARM_MAX_VQ; --=20 2.17.2 From nobody Sun May 19 00:47:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546988162481784.9686393864479; Tue, 8 Jan 2019 14:56:02 -0800 (PST) Received: from localhost ([127.0.0.1]:45796 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gh0Hx-0006NJ-Ag for importer@patchew.org; Tue, 08 Jan 2019 17:56:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggzvf-0000rT-JV for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 31/31] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can perform this with fewer operations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Update for tbii =3D tbi1:tbi0. --- target/arm/translate-a64.c | 62 +++++++++++++------------------------- 1 file changed, 21 insertions(+), 41 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee92533469..c398da9214 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 @@ -280,54 +280,34 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) int tbi =3D s->tbii; =20 if (s->current_el <=3D 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (tbi =3D=3D 3) { - TCGv_i64 tmp_reg =3D tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (tbi =3D=3D 0) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval =3D tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + if (tbi !=3D 0) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); =20 - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi !=3D 3) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); =20 - if (tbi =3D=3D 1) { - /* tbi0=3D=3D1, tbi1=3D=3D0, so 0-fill upper byte if bit 5= 5 =3D 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); - } else { - /* tbi0=3D=3D0, tbi1=3D=3D1, so 1-fill upper byte if bit 5= 5 =3D 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_= LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ + } else { if (tbi !=3D 0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } =20 typedef struct DisasCompare64 { --=20 2.17.2