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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b7sm47917422wrs.47.2019.01.08.10.00.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 10:00:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rv4ZubjSiBZw4VBG0d+ylKob+8B/qKd0tficu4kTNoo=; b=JZZ7h0vq/FTENOESLiAwPiAINKSkB7P+h5WJxVNI1FXmteWLaRtdANtQXVWFrkOAhu N6X6zme+qadGnDx+N5ma2GhdMgGiLA9SMANOUDOjg/7amA26VL+CPb4umw2cVoKRnsOr IN47VF48fTYdz+cu9NLq1erzUs667Jr0XYiNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rv4ZubjSiBZw4VBG0d+ylKob+8B/qKd0tficu4kTNoo=; b=RPj7wQgwIOz9YNei7H5cA+5sWXRb4hS4EwgFdbu2gqJe1EJKqXfuzPdmiNy+ELglq4 op8hytQWqaK7pFCtKb0nZjQjCWyqmeh8WrpbY24vfDojChK3xi38V6bFtXYZd9GuzU2/ mpAOTok9yN1eTC7XdnZJRLVDXQ98pcVU5t5KmZ6aIlkvb81sL9WyUYL7YeEjl4Bo/ETH LkUuUWuhHKCPrUohoJPZ17CJdjELyy/xqf9wTBVf+ATitF31shH3G72jsKAKFK9vyFFW F24lcKKW+h8IvoCKhHUWx8KzIvcj6oThsR/xpf9DeIQjmBWeNzuRJPkAaKrfSUoNTUIx XbNg== X-Gm-Message-State: AJcUukcWJstTBpJkNKY9Ok9JhlkItW+6c3UQ6OAwA/MintiMXZGgMZ5V FDEIMPffNC2nz2WGC+LKCcwZQg== X-Google-Smtp-Source: ALg8bN7BMuxbpJC3fLNVgYEv0WYBmP+CloYU7sT5Fovqfv18XADZ0tYYL4RgwFOrFyFPjJOd8VRjfw== X-Received: by 2002:adf:e08c:: with SMTP id c12mr2089622wri.199.1546970416902; Tue, 08 Jan 2019 10:00:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 18:00:14 +0000 Message-Id: <20190108180014.32386-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In cpu_signal_handler() for aarch64 hosts, currently we parse the faulting instruction to see if it is a load or a store. Since the 3.16 kernel (~2014), the kernel has provided us with the syndrome register for a fault, which includes the WnR bit. Use this instead if it is present, only falling back to instruction parsing if not. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Since I originally asked the kernel folks to add the ESR context so we could use it in QEMU, I figured that it was about time (five years later...) to write the code to make use of it. I wanted to say "everybody surely has at least a 3.16 kernel for aarch64 machines" and delete the fallback code, but it turns out that the gcc compile farm box has 3.13.0... --- accel/tcg/user-exec.c | 66 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 14 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 941295ea49b..66cc818e3f3 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -479,28 +479,66 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 #elif defined(__aarch64__) =20 +#ifndef ESR_MAGIC +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info =3D pinfo; ucontext_t *uc =3D puc; uintptr_t pc =3D uc->uc_mcontext.pc; - uint32_t insn =3D *(uint32_t *)pc; bool is_write; + struct _aarch64_ctx *hdr; + struct esr_context const *esrctx =3D NULL; =20 - /* XXX: need kernel patch to get write flag faster. */ - is_write =3D ( (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ - /* Ingore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,14-16= */ + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + esrctx =3D (struct esr_context const *)hdr; + break; + } + } =20 + if (esrctx) { + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + uint64_t esr =3D esrctx->esr; + is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; + } else { + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + uint32_t insn =3D *(uint32_t *)pc; + + is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ + } return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 --=20 2.20.1