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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8TvLhHeHZ8C43Ib56UzJG7XSdaUbxT7qr+rCEbqz1Ng=; b=OD1j2netgEyGE6MXVCLp5wTzMppg3ETryCQe6xQ8ubpj8ybsL8WJMjh9ABEEzUeW60 F3DWwWLRHzcwrR9YDAYk9RFlqocA+R/js2DZ4pVue5Yzm53WPHsL+2EkYEGZy0podt1o aga6nAqdRm8AgcPLXAEbpwGoxCSKvm/DcoiMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8TvLhHeHZ8C43Ib56UzJG7XSdaUbxT7qr+rCEbqz1Ng=; b=k38HVaLoMWeDOMjK/QxFPMUy7MWDp+FTYfxkRxuvL10S4yWTM5ywD19wZcNlgXh6Q1 9BUnL95fFYpoH1VHfSAprABXxOHK7ERPpYHg8PWxm5I4kiyuUZvCBGEn5ugJic9kjnHp YDB9yA5RpjbGceV56AVBOgEt1XnEgGHPLSQvBx1cGoqsrw4RKssGMGrPs5pmoo/cJc5V 8iLpyN9SF2meSLbDLz6MmWOkHgkK+XBu5u7YobqEXDrpcQvTEAGvbgt4t1O/WFKQd30e oKSMoMUVZy1OI5pxcVfv31WhM2o/SImAb8GZNCu/dPEyfNt5pS+CptL2hjjO4bTR4HsJ k4bA== X-Gm-Message-State: AJcUukeQErp8NG5iqyFUEg4LGt2Tqf+LyuyyLBMN60da1s/0SJ8BkigN lZtwdEZFH5EBwgxgSHGUAW0BEQ== X-Google-Smtp-Source: ALg8bN5xoqxOYLsxVi9NPFmNiYUfuRBU4ebmZEZNPZlY4OvPOMCVOr9r9FW8Pk5wOvduZ0DOuY6I6A== X-Received: by 2002:a05:6000:100f:: with SMTP id a15mr2074153wrx.298.1546965012378; Tue, 08 Jan 2019 08:30:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 16:30:05 +0000 Message-Id: <20190108163008.7006-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 1/4] hw/arm/xlx-zynqmp: Realize cluster after putting RPUs in it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , patches@linaro.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the cluster implementation doesn't have any constraints on the ordering of realizing the TYPE_CPU_CLUSTER and populating it with child objects. We want to impose a constraint that realize must happen only after all the child objects are added, so move the realize of rpu_cluster. (The apu_cluster is already realized after child population.) Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Reviewed-by: Richard Henderson --- hw/arm/xlnx-zynqmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c67ac2e64ac..370b0e44a38 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -183,8 +183,6 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, = const char *boot_cpu, &error_abort, NULL); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); =20 - qdev_init_nofail(DEVICE(&s->rpu_cluster)); - for (i =3D 0; i < num_rpus; i++) { char *name; =20 @@ -212,6 +210,8 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, = const char *boot_cpu, return; } } + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); } =20 static void xlnx_zynqmp_init(Object *obj) --=20 2.19.2 From nobody Fri Nov 7 05:40:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546965330288173.09137236915456; Tue, 8 Jan 2019 08:35:30 -0800 (PST) Received: from localhost ([127.0.0.1]:55149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguLd-0006M0-S3 for importer@patchew.org; Tue, 08 Jan 2019 11:35:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguGk-0002m1-S5 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gguGf-0003oy-Dp for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:20 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:50949) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gguGf-0003hS-39 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:17 -0500 Received: by mail-wm1-x344.google.com with SMTP id n190so4755048wmd.0 for ; Tue, 08 Jan 2019 08:30:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=GC4QfhBeddbU6aUBlbRYZ6v4jU+85Qu2Z5QAfue52hBcgixrikT7jYJEkJ5+VZZQvW QvvA/jW7wOjhKOfoGFVWD766/SlAYy0SsplNHAvRp5nfv2SBQ78DQrfGyjiaQzgPnV/j MwwW0MfxWHQqlqqCUIpcNgxUquHfZt4HUD4Tg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=CCdUhfTsRRGpDRQunDT0qdBEhIp3cb+WUVskIodd6f9+8iqX8A/DIebxc8Z0iE2ugI upgTLpcF0HRweb2BqWYhyhMYj8kVs6bUz5H+jAjtTVWQnGPsVXCnZDxXht+W+yBRw9lD vjpq2Gx8xoY2Xp6qjtIldwuoiUTDBbBrUTAQrhYZxLGaRvsJqNY1kOEWtbst/UD265vF G378lxRoW4xyVa7dUR3PXVD5HzyxcQcezU2Soyj5q/lxL9YFd+/QQfCvyDUc5cTvnwOD pFR/c2ZPFLltvQtk+AVBT4KB0LMobvog7+t29Yd0jo1Z+9gRwVrW/7tiVNCUj2XjXHn8 C5EQ== X-Gm-Message-State: AJcUukcy11z9GoZl/trR9KNxun0hNAvshwEUH7DTMD93bwIuXpD7xS4u nvRjhjodD+9DNpGrU93M84HSgA== X-Google-Smtp-Source: ALg8bN5XZ3IBaDzH8QJBkh7u+q3aP3ppBSeTZjilUQdKIjPfLHOfQEul1oKCbO2O4wm/JkLogFQJFA== X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr2405012wme.82.1546965013904; Tue, 08 Jan 2019 08:30:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 16:30:06 +0000 Message-Id: <20190108163008.7006-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 2/4] qom/cpu: Add cluster_index to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , patches@linaro.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/cpu/cluster.h | 19 +++++++++++++++++++ include/qom/cpu.h | 7 +++++++ hw/cpu/cluster.c | 33 +++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 60 insertions(+) diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..d1bef315d10 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,31 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPU= s do * not have the same view of memory (for example the main CPU and a manage= ment * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realiz= ed + * object and no way for the parent to be notified when a new child is add= ed + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ =20 #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) =20 +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and sh= ould diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1396f53e5b5..844becbcedc 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -279,6 +279,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assign= ed + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_C= LUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -404,6 +409,7 @@ struct CPUState { =20 /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1109,5 +1115,6 @@ extern const struct VMStateDescription vmstate_cpu_co= mmon; #endif /* NEED_CPU_H */ =20 #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 =20 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..d672f54a620 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,52 @@ =20 #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" =20 static Property cpu_cluster_properties[] =3D { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; =20 +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster =3D CPU_CLUSTER(dev); + ObjectPropertyIterator iter; + ObjectProperty *prop; + Object *cluster_obj =3D OBJECT(dev); + + if (cluster->cluster_id >=3D MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_property_iter_init(&iter, cluster_obj); + while ((prop =3D object_property_iter_next(&iter))) { + Object *cpu_obj; + CPUState *cpu; + + if (!strstart(prop->type, "child<", NULL)) { + continue; + } + cpu_obj =3D object_property_get_link(cluster_obj, prop->name, NULL= ); + cpu =3D (CPUState *)object_dynamic_cast(cpu_obj, TYPE_CPU); + if (!cpu) { + continue; + } + cpu->cluster_index =3D cluster->cluster_id; + } +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->props =3D cpu_cluster_properties; + dc->realize =3D cpu_cluster_realize; } =20 static const TypeInfo cpu_cluster_type_info =3D { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc =3D CPU_GET_CLASS(obj); =20 cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; + cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */ --=20 2.19.2 From nobody Fri Nov 7 05:40:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546965386505181.8840586660151; Tue, 8 Jan 2019 08:36:26 -0800 (PST) Received: from localhost ([127.0.0.1]:55254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguMZ-00076y-S7 for importer@patchew.org; Tue, 08 Jan 2019 11:36:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguGu-0002wA-2M for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gguGk-0003xu-64 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:26 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34367) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gguGg-0003lF-Fe for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:18 -0500 Received: by mail-wm1-x344.google.com with SMTP id y185so8848726wmd.1 for ; Tue, 08 Jan 2019 08:30:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=46ldnkoBNzwTQapSHqF1F5MiDCIH8/mF+o2srm542zA=; b=WaPUYokY5ErXyR7LdmjSESE3txFpKVAfb+jQ2XV7N7W9M0t5rQM1VHbbGd/DxJFHvy c2KlgQw3cYVn9DyvHT7AywpuGKLR5PYDtJM94fqzpk0NjQkrjJJpr5qmU2htXgy+QrRF bkSrPYTJhcV5FTnceKH76MBklxcmTejTqEW/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=46ldnkoBNzwTQapSHqF1F5MiDCIH8/mF+o2srm542zA=; b=IN4xe1vEVKKwHa9zjzCgaTkI+nv7ib6EK7AMz8mpdIznqk918P7HMUqe33fO3D9bA/ GaXD7HPHuczpWWix4L32loZxTjuBAP/Z1HDLZCOFUvdsKiTvom1ES2+ko1gQ6s1TKqCE Ha8E9RzKnT41LyxJtwBYfQtAdNFX09mGHGD1OQrDKYcfYApKLNZRpNt2vhmqWDumRNaE 6qLkUfaOz7sAchiD/f+MT+5BstOQnRQDdVOdyAYPh5aVabsVfKC0geCEIJfX1hG9pMZp J3SORPWZpGnjKdreBosTy5awkylO8O1NR3oEjO1xmX6jS0VAupqYs2Ek+Si3pDblRlkK eMFA== X-Gm-Message-State: AJcUukfhPQ26yekWuL2Fncnrnrd58akVKmNYzQSGOm5vuNYUukIbc9Sd a3mJOEMR39Gtgt1snpf1uI/FJw== X-Google-Smtp-Source: ALg8bN74tF166Sq83/2IFptmgmnhGHhKb5TkeuvcFr88Irmh4Gm1DF4/Z21hHUYjWUDU4S1tNkBB9A== X-Received: by 2002:a1c:1b8d:: with SMTP id b135mr2312163wmb.115.1546965015380; Tue, 08 Jan 2019 08:30:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 16:30:07 +0000 Message-Id: <20190108163008.7006-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 3/4] accel/tcg: Add cluster number to TCG TB hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , patches@linaro.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Include the cluster number in the hash we use to look up TBs. This is important because a TB that is valid for one cluster at a given physical address and set of CPU flags is not necessarily valid for another: the two clusters may have different views of physical memory, or may have different CPU features (eg FPU present or absent). We put the cluster number in the high 8 bits of the TB cflags. This gives us up to 256 clusters, which should be enough for anybody. If we ever need more, or need more bits in cflags for other purposes, we could make tb_hash_func() take more data (and expand qemu_xxhash7() to qemu_xxhash8()). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 4 +++- accel/tcg/cpu-exec.c | 4 ++++ accel/tcg/translate-all.c | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 815e5b1e838..aa7b81aaf01 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -351,9 +351,11 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held = */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 /* cflags' mask for hashing/comparison */ #define CF_HASH_MASK \ - (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) + (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER= _MASK) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 870027d4359..e578a1a3aee 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -336,6 +336,10 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targ= et_ulong pc, return NULL; } desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; + + cf_mask &=3D ~CF_CLUSTER_MASK; + cf_mask |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; + h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b27287..ba27f5acc8c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1692,6 +1692,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |=3D CF_NOCACHE | 1; } =20 + cflags &=3D ~CF_CLUSTER_MASK; + cflags |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { --=20 2.19.2 From nobody Fri Nov 7 05:40:50 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546965503141732.5077664650481; Tue, 8 Jan 2019 08:38:23 -0800 (PST) Received: from localhost ([127.0.0.1]:55466 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguOK-0008L8-F6 for importer@patchew.org; Tue, 08 Jan 2019 11:38:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gguGw-0002yW-B2 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gguGu-0004HJ-2y for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:34 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46002) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gguGl-0003oh-56 for qemu-devel@nongnu.org; Tue, 08 Jan 2019 11:30:26 -0500 Received: by mail-wr1-x443.google.com with SMTP id t6so4641153wrr.12 for ; Tue, 08 Jan 2019 08:30:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lHw25Aq6KmkJUqEwitBkXgdSRY6pkgGYnAbHYsqk6tg=; b=PFC02pyTYUTf7RVgboMHb9D890vfTPFjCqcMDUTi7873obKgsYCxfGUgXSthXTt196 OtFBZ19j3LcARz0wiN6DK23UhPjZLNU60Zc3hpmlGejtigi1pm9xKQDQdHq+qovfwPgw b6kuvmHx39Agf/S49EDAMJ+gIXoTe7kAN/0TY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lHw25Aq6KmkJUqEwitBkXgdSRY6pkgGYnAbHYsqk6tg=; b=WWcGLrkdq57PnzWeVyDRVdeSnuC0Mth1I0xOF/M/rASSSu0fRvhuESvThgphfSEg8b TzM3sbdTwSD+5f61+NMEmJwCUSx89yMuM4PVpFNAIFqNh1mMk++4/7MmTfMu47rwCb+B BfdVnZefsfEKjZPayoL8eJUAIy0wU92QwiXefo9W5vjS2B3AFH5FHxCniZymv60vQUoY z8LssdTMw+wl5GLHfJJSpvbIVFz9usIuv/kRTEtbexDFAq7xriMJAGpEtHph7807qvQC 9aCaaXkoCDpJJooWgi14bWLnvGHIkjCapllW3AZ5NL+HHvhc7te3uZYQrJs0CEH51fgB W8bQ== X-Gm-Message-State: AJcUukfq6UX/1Aueswp9OQr5cH6Ni9lBF5Oh6voSDZ/N/IUKs9STWbql Q97Whc6FKanzwKAKCBQj5tCSsA== X-Google-Smtp-Source: ALg8bN5ZIj1zsnqZt+8hHJKF99Se4N2TvoP0ilqbwTvpKPL6Anjr+Ck6457bk6lJLwIJhm0Q6aotSA== X-Received: by 2002:a5d:47d1:: with SMTP id l17mr1925630wrs.319.1546965016893; Tue, 08 Jan 2019 08:30:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 16:30:08 +0000 Message-Id: <20190108163008.7006-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 4/4] gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , patches@linaro.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we're keeping the cluster index in the CPUState, we don't need to jump through hoops in gdb_get_cpu_pid() to find the associated cluster object. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- gdbstub.c | 48 +++++------------------------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index bfc7afb5096..5d6cbea9d35 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -644,50 +644,12 @@ static int memtox(char *buf, const char *mem, int len) =20 static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) { -#ifndef CONFIG_USER_ONLY - gchar *path, *name =3D NULL; - Object *obj; - CPUClusterState *cluster; - uint32_t ret; - - path =3D object_get_canonical_path(OBJECT(cpu)); - - if (path =3D=3D NULL) { - /* Return the default process' PID */ - ret =3D s->processes[s->process_num - 1].pid; - goto out; - } - - name =3D object_get_canonical_path_component(OBJECT(cpu)); - assert(name !=3D NULL); - - /* - * Retrieve the CPU parent path by removing the last '/' and the CPU n= ame - * from the CPU canonical path. - */ - path[strlen(path) - strlen(name) - 1] =3D '\0'; - - obj =3D object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); - - if (obj =3D=3D NULL) { - /* Return the default process' PID */ - ret =3D s->processes[s->process_num - 1].pid; - goto out; - } - - cluster =3D CPU_CLUSTER(obj); - ret =3D cluster->cluster_id + 1; - -out: - g_free(name); - g_free(path); - - return ret; - -#else /* TODO: In user mode, we should use the task state PID */ - return s->processes[s->process_num - 1].pid; -#endif + if (cpu->cluster_index =3D=3D UNASSIGNED_CLUSTER_INDEX) { + /* Return the default process' PID */ + return s->processes[s->process_num - 1].pid; + } + return cpu->cluster_index + 1; } =20 static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid) --=20 2.19.2