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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id f64sm175814137pfh.0.2019.01.07.18.17.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Jan 2019 18:17:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8yBr0Exh7UTFMeMWhRhfdOVF/dENufT9yCU4z4IZKHI=; b=T4vu0qxlED6K2Bd+7K94JmiWOFEgdzbji5LuvifjQocW0F8r1JJqj5mGpQr5Lkc6p5 1aoeD1hEVUb8rUpLsMMRDFJEWTYyllgsofEdohKo2jYkY/FCUymrEqFyODYls7OaE75B vPgOlZzB87D2mQckB6TwDnz8xNtf+VAe44BD0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8yBr0Exh7UTFMeMWhRhfdOVF/dENufT9yCU4z4IZKHI=; b=DwPfyWdHgDMHQWTDJf9MTfi846zjBiETh9Je3dAwbk22xf7sScfLNugpzHhAWJtAxH kj3T5jwPme4Xn9HupwNVXwuJiWMJXcgg+bfJJtCA4HaBmBhOqAnrG9+/h4u0FPzv5FxO cAS8R7JZUOy+DY3MDUr3mLMM7r/X/jpep0pgFMaTsdBIyvLAbwxmsoc3IXRRZOiVlY7h R35KQLkaycpx2/rh9ZXFtcgVUO+9caaFXQ1eMxuF20vLPeGAMj5OIwdtpP+k9RJrENca FmmVg+8gHfy0djiAWp7q7rKaYz8olPVSx2DIqbjygbU5ZOQ38I+R2c1NgfaP9EuZS1v5 T/DA== X-Gm-Message-State: AJcUukcAauH34enszG2SYHJTthmq8I8O9yZ2zT8eRVCiaLYdIPo7iIsa NV8fcoag3bRNI7672BjMPFNyxNyVxH+MUw== X-Google-Smtp-Source: ALg8bN7+Vsff6U8ZE9ZuI2Y6at2TOHANe40q3RtsYjjc+qwKJV2kGfzZarLtHfFPfCkuZLJiBtnKCA== X-Received: by 2002:a17:902:a98c:: with SMTP id bh12mr63999137plb.31.1546913852589; Mon, 07 Jan 2019 18:17:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 8 Jan 2019 12:17:21 +1000 Message-Id: <20190108021723.14762-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108021723.14762-1-richard.henderson@linaro.org> References: <20190108021723.14762-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PULL 1/3] hw/alpha/typhoon: Stop calling cpu_unassigned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Peter Maydell The typhoon MemoryRegionOps callbacks directly call cpu_unassigned_access(), presumably as the old-fashioned way to provoke a CPU exception. This won't work since commit 6ad4d7eed05a1e235 when we switched Alpha over to the transaction_failed hook API, because now cpu_unassigned_access() is a no-op for Alpha. Make the MemoryRegionOps callbacks use the read_with_attrs and write_with_attrs hooks, so they can signal a failure that should cause a CPU exception by returning MEMTX_ERROR. Signed-off-by: Peter Maydell Message-Id: <20181210173350.13073-1-peter.maydell@linaro.org> Tested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- hw/alpha/typhoon.c | 47 ++++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 8004afe45b..cbacea5fbd 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) } } =20 -static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult cchip_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { CPUState *cpu =3D current_cpu; TyphoonState *s =3D opaque; @@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } =20 - return ret; + *data =3D ret; + return MEMTX_OK; } =20 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) @@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, u= nsigned size) return 0; } =20 -static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t ret =3D 0; @@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } =20 - return ret; + *data =3D ret; + return MEMTX_OK; } =20 -static void cchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult cchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t oldval, newval; @@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } =20 static void dchip_write(void *opaque, hwaddr addr, @@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr, /* Skip this. It's all related to DRAM timing and setup. */ } =20 -static void pchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult pchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t oldval; @@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } =20 static const MemoryRegionOps cchip_ops =3D { - .read =3D cchip_read, - .write =3D cchip_write, + .read_with_attrs =3D cchip_read, + .write_with_attrs =3D cchip_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 8, @@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops =3D { }; =20 static const MemoryRegionOps pchip_ops =3D { - .read =3D pchip_read, - .write =3D pchip_write, + .read_with_attrs =3D pchip_read, + .write_with_attrs =3D pchip_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 8, --=20 2.17.2