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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Hpjch+dvzst++X19IH78pXwdDqlcLO/9Ua30/ssckpw=; b=Zy17NGV+g2pyEacT+3TOdflLo4Q4mUXcKVENTW3RPcDxLajm3WB7U5ukaCaqAybZam MoxnHw/PouVIEl0qBx+DZ3dF86O3lyesyvvhM5tQFFECjNx9Mzo2WlaHJezJGcKyefGz Jg4NDdMztW8oKFEPb1gV7CGiWPsrIWuc2geO0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hpjch+dvzst++X19IH78pXwdDqlcLO/9Ua30/ssckpw=; b=pIBb5AF5NKW+O1GTmtM/m2zzdKnOJ51CALNWcmM0AC8ZZHN7v0flUMWXyEi/6acsrA VsQ8BVUeAHghZ+oX56NRUF+LbcfsQHvlsC/S4NJspRLMqc3TYWec2NkSy+WqO/Rd3kG/ yT/ao9gpjAnA7Wcp/MywNaHHAzuJhQDeZSoMvtmxGNWO2rMUo5ZjzeOQljcoMITYLxHr Adjgd0KxOJiho8NphKYu77rr9acKXxI+An86kCfIwHdoAfc+kopSvRnx4qWQGr1nuznn S7anq/b7JkfInTHYc6FRopJZqyag64Whk0x2FylS1PLr8zUhrOm4lPeadZh69gQcc+0v MbcA== X-Gm-Message-State: AJcUukexS0iJ6Al7HcEYFfs+s7IHgIr+dJfpFgWSR3VzrLZFNu9RAotQ cj9ORK09q1WKRUpaCgsrF+rk2+ky8KpzDQ== X-Google-Smtp-Source: ALg8bN6WxYdCKr903zLbecL+5eqGPWinvBcJ8H/XWPG07HJMG3kt0RyzHrWrwuTlHzbr/V3bm2UmRQ== X-Received: by 2002:adf:dec4:: with SMTP id i4mr50350860wrn.307.1546878682090; Mon, 07 Jan 2019 08:31:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:41 +0000 Message-Id: <20190107163117.16269-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 01/37] target/arm: Convert ARM_TBFLAG_* to FIELDs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Use "register" TBFLAG_ANY to indicate shared state between A32 and A64, and "registers" TBFLAG_A32 & TBFLAG_A64 for fields that are specific to the given cpu state. Move ARM_TBFLAG_BE_DATA to shared state, instead of its current placement within "Bit usage when in AArch32 state". Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20181218164348.7127-1-richard.henderson@linaro.org [PMM: removed the renaming of BE_DATA flag to BE] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 102 ++++++++----------------------------- target/arm/helper.c | 49 +++++++++--------- target/arm/translate-a64.c | 22 ++++---- target/arm/translate.c | 40 ++++++++------- 4 files changed, 78 insertions(+), 135 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c943f35dd92..fba1c578d30 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2944,102 +2944,40 @@ static inline bool arm_cpu_data_is_big_endian(CPUA= RMState *env) * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. */ -#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 -#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHI= FT) -#define ARM_TBFLAG_MMUIDX_SHIFT 28 -#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 -#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS_SHIFT 26 -#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) +FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) +FIELD(TBFLAG_ANY, MMUIDX, 28, 3) +FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ -#define ARM_TBFLAG_FPEXC_EL_SHIFT 24 -#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) +FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) +FIELD(TBFLAG_ANY, BE_DATA, 23, 1) =20 /* Bit usage when in AArch32 state: */ -#define ARM_TBFLAG_THUMB_SHIFT 0 -#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN_SHIFT 1 -#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 -#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN_SHIFT 7 -#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC_SHIFT 8 -#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B_SHIFT 16 -#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) +FIELD(TBFLAG_A32, THUMB, 0, 1) +FIELD(TBFLAG_A32, VECLEN, 1, 3) +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 -#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) /* Indicates whether cp register reads and writes by guest code should acc= ess * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 19 -#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA_SHIFT 20 -#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) +FIELD(TBFLAG_A32, NS, 19, 1) /* For M profile only, Handler (ie not Thread) mode */ -#define ARM_TBFLAG_HANDLER_SHIFT 21 -#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) +FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ -#define ARM_TBFLAG_STACKCHECK_SHIFT 22 -#define ARM_TBFLAG_STACKCHECK_MASK (1 << ARM_TBFLAG_STACKCHECK_SHIFT) +FIELD(TBFLAG_A32, STACKCHECK, 22, 1) =20 /* Bit usage when in AArch64 state */ -#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 = */ -#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ -#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 -#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 -#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) - -/* some convenience accessor macros */ -#define ARM_TBFLAG_AARCH64_STATE(F) \ - (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHI= FT) -#define ARM_TBFLAG_MMUIDX(F) \ - (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE(F) \ - (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS(F) \ - (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) -#define ARM_TBFLAG_FPEXC_EL(F) \ - (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) -#define ARM_TBFLAG_THUMB(F) \ - (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN(F) \ - (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE(F) \ - (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN(F) \ - (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC(F) \ - (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B(F) \ - (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) -#define ARM_TBFLAG_XSCALE_CPAR(F) \ - (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) -#define ARM_TBFLAG_NS(F) \ - (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA(F) \ - (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) -#define ARM_TBFLAG_HANDLER(F) \ - (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) -#define ARM_TBFLAG_STACKCHECK(F) \ - (((F) & ARM_TBFLAG_STACKCHECK_MASK) >> ARM_TBFLAG_STACKCHECK_SHIFT) -#define ARM_TBFLAG_TBI0(F) \ - (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1(F) \ - (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL(F) \ - (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN(F) \ - (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +FIELD(TBFLAG_A64, TBI0, 0, 1) +FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) +FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 644599b29d6..f00c141ef96 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12955,16 +12955,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); int current_el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags =3D 0; =20 if (is_a64(env)) { ARMCPU *cpu =3D arm_env_get_cpu(env); =20 *pc =3D env->pc; - flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); - flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI0, + arm_regime_tbi0(env, mmu_idx)); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI1, + arm_regime_tbi1(env, mmu_idx)); =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); @@ -12978,28 +12980,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, } else { zcr_len =3D sve_zcr_len_for_el(env, current_el); } - flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; - flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; + flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } } else { *pc =3D env->regs[15]; - flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) - | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) - | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); - if (!(access_secure_reg(env))) { - flags |=3D ARM_TBFLAG_NS_MASK; - } + flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags =3D FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); + flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_st= ride); + flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); + flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env= )); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - flags |=3D ARM_TBFLAG_VFPEN_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - flags |=3D (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags =3D FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15= _cpar); } =20 - flags |=3D (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags =3D FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mm= u_idx)); =20 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -13009,24 +13008,24 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - flags |=3D ARM_TBFLAG_SS_ACTIVE_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } else { if (env->uncached_cpsr & PSTATE_SS) { - flags |=3D ARM_TBFLAG_PSTATE_SS_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } } if (arm_cpu_data_is_big_endian(env)) { - flags |=3D ARM_TBFLAG_BE_DATA_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags |=3D fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags =3D FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); =20 if (arm_v7m_is_handler_mode(env)) { - flags |=3D ARM_TBFLAG_HANDLER_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } =20 /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is @@ -13036,7 +13035,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, arm_feature(env, ARM_FEATURE_M) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags |=3D ARM_TBFLAG_STACKCHECK_MASK; + flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } =20 *pflags =3D flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f5..b7b6ab63716 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13380,7 +13380,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); - int bound; + uint32_t tb_flags =3D dc->base.tb->flags; + int bound, core_mmu_idx; =20 dc->isar =3D &arm_cpu->isar; dc->pc =3D dc->base.pc_first; @@ -13394,19 +13395,20 @@ static void aarch64_tr_init_disas_context(DisasCo= ntextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); - dc->tbi0 =3D ARM_TBFLAG_TBI0(dc->base.tb->flags); - dc->tbi1 =3D ARM_TBFLAG_TBI1(dc->base.tb->flags); + core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); + dc->tbi0 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); + dc->tbi1 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->sve_excp_el =3D ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); - dc->sve_len =3D (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); + dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; @@ -13427,8 +13429,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c4675ffd8a..ed3db0c3946 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13021,6 +13021,8 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t tb_flags =3D dc->base.tb->flags; + uint32_t condexec, core_mmu_idx; =20 dc->isar =3D &cpu->isar; dc->pc =3D dc->base.pc_first; @@ -13032,26 +13034,28 @@ static void arm_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); + dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); + dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; + condexec =3D FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + dc->condexec_mask =3D (condexec & 0xf) << 1; + dc->condexec_cond =3D condexec >> 4; + core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); + dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck =3D ARM_TBFLAG_STACKCHECK(dc->base.tb->flags); + dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -13070,8 +13074,8 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 @@ -13516,11 +13520,11 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; =20 - if (ARM_TBFLAG_THUMB(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { ops =3D &aarch64_translator_ops; } #endif --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154687882418426.053946902252846; Mon, 7 Jan 2019 08:33:44 -0800 (PST) Received: from localhost ([127.0.0.1]:42770 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXqQ-00060N-Nw for importer@patchew.org; Mon, 07 Jan 2019 11:33:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoE-0004mG-QG for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoD-0001Yv-30 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:26 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:37269) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoC-0001Xy-TC for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:25 -0500 Received: by mail-wm1-x32e.google.com with SMTP id g67so1518126wmd.2 for ; Mon, 07 Jan 2019 08:31:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vDv66PJYZ8IkWxNWsE5Oc2nyeU86TpAONaK01uxo88o=; b=foYto4/VFLT7mpeJScvAU6fdpGwPCbQUtnHbLiG7ukl7cXWyenelGEL8bfxvIx785n dIbr9/4IdVGBUCzUaSxvPqNy2euzp0nOa3V2Al4VTMMzW1I2QZPUyUwDrtFlaB1r1IkY nFqNg+tilEX0Z9cRwZgh/ATapcfSjokybV13k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vDv66PJYZ8IkWxNWsE5Oc2nyeU86TpAONaK01uxo88o=; b=Zgd66roTj6OGlIK+917mpc2Fpkmkqzs5lOe6iJYb5yhgEbkm/vMnLbD97TuSKKXctZ Fd1yKTSCW5pC3po3M/u6h3th8EX4tgrSI+Y+aB84SJIROLqMIlMzpAkbMx0JIrCQCJGd d/j6NIQCMsUeML2CsgJBLJj2YeyYgsNBfh1qx68WAlYcVHzvUPKp1Wo/DIZwvor3wlLF VYtC5+Ypd7GWWNzZ6Cb8x6eVhcGrpUnI/cYXl7aCPMkd58sbK9w93nUF5BoVBz2ZbmdH ATwjFoy3q3UUKtMqLNHExMDGfqp9TbyhGdBTq2Gwj2xbcHMLLf43LoLTYvqLqBzWirje 3soQ== X-Gm-Message-State: AJcUukcIhpYSH1hhnX8YBQzyVYzhdga4bFGqAFSRJMGhaZCNgG2Ij5RX aKoP6zF3rS0KfUf5rjTayiUoJOvkpme6rA== X-Google-Smtp-Source: ALg8bN6JfNxyKFFIQfwB0oRR4D/cvjbi0iWe74X1rGxL9w2D/Gadl8QSHb96f/dV41eX2lYGULT0xA== X-Received: by 2002:a1c:cbc7:: with SMTP id b190mr9977142wmg.13.1546878683528; Mon, 07 Jan 2019 08:31:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:42 +0000 Message-Id: <20190107163117.16269-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 02/37] target/arm: SVE brk[ab] merging does not have s bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson While brk[ab] zeroing has a flags setting option, the merging variant does not. Retain the same argument structure, to share expansion but force the flag zero and do not decode bit 22. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20181226215003.31438-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/sve.decode | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e10b689454e..4f580a25e70 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -99,6 +99,7 @@ =20 # Two operand with governing predicate, flags setting @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s +@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s= =3D0 =20 # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz e= sz=3D0 @@ -667,8 +668,8 @@ BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 ..= .. @pd_pg_pn_pm_s # SVE partition break condition BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s -BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s -BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s +BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_= s0 +BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_= s0 =20 # SVE propagate break to next partition BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879040529247.1802575997524; Mon, 7 Jan 2019 08:37:20 -0800 (PST) Received: from localhost ([127.0.0.1]:43566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXte-0000EH-C6 for importer@patchew.org; Mon, 07 Jan 2019 11:37:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoG-0004mj-Cl for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoE-0001b5-ME for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:28 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40571) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoE-0001Zk-D1 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:26 -0500 Received: by mail-wr1-x429.google.com with SMTP id p4so1062139wrt.7 for ; Mon, 07 Jan 2019 08:31:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5VuVI331ytNyDlTx9NKnef1XgHmbGjUAdHkiXIl1t78=; b=JPEJhmgNkL+40L5rlrapeRorywEUpFJ4D5hCYENdHjAKedOy1VV09iy1f4Udhi7Em7 HuNR9BI/8DPoKc/S9PfjXAlgceSScmSMNq2gNx4NGugoPICemJufXISiUizCH54SL5rH lFGxsaLeeGfeDKvvXh2Sn2LNZMKhFVEPc2Olk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5VuVI331ytNyDlTx9NKnef1XgHmbGjUAdHkiXIl1t78=; b=s5ZgQuMNH/SeAWNr8gDBWWOewARgeiOAGOcAA5VVh+riAvkgmb+S4noc3DJ5IfqgIH iZUvn0ZTDGN6+xGcVt8vA4S2j6O4tiDRvT4dV8YvGJYpnHfpOOzBL4YDOv0HBNxV/udu 97vFlUgkAeL2gp8N+l42DaylbZOiLaLqZWtHClZImTeIXpB04zjsSt9zvrfmj+wnlh4U eSpZG/6a+13LNQDpNeiotN++sUhoyexhb0kXcCUkJLjnQJRuUNZhZfskqPxb+3sVNx/a MZ6RfTWD1MkY0PqFEvYE4rG1DoDuXdayURhxmtAZXSr4KLLbClmEIyNR0JajXGHIbCBj 9M2g== X-Gm-Message-State: AJcUukeLMMdmLKawmodY3ttyWJ+29PZ2bsKnlDfmuAB0C2Dt4itaZctb donwFXPny+inERk7OWjTfgTGVOrzsPKktA== X-Google-Smtp-Source: ALg8bN7kZVQCSHAG6mCFYCjIlY1a9FwAeF3rOdhSnrpuJoEFNiKs+2ABfRQi5Ram+IX02OGvz8rRDg== X-Received: by 2002:a5d:6244:: with SMTP id m4mr41722713wrv.314.1546878684935; Mon, 07 Jan 2019 08:31:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:43 +0000 Message-Id: <20190107163117.16269-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 03/37] hw/cpu: introduce CPU clusters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel This commit adds the cpu-cluster type. It aims at gathering CPUs from the same cluster in a machine. For now it only has a `cluster-id` property. Documentation in cluster.h written with the help of Peter Maydell. Signed-off-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-2-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/cpu/Makefile.objs | 2 +- include/hw/cpu/cluster.h | 58 ++++++++++++++++++++++++++++++++++++++++ hw/cpu/cluster.c | 50 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 ++ 4 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 include/hw/cpu/cluster.h create mode 100644 hw/cpu/cluster.c diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index cd52d20b652..8db9e8a7b3c 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -2,4 +2,4 @@ obj-$(CONFIG_ARM11MPCORE) +=3D arm11mpcore.o obj-$(CONFIG_REALVIEW) +=3D realview_mpcore.o obj-$(CONFIG_A9MPCORE) +=3D a9mpcore.o obj-$(CONFIG_A15MPCORE) +=3D a15mpcore.o -common-obj-y +=3D core.o +common-obj-y +=3D core.o cluster.o diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h new file mode 100644 index 00000000000..73818232437 --- /dev/null +++ b/include/hw/cpu/cluster.h @@ -0,0 +1,58 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef HW_CPU_CLUSTER_H +#define HW_CPU_CLUSTER_H + +#include "qemu/osdep.h" +#include "hw/qdev.h" + +/* + * CPU Cluster type + * + * A cluster is a group of CPUs which are all identical and have the same = view + * of the rest of the system. It is mainly an internal QEMU representation= and + * does not necessarily match with the notion of clusters on the real hard= ware. + * + * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs = in an + * Arm big.LITTLE system) they should be in different clusters. If the CPU= s do + * not have the same view of memory (for example the main CPU and a manage= ment + * controller processor) they should be in different clusters. + */ + +#define TYPE_CPU_CLUSTER "cpu-cluster" +#define CPU_CLUSTER(obj) \ + OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) + +/** + * CPUClusterState: + * @cluster_id: The cluster ID. This value is for internal use only and sh= ould + * not be exposed directly to the user or to the guest. + * + * State of a CPU cluster. + */ +typedef struct CPUClusterState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + uint32_t cluster_id; +} CPUClusterState; + +#endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c new file mode 100644 index 00000000000..9d50a235d5c --- /dev/null +++ b/hw/cpu/cluster.c @@ -0,0 +1,50 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "hw/cpu/cluster.h" +#include "qapi/error.h" +#include "qemu/module.h" + +static Property cpu_cluster_properties[] =3D { + DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void cpu_cluster_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D cpu_cluster_properties; +} + +static const TypeInfo cpu_cluster_type_info =3D { + .name =3D TYPE_CPU_CLUSTER, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CPUClusterState), + .class_init =3D cpu_cluster_class_init, +}; + +static void cpu_cluster_register_types(void) +{ + type_register_static(&cpu_cluster_type_info); +} + +type_init(cpu_cluster_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 19792cfb2da..471161742de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1195,7 +1195,9 @@ M: Marcel Apfelbaum S: Supported F: hw/core/machine.c F: hw/core/null-machine.c +F: hw/cpu/cluster.c F: include/hw/boards.h +F: include/hw/cpu/cluster.h T: git https://github.com/ehabkost/qemu.git machine-next =20 Xtensa Machines --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879202593652.5040009983239; Mon, 7 Jan 2019 08:40:02 -0800 (PST) Received: from localhost ([127.0.0.1]:44309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXwX-0002kf-HI for importer@patchew.org; Mon, 07 Jan 2019 11:40:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoI-0004nw-AW for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoG-0001dy-DN for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:30 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:52182) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoF-0001bi-Rl for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:28 -0500 Received: by mail-wm1-x332.google.com with SMTP id b11so1465566wmj.1 for ; Mon, 07 Jan 2019 08:31:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vMh6xY1GMYIdM+kfMAqkwNArXmtcSl7a//C6INwAbMg=; b=Ih4zsYxfRe5gaXs5f6pLlb8USSLIsBEWtIWtBCmaBWAn9jG4C2bP8S6Ae9qly9dyxe X+PJ3Om4GEKLTocjwwTuv+A8VN1wsv/UMgd64YBX+Roo/rnycTIikOAd9cgpk294ch2b /PFpH94n0yTqOwldoAhjzk5rhVsIjNsFNIIZ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vMh6xY1GMYIdM+kfMAqkwNArXmtcSl7a//C6INwAbMg=; b=GWszZD8cXS8nN2d+woGfHjYTFItWwmI8zJX+l4DYOauxbVVXgiC42sm/wfKTe962qd dAaTCBPlDgIBKGeBFrujJGEundqmSIAE50UKfqLOu+rYT8xTu0BWnscb4muF6F2Ndsur jX/7V6BiWSNzTtptSktQ2fzhu4aVWnk2WROtV6I/1B3bLQkxq9IJZxl3q7DjytS564DR aqf4IRJGRrxVSe2fRTlaoyrPo3Jetve5mV+9Szq0ciinG2pr6L9M5TmObe083Z+vSaoY k/zm1gsobpa9HKDx62OxbQ9IGs13oxfCND1/y3sqAM8LN9e5vcrgZd29NLE2GEkRAO0o XWzw== X-Gm-Message-State: AJcUukfqc5eEpCLBuNIwZtkK0xhmT3kfcZJHzZLr4F22ccNg6JLShNRx 7UtwoVgDnMY//OVZFUnmWHBo1osenHBQew== X-Google-Smtp-Source: ALg8bN60rB2GYXdqTjvl9JUPFZPpJdGZIdfCNncjBezJdmdzPRe8Lxk6hs+eO1ELF4Cps41PEwUfCg== X-Received: by 2002:a1c:13d1:: with SMTP id 200mr9078593wmt.4.1546878686243; Mon, 07 Jan 2019 08:31:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:44 +0000 Message-Id: <20190107163117.16269-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 Subject: [Qemu-devel] [PULL 04/37] gdbstub: introduce GDB processes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add a structure GDBProcess that represents processes from the GDB semantic point of view. CPUs can be split into different processes, by grouping them under different cpu-cluster objects. Each occurrence of a cpu-cluster object implies the existence of the corresponding process in the GDB stub. The GDB process ID is derived from the corresponding cluster ID as follows: GDB PID =3D cluster ID + 1 This is because PIDs -1 and 0 are reserved in GDB and cannot be used by processes. A default process is created to handle CPUs that are not in a cluster. This process gets the PID of the last process PID + 1. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20181207090135.7651-3-luc.michel@greensocs.com [PMM: fixed checkpatch nit about block comment style] Signed-off-by: Peter Maydell --- gdbstub.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index c4e4f9f0821..9ac6f19a186 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -29,6 +29,7 @@ #include "chardev/char-fe.h" #include "sysemu/sysemu.h" #include "exec/gdbstub.h" +#include "hw/cpu/cluster.h" #endif =20 #define MAX_PACKET_LENGTH 4096 @@ -296,6 +297,11 @@ typedef struct GDBRegisterState { struct GDBRegisterState *next; } GDBRegisterState; =20 +typedef struct GDBProcess { + uint32_t pid; + bool attached; +} GDBProcess; + enum RSState { RS_INACTIVE, RS_IDLE, @@ -324,6 +330,9 @@ typedef struct GDBState { CharBackend chr; Chardev *mon_chr; #endif + bool multiprocess; + GDBProcess *processes; + int process_num; char syscall_buf[256]; gdb_syscall_complete_cb current_syscall_cb; } GDBState; @@ -1751,6 +1760,30 @@ void gdb_exit(CPUArchState *env, int code) #endif } =20 +/* + * Create the process that will contain all the "orphan" CPUs (that are not + * part of a CPU cluster). Note that if this process contains no CPUs, it = won't + * be attachable and thus will be invisible to the user. + */ +static void create_default_process(GDBState *s) +{ + GDBProcess *process; + int max_pid =3D 0; + + if (s->process_num) { + max_pid =3D s->processes[s->process_num - 1].pid; + } + + s->processes =3D g_renew(GDBProcess, s->processes, ++s->process_num); + process =3D &s->processes[s->process_num - 1]; + + /* We need an available PID slot for this process */ + assert(max_pid < UINT32_MAX); + + process->pid =3D max_pid + 1; + process->attached =3D false; +} + #ifdef CONFIG_USER_ONLY int gdb_handlesig(CPUState *cpu, int sig) @@ -1848,6 +1881,7 @@ static bool gdb_accept(void) s =3D g_malloc0(sizeof(GDBState)); s->c_cpu =3D first_cpu; s->g_cpu =3D first_cpu; + create_default_process(s); s->fd =3D fd; gdb_has_xml =3D false; =20 @@ -2004,6 +2038,65 @@ static const TypeInfo char_gdb_type_info =3D { .class_init =3D char_gdb_class_init, }; =20 +static int find_cpu_clusters(Object *child, void *opaque) +{ + if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { + GDBState *s =3D (GDBState *) opaque; + CPUClusterState *cluster =3D CPU_CLUSTER(child); + GDBProcess *process; + + s->processes =3D g_renew(GDBProcess, s->processes, ++s->process_nu= m); + + process =3D &s->processes[s->process_num - 1]; + + /* + * GDB process IDs -1 and 0 are reserved. To avoid subtle errors at + * runtime, we enforce here that the machine does not use a cluste= r ID + * that would lead to PID 0. + */ + assert(cluster->cluster_id !=3D UINT32_MAX); + process->pid =3D cluster->cluster_id + 1; + process->attached =3D false; + + return 0; + } + + return object_child_foreach(child, find_cpu_clusters, opaque); +} + +static int pid_order(const void *a, const void *b) +{ + GDBProcess *pa =3D (GDBProcess *) a; + GDBProcess *pb =3D (GDBProcess *) b; + + if (pa->pid < pb->pid) { + return -1; + } else if (pa->pid > pb->pid) { + return 1; + } else { + return 0; + } +} + +static void create_processes(GDBState *s) +{ + object_child_foreach(object_get_root(), find_cpu_clusters, s); + + if (s->processes) { + /* Sort by PID */ + qsort(s->processes, s->process_num, sizeof(s->processes[0]), pid_o= rder); + } + + create_default_process(s); +} + +static void cleanup_processes(GDBState *s) +{ + g_free(s->processes); + s->process_num =3D 0; + s->processes =3D NULL; +} + int gdbserver_start(const char *device) { trace_gdbstub_op_start(device); @@ -2060,11 +2153,15 @@ int gdbserver_start(const char *device) } else { qemu_chr_fe_deinit(&s->chr, true); mon_chr =3D s->mon_chr; + cleanup_processes(s); memset(s, 0, sizeof(GDBState)); s->mon_chr =3D mon_chr; } s->c_cpu =3D first_cpu; s->g_cpu =3D first_cpu; + + create_processes(s); + if (chr) { qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_rec= eive, --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546878909942360.2908152295539; Mon, 7 Jan 2019 08:35:09 -0800 (PST) Received: from localhost ([127.0.0.1]:43084 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXro-00076n-OI for importer@patchew.org; Mon, 07 Jan 2019 11:35:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoM-0004r5-9W for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoK-0001jx-By for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:34 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38967) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoI-0001eH-Ca for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:32 -0500 Received: by mail-wr1-x42a.google.com with SMTP id t27so1064602wra.6 for ; Mon, 07 Jan 2019 08:31:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aPHEkDUEPKX+Od0Ed7JXhMgvIC4t96wvbymS1WuuHm0=; b=WslWoJoklxFVEw6ZRYOuxjj1zIVe8co8EwsZFO/Pnt3POs+LaHf6sv3ohHHka5kBGr hQVE29EUZpgNuyP8TLymQoosK8/W2E8nMdOdKjbdeDzgTDR6SIC4Gxw7EOhq/G0tYihL eJMKc8Skms3y4iUFmrI+5rldUBWk5QE0DWRY4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aPHEkDUEPKX+Od0Ed7JXhMgvIC4t96wvbymS1WuuHm0=; b=tp1ZABW4npO/Z7MNk/jDR1kwE6nfsrpXXRCT48W6K4ksHtUwfwb+MTkZfT/BVmB6Mc aszCUd1Hd7loBzOLaDF+74zaR7fIsk+WQujQYsuFVQFgySFlR0lfvQSlVpc9Cmi4ufeg LLgabE78a7+aYeL5SgGYQiFYzv7Cxg4zIbrK7U7CzuRdFtTa6dyx8oTrUaWELHd5MAdN f3Qyl7bUzPEW8yDZ7S+s5zFfMquxGzZyS1OK/GNMj+i4CjOXG59N0E+cv2PkUpwuWenO bzd0NInx6NQCVC5Iqlhf17fMXc1bUqwvt3aTM43aKsgOse55cstUNobgDOk/Zr6xJGGF EcJQ== X-Gm-Message-State: AJcUukdduR121ect45bCJkyY1Sn9/UIPYFHl94dljraak9meYrD6r2X9 Lbhwc4Mu7RfExOqHq5CmPScbHQhxj1UFDw== X-Google-Smtp-Source: ALg8bN5hZltGhIHDO1Xx+iOPCTdYLB9LzAMP6Mo/qOKe5pWG76cDWTlXp5RE4pPdCIWnptqAi3p85g== X-Received: by 2002:adf:9d4c:: with SMTP id o12mr49121883wre.94.1546878687488; Mon, 07 Jan 2019 08:31:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:45 +0000 Message-Id: <20190107163117.16269-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 05/37] gdbstub: add multiprocess support to '?' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luc Michel The gdb_get_cpu_pid() function does the PID lookup for the given CPU. It checks if the CPU is a direct child of a CPU cluster. If it is, the returned PID is the cluster ID plus one (cluster IDs start at 0, GDB PIDs at 1). When the CPU is not a child of such a container, the PID of the default process is returned. The gdb_fmt_thread_id() function generates the string to be used to identify a given thread, in a response packet for the peer. This function supports generating thread IDs when multiprocess mode is enabled (in the form `p.'). Use them in the reply to a '?' request. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-4-luc.michel@greensocs.com [PMM: fixed checkpatch blockquote style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 9ac6f19a186..02beb44d973 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -640,6 +640,54 @@ static int memtox(char *buf, const char *mem, int len) return p - buf; } =20 +static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) +{ +#ifndef CONFIG_USER_ONLY + gchar *path, *name =3D NULL; + Object *obj; + CPUClusterState *cluster; + uint32_t ret; + + path =3D object_get_canonical_path(OBJECT(cpu)); + + if (path =3D=3D NULL) { + /* Return the default process' PID */ + ret =3D s->processes[s->process_num - 1].pid; + goto out; + } + + name =3D object_get_canonical_path_component(OBJECT(cpu)); + assert(name !=3D NULL); + + /* + * Retrieve the CPU parent path by removing the last '/' and the CPU n= ame + * from the CPU canonical path. + */ + path[strlen(path) - strlen(name) - 1] =3D '\0'; + + obj =3D object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); + + if (obj =3D=3D NULL) { + /* Return the default process' PID */ + ret =3D s->processes[s->process_num - 1].pid; + goto out; + } + + cluster =3D CPU_CLUSTER(obj); + ret =3D cluster->cluster_id + 1; + +out: + g_free(name); + g_free(path); + + return ret; + +#else + /* TODO: In user mode, we should use the task state PID */ + return s->processes[s->process_num - 1].pid; +#endif +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -909,6 +957,19 @@ static CPUState *find_cpu(uint32_t thread_id) return NULL; } =20 +static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, + char *buf, size_t buf_size) +{ + if (s->multiprocess) { + snprintf(buf, buf_size, "p%02x.%02x", + gdb_get_cpu_pid(s, cpu), cpu_gdb_index(cpu)); + } else { + snprintf(buf, buf_size, "%02x", cpu_gdb_index(cpu)); + } + + return buf; +} + static int is_query_packet(const char *p, const char *query, char separato= r) { unsigned int query_len =3D strlen(query); @@ -1020,6 +1081,7 @@ static int gdb_handle_packet(GDBState *s, const char = *line_buf) int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; char buf[sizeof(mem_buf) + 1 /* trailing NUL */]; + char thread_id[16]; uint8_t *registers; target_ulong addr, len; =20 @@ -1030,8 +1092,8 @@ static int gdb_handle_packet(GDBState *s, const char = *line_buf) switch(ch) { case '?': /* TODO: Make this return the correct value for user-mode. */ - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP, - cpu_gdb_index(s->c_cpu)); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, s->c_cpu, thread_id, sizeof(thread_i= d))); put_packet(s, buf); /* Remove all the breakpoints when this query is issued, * because gdb is doing and initial connect and the state --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879096850860.4457647123884; Mon, 7 Jan 2019 08:38:16 -0800 (PST) Received: from localhost ([127.0.0.1]:43873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXuo-0001Gp-LP for importer@patchew.org; Mon, 07 Jan 2019 11:38:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46086) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoM-0004r6-9a for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoK-0001k1-CS for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:34 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:35428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoJ-0001fn-EA for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:32 -0500 Received: by mail-wm1-x32d.google.com with SMTP id t200so1538751wmt.0 for ; Mon, 07 Jan 2019 08:31:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Aq92C83LcKOoCWdBYbpQh+pRHAX7dVL7eocp+7k0PFc=; b=a8Y7I9rFn+HIiFkJFYqISMz9ggRmRfsei0PoqWnFbdVLwLot1N+l6kRAHejeOVJrek ZJDhVzKisc2+Dn38bygAm6Nk/1//9+mMi0CHogy++y3C/q/RNepq57y/X/XKkBShvJUr Dc/IM6S0l0/m0f7pb7oPFOIGFdZSIaApyUG1c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aq92C83LcKOoCWdBYbpQh+pRHAX7dVL7eocp+7k0PFc=; b=neplLyRNNHSfJjJViAshb1wZvDBQ1ULUwa0Z+iberUUHqjeylso/rBERhhceeSM337 cvCyiroN5N0DRi+NFiltTkdGKylpNIt3zM+SUum7AEFuh5506tK/N4A7QjGKc90eljjI GLhyStnuJW8VFBlO5hKFFpzPi0xWuMG61n7o6SS+XwdxCCGdB2i8btJnBzoYNbKlcXdp KoNxCzA6PXdxAi+Y8CW80VNCMTLkVUYKuC4Z4ab3AORGd0SP3TC9PygTaeOWuV/7yS5N bUvw/wimh4h9dZAk4yLyCiXHaTer5D/rMECnYx7IZBUgudbmS5VUf6eHddaBZj/FNRVm bQug== X-Gm-Message-State: AJcUukd6xVeKthSyu+rxEcNh60jdfJDxEyiF9lmbedXlGqbFE4rB5RXX flvgGCRQWyB3qOh7yYFCwrXFNDOpNw4kig== X-Google-Smtp-Source: ALg8bN7MlO/oOm/CYxQRFGtOSdVcP7HNWPQ8V0RirC+MJe9uqgoe6jQrmF7jTXXcfPorCiWtz6I37Q== X-Received: by 2002:a1c:a503:: with SMTP id o3mr9159481wme.122.1546878688892; Mon, 07 Jan 2019 08:31:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:46 +0000 Message-Id: <20190107163117.16269-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 06/37] gdbstub: add multiprocess support to 'H' and 'T' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add a couple of helper functions to cope with GDB threads and processes. The gdb_get_process() function looks for a process given a pid. The gdb_get_cpu() function returns the CPU corresponding to the (pid, tid) pair given as parameters. The read_thread_id() function parses the thread-id sent by the peer. This function supports the multiprocess extension thread-id syntax. The return value specifies if the parsing failed, or if a special case was encountered (all processes or all threads). Use them in 'H' and 'T' packets handling to support the multiprocess extension. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-5-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 136 insertions(+), 18 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 02beb44d973..644377db9f5 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -688,6 +688,71 @@ out: #endif } =20 +static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid) +{ + int i; + + if (!pid) { + /* 0 means any process, we take the first one */ + return &s->processes[0]; + } + + for (i =3D 0; i < s->process_num; i++) { + if (s->processes[i].pid =3D=3D pid) { + return &s->processes[i]; + } + } + + return NULL; +} + +static GDBProcess *gdb_get_cpu_process(const GDBState *s, CPUState *cpu) +{ + return gdb_get_process(s, gdb_get_cpu_pid(s, cpu)); +} + +static CPUState *find_cpu(uint32_t thread_id) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (cpu_gdb_index(cpu) =3D=3D thread_id) { + return cpu; + } + } + + return NULL; +} + +static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) +{ + GDBProcess *process; + CPUState *cpu; + + if (!tid) { + /* 0 means any thread, we take the first one */ + tid =3D 1; + } + + cpu =3D find_cpu(tid); + + if (cpu =3D=3D NULL) { + return NULL; + } + + process =3D gdb_get_cpu_process(s, cpu); + + if (process->pid !=3D pid) { + return NULL; + } + + if (!process->attached) { + return NULL; + } + + return cpu; +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -944,19 +1009,6 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong = pc) cpu_set_pc(cpu, pc); } =20 -static CPUState *find_cpu(uint32_t thread_id) -{ - CPUState *cpu; - - CPU_FOREACH(cpu) { - if (cpu_gdb_index(cpu) =3D=3D thread_id) { - return cpu; - } - } - - return NULL; -} - static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, char *buf, size_t buf_size) { @@ -970,6 +1022,60 @@ static char *gdb_fmt_thread_id(const GDBState *s, CPU= State *cpu, return buf; } =20 +typedef enum GDBThreadIdKind { + GDB_ONE_THREAD =3D 0, + GDB_ALL_THREADS, /* One process, all threads */ + GDB_ALL_PROCESSES, + GDB_READ_THREAD_ERR +} GDBThreadIdKind; + +static GDBThreadIdKind read_thread_id(const char *buf, const char **end_bu= f, + uint32_t *pid, uint32_t *tid) +{ + unsigned long p, t; + int ret; + + if (*buf =3D=3D 'p') { + buf++; + ret =3D qemu_strtoul(buf, &buf, 16, &p); + + if (ret) { + return GDB_READ_THREAD_ERR; + } + + /* Skip '.' */ + buf++; + } else { + p =3D 1; + } + + ret =3D qemu_strtoul(buf, &buf, 16, &t); + + if (ret) { + return GDB_READ_THREAD_ERR; + } + + *end_buf =3D buf; + + if (p =3D=3D -1) { + return GDB_ALL_PROCESSES; + } + + if (pid) { + *pid =3D p; + } + + if (t =3D=3D -1) { + return GDB_ALL_THREADS; + } + + if (tid) { + *tid =3D t; + } + + return GDB_ONE_THREAD; +} + static int is_query_packet(const char *p, const char *query, char separato= r) { unsigned int query_len =3D strlen(query); @@ -1078,12 +1184,14 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) CPUClass *cc; const char *p; uint32_t thread; + uint32_t pid, tid; int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; char buf[sizeof(mem_buf) + 1 /* trailing NUL */]; char thread_id[16]; uint8_t *registers; target_ulong addr, len; + GDBThreadIdKind thread_kind; =20 trace_gdbstub_io_command(line_buf); =20 @@ -1291,12 +1399,18 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) break; case 'H': type =3D *p++; - thread =3D strtoull(p, (char **)&p, 16); - if (thread =3D=3D -1 || thread =3D=3D 0) { + + thread_kind =3D read_thread_id(p, &p, &pid, &tid); + if (thread_kind =3D=3D GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + + if (thread_kind !=3D GDB_ONE_THREAD) { put_packet(s, "OK"); break; } - cpu =3D find_cpu(thread); + cpu =3D gdb_get_cpu(s, pid, tid); if (cpu =3D=3D NULL) { put_packet(s, "E22"); break; @@ -1316,8 +1430,12 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) } break; case 'T': - thread =3D strtoull(p, (char **)&p, 16); - cpu =3D find_cpu(thread); + thread_kind =3D read_thread_id(p, &p, &pid, &tid); + if (thread_kind =3D=3D GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu =3D gdb_get_cpu(s, pid, tid); =20 if (cpu !=3D NULL) { put_packet(s, "OK"); --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879394186980.9134144713199; Mon, 7 Jan 2019 08:43:14 -0800 (PST) Received: from localhost ([127.0.0.1]:45043 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXzR-0005Li-0W for importer@patchew.org; Mon, 07 Jan 2019 11:43:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoP-0004tM-VD for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoM-0001nT-BH for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:36 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:42843) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoK-0001hp-AO for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:34 -0500 Received: by mail-wr1-x42c.google.com with SMTP id q18so1047302wrx.9 for ; Mon, 07 Jan 2019 08:31:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6Q1htC/UokkIYz5uiEFuAKSsnFkHc99ED2dIgHQgmjw=; b=CdO74wg9/aSczH0jPqUFE1Z4GOIlaew0fUX8gEoKWharc7NwwYeu+xyfqZ/p6MyYrH hNecfC7NUlrZ94vY2983IvOenSlb424GQaijg9Av1eDUj/RFf4IpicDZonhBX7iBrDP2 b/WXkzVfeFHNMIaZh/hF3BCzrXZDqe4xWjkkw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Q1htC/UokkIYz5uiEFuAKSsnFkHc99ED2dIgHQgmjw=; b=kQSEdG0y6LpbP493ONO8K8xCchBtofb2UtLrnzhzgqvWiYlw4EGFUAjI2vszTuiBVk 1OkCcVM+KKDbsqsiU5YSL2e5ouaL3Kkdtq9hR8q+OIJe3onISwgfz03fvTYeGJ0fdik0 OZrEoFGXOVEsxAhgh+WcemzFCv1HJQR34+COgbugkSkG7T06y/0uD7yo9V5VMqgfYnxM xn6/FHK8wRNf0H7XDXW6nBsj7pM5jY5H3AY7X4XJYu/dE/sCNoG1XEPQQ8SqWq9cAWQk 4kDjELIjZ0aKa9xS5aeqBscp4LkfYiVEQUdHa+AXmT6WzOdRmS62fR3ARjGpjThuGXIm iKUw== X-Gm-Message-State: AJcUukfQBopMYb2BkFJlxoLFNHdk6KPelGd6MRKsJ+HcRQw8p7vPnhkC rV29drFm3dqajb7uCD+0bF2kW9LDzDhDCg== X-Google-Smtp-Source: ALg8bN4FOOtStcru0IgqNzfHm97JtCUPDC4JhzKRqjQgFJRDoqt9nkRwMyKm3qJMAs3MpZLaCbDpfg== X-Received: by 2002:a5d:6450:: with SMTP id d16mr52214294wrw.64.1546878690219; Mon, 07 Jan 2019 08:31:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:47 +0000 Message-Id: <20190107163117.16269-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 07/37] gdbstub: add multiprocess support to vCont packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add the gdb_first_attached_cpu() and gdb_next_attached_cpu() to iterate over all the CPUs in currently attached processes. Add the gdb_first_cpu_in_process() and gdb_next_cpu_in_process() to iterate over CPUs of a given process. Use them to add multiprocess extension support to vCont packets. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-6-luc.michel@greensocs.com [PMM: corrected checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 100 insertions(+), 15 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 644377db9f5..09114ea7769 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -724,6 +724,36 @@ static CPUState *find_cpu(uint32_t thread_id) return NULL; } =20 +static CPUState *get_first_cpu_in_process(const GDBState *s, + GDBProcess *process) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (gdb_get_cpu_pid(s, cpu) =3D=3D process->pid) { + return cpu; + } + } + + return NULL; +} + +static CPUState *gdb_next_cpu_in_process(const GDBState *s, CPUState *cpu) +{ + uint32_t pid =3D gdb_get_cpu_pid(s, cpu); + cpu =3D CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_pid(s, cpu) =3D=3D pid) { + break; + } + + cpu =3D CPU_NEXT(cpu); + } + + return cpu; +} + static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) { GDBProcess *process; @@ -753,6 +783,35 @@ static CPUState *gdb_get_cpu(const GDBState *s, uint32= _t pid, uint32_t tid) return cpu; } =20 +/* Return the cpu following @cpu, while ignoring unattached processes. */ +static CPUState *gdb_next_attached_cpu(const GDBState *s, CPUState *cpu) +{ + cpu =3D CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_process(s, cpu)->attached) { + break; + } + + cpu =3D CPU_NEXT(cpu); + } + + return cpu; +} + +/* Return the first attached cpu */ +static CPUState *gdb_first_attached_cpu(const GDBState *s) +{ + CPUState *cpu =3D first_cpu; + GDBProcess *process =3D gdb_get_cpu_process(s, cpu); + + if (!process->attached) { + return gdb_next_attached_cpu(s, cpu); + } + + return cpu; +} + static const char *get_feature_xml(const char *p, const char **newp, CPUClass *cc) { @@ -1091,10 +1150,12 @@ static int is_query_packet(const char *p, const cha= r *query, char separator) */ static int gdb_handle_vcont(GDBState *s, const char *p) { - int res, idx, signal =3D 0; + int res, signal =3D 0; char cur_action; char *newstates; unsigned long tmp; + uint32_t pid, tid; + GDBProcess *process; CPUState *cpu; #ifdef CONFIG_USER_ONLY int max_cpus =3D 1; /* global variable max_cpus exists only in system = mode */ @@ -1137,25 +1198,48 @@ static int gdb_handle_vcont(GDBState *s, const char= *p) res =3D -ENOTSUP; goto out; } - /* thread specification. special values: (none), -1 =3D all; 0 =3D= any */ - if ((p[0] =3D=3D ':' && p[1] =3D=3D '-' && p[2] =3D=3D '1') || (p[= 0] !=3D ':')) { - if (*p =3D=3D ':') { - p +=3D 3; - } - for (idx =3D 0; idx < max_cpus; idx++) { - if (newstates[idx] =3D=3D 1) { - newstates[idx] =3D cur_action; + + if (*p++ !=3D ':') { + res =3D -ENOTSUP; + goto out; + } + + switch (read_thread_id(p, &p, &pid, &tid)) { + case GDB_READ_THREAD_ERR: + res =3D -EINVAL; + goto out; + + case GDB_ALL_PROCESSES: + cpu =3D gdb_first_attached_cpu(s); + while (cpu) { + if (newstates[cpu->cpu_index] =3D=3D 1) { + newstates[cpu->cpu_index] =3D cur_action; } + + cpu =3D gdb_next_attached_cpu(s, cpu); } - } else if (*p =3D=3D ':') { - p++; - res =3D qemu_strtoul(p, &p, 16, &tmp); - if (res) { + break; + + case GDB_ALL_THREADS: + process =3D gdb_get_process(s, pid); + + if (!process->attached) { + res =3D -EINVAL; goto out; } =20 - /* 0 means any thread, so we pick the first valid CPU */ - cpu =3D tmp ? find_cpu(tmp) : first_cpu; + cpu =3D get_first_cpu_in_process(s, process); + while (cpu) { + if (newstates[cpu->cpu_index] =3D=3D 1) { + newstates[cpu->cpu_index] =3D cur_action; + } + + cpu =3D gdb_next_cpu_in_process(s, cpu); + } + break; + + case GDB_ONE_THREAD: + cpu =3D gdb_get_cpu(s, pid, tid); =20 /* invalid CPU/thread specified */ if (!cpu) { @@ -1167,6 +1251,7 @@ static int gdb_handle_vcont(GDBState *s, const char *= p) if (newstates[cpu->cpu_index] =3D=3D 1) { newstates[cpu->cpu_index] =3D cur_action; } + break; } } s->signal =3D signal; --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154687955922347.98935490551446; Mon, 7 Jan 2019 08:45:59 -0800 (PST) Received: from localhost ([127.0.0.1]:45740 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY2I-0007xP-6D for importer@patchew.org; Mon, 07 Jan 2019 11:45:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoR-0004ue-Cm for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoO-0001rx-P6 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:38 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoM-0001iy-Ai for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:35 -0500 Received: by mail-wm1-x32f.google.com with SMTP id n190so1469885wmd.0 for ; Mon, 07 Jan 2019 08:31:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YmllhqSrlPuqu/kNnOCys3nYm3gqrfzNAGZ2x7fkAlw=; b=IB5vzVrmErKVL/AydwAR6mFEVp1IZtovJn+U3XZsIBFYUv2Rv7W773o7vfg3xh5sKv WCgf06mneblIbhy3fVdF/g0GM1gq7Sky3+qUkkL0dSVIU23hg6RLiocIKtYH7azyD89j ON8HQndOwu+HECfzEgk4RhDDBbKhITKtBqwas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YmllhqSrlPuqu/kNnOCys3nYm3gqrfzNAGZ2x7fkAlw=; b=aFbN4iq3t02iZ3p2huErTIbPDZ7Z74nYXLyvzegzLfRk4ieKT/q26Kocw3ba8opDvk BUXJKCEgiY9qvlM5yzOqR/QqjG8er05mZOYMbhQ6h78PCaVGUR5/cfmz0l7wCiRCauXC pnnwwNk0jYFwhuLz+amywNTMjia+rKLmn3mlQ/b5vJMb78DnYwPfCn8FnBtxZqEyCtDV /iH1P27gG4XAd7aRIX8H5SsR7GNrofqXLhRrxdqmy9nFcHL3buduJGEQ4eBLSnuIAz1s i/1PNs4HJkPd8vhcJ6XpCw+BGIOkGBrBuF858/cc8Pkw/k0R2oeya46q7y9AKsvHzhaV aXpQ== X-Gm-Message-State: AJcUukdM6rcqwU6TaubsWiUKA8gplKCzVwYxQrJLYZhR2Ji9+5NmsKlZ 4VneRNBLJ6Ed33W4/mPOd/cKfnzLmvi44A== X-Google-Smtp-Source: ALg8bN73Q+GJOOWnS6Pns7eCc97zecwZYA9gNI09LZUfBKF/wx5vP594bcQU/u13qnH/pjb3x07uug== X-Received: by 2002:a1c:2408:: with SMTP id k8mr8833322wmk.110.1546878691257; Mon, 07 Jan 2019 08:31:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:48 +0000 Message-Id: <20190107163117.16269-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 08/37] gdbstub: add multiprocess support to 'sC' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Change the sC packet handling to support the multiprocess extension. Instead of returning the first thread, we return the first thread of the current process. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-7-luc.michel@greensocs.com [PMM: corrected checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 09114ea7769..1ba7aa6a28a 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1554,9 +1554,15 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) put_packet(s, "OK"); break; } else if (strcmp(p,"C") =3D=3D 0) { - /* "Current thread" remains vague in the spec, so always return - * the first CPU (gdb returns the first thread). */ - put_packet(s, "QC1"); + /* + * "Current thread" remains vague in the spec, so always return + * the first thread of the current process (gdb returns the + * first thread). + */ + cpu =3D get_first_cpu_in_process(s, gdb_get_cpu_process(s, s->= g_cpu)); + snprintf(buf, sizeof(buf), "QC%s", + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id= ))); + put_packet(s, buf); break; } else if (strcmp(p,"fThreadInfo") =3D=3D 0) { s->query_cpu =3D first_cpu; --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546878839846339.70228656335667; Mon, 7 Jan 2019 08:33:59 -0800 (PST) Received: from localhost ([127.0.0.1]:42840 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXqg-0006D7-Qn for importer@patchew.org; Mon, 07 Jan 2019 11:33:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoR-0004ud-Cg for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoO-0001s0-PO for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:38 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35429) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoM-0001l9-Ao for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:35 -0500 Received: by mail-wr1-x42d.google.com with SMTP id 96so1089424wrb.2 for ; Mon, 07 Jan 2019 08:31:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qzU0ympb5SfpvFVwfmO3i1qJ2YHOQU/0Au0uTSOXsmk=; b=ZxKIykM3oDCSc3v9JEWD1uVMHrSz57LQUvmJhxSS4xhYvphPjaGZ/dQFHeogMbv6cI wqk3G9J1iXtHYYJBEFX/numymw3k+8sKDfKmfHGRoCqQNFfbpA7WzzIZNr6Nr3aNDaUl 8CJ0eDS0oaCXhIrIj1vrHzOnHQSvFneUv5vN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qzU0ympb5SfpvFVwfmO3i1qJ2YHOQU/0Au0uTSOXsmk=; b=axnfwiY0eOc/BFuG6Z4iBF3EVr8srWin9ep0fXL52WPRYuel/0shUEYmvUGwviqsJA hnv3ON99FUG/+5WyIRF9tZ1MU4FxLa+7gvUsYPwHhqUO6SJUnMPuQFLPjRg9j5hVWc/7 LRDnlQPhPqSowR+9CvueXuYqdFsQpyYEs1eWOn5zfcnVNZlpcucUlUyCAgEh4I/YYZlX g4HG8yckzVBJRcW0AxYU1FCwMzDMbEayVAEk6XsDeSnSt+J+Q3oLgvNsRDKYFU2hvI00 GyIxeSEUlUfdryMgKzKXRm2gHmsDPtHSYGgxF9StJdycSLMhpNdShkgisLmYOYB8BHc+ /c/Q== X-Gm-Message-State: AJcUukelmnyEG8JBauE30M+UWkqUamb3Qbk7plc2hMJtIOL2Hr75BF0F bTjY2zRdvz65KGHW5nZrZCwXBkz/tl9a0A== X-Google-Smtp-Source: ALg8bN5xeBMjIKZuAebI/yvLDya39FrHkuAR5zKXZ3ICLys8T2d2ziCBQ5UAYuykwG0+SIMwOrFvnw== X-Received: by 2002:a5d:4acb:: with SMTP id y11mr50715502wrs.281.1546878692414; Mon, 07 Jan 2019 08:31:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:49 +0000 Message-Id: <20190107163117.16269-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PULL 09/37] gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Change the thread info related packets handling to support multiprocess extension. Add the CPUs class name in the extra info to help differentiate them in multiprocess mode. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-8-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 1ba7aa6a28a..f70b5a326fe 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1268,7 +1268,6 @@ static int gdb_handle_packet(GDBState *s, const char = *line_buf) CPUState *cpu; CPUClass *cc; const char *p; - uint32_t thread; uint32_t pid, tid; int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; @@ -1565,26 +1564,44 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) put_packet(s, buf); break; } else if (strcmp(p,"fThreadInfo") =3D=3D 0) { - s->query_cpu =3D first_cpu; + s->query_cpu =3D gdb_first_attached_cpu(s); goto report_cpuinfo; } else if (strcmp(p,"sThreadInfo") =3D=3D 0) { report_cpuinfo: if (s->query_cpu) { - snprintf(buf, sizeof(buf), "m%x", cpu_gdb_index(s->query_c= pu)); + snprintf(buf, sizeof(buf), "m%s", + gdb_fmt_thread_id(s, s->query_cpu, + thread_id, sizeof(thread_id))); put_packet(s, buf); - s->query_cpu =3D CPU_NEXT(s->query_cpu); + s->query_cpu =3D gdb_next_attached_cpu(s, s->query_cpu); } else put_packet(s, "l"); break; } else if (strncmp(p,"ThreadExtraInfo,", 16) =3D=3D 0) { - thread =3D strtoull(p+16, (char **)&p, 16); - cpu =3D find_cpu(thread); + if (read_thread_id(p + 16, &p, &pid, &tid) =3D=3D GDB_READ_THR= EAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu =3D gdb_get_cpu(s, pid, tid); if (cpu !=3D NULL) { cpu_synchronize_state(cpu); - /* memtohex() doubles the required space */ - len =3D snprintf((char *)mem_buf, sizeof(buf) / 2, - "CPU#%d [%s]", cpu->cpu_index, - cpu->halted ? "halted " : "running"); + + if (s->multiprocess && (s->process_num > 1)) { + /* Print the CPU model and name in multiprocess mode */ + ObjectClass *oc =3D object_get_class(OBJECT(cpu)); + const char *cpu_model =3D object_class_get_name(oc); + char *cpu_name =3D + object_get_canonical_path_component(OBJECT(cpu)); + len =3D snprintf((char *)mem_buf, sizeof(buf) / 2, + "%s %s [%s]", cpu_model, cpu_name, + cpu->halted ? "halted " : "running"); + g_free(cpu_name); + } else { + /* memtohex() doubles the required space */ + len =3D snprintf((char *)mem_buf, sizeof(buf) / 2, + "CPU#%d [%s]", cpu->cpu_index, + cpu->halted ? "halted " : "running"); + } trace_gdbstub_op_extra_info((char *)mem_buf); memtohex(buf, mem_buf, len); put_packet(s, buf); --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879275027565.0024722951979; Mon, 7 Jan 2019 08:41:15 -0800 (PST) Received: from localhost ([127.0.0.1]:44623 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXxh-0003pG-UX for importer@patchew.org; Mon, 07 Jan 2019 11:41:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46176) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoT-0004wm-Qy for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoR-0001vZ-Dx for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:41 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:54913) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoO-0001mk-AO for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:38 -0500 Received: by mail-wm1-x32b.google.com with SMTP id a62so1454877wmh.4 for ; Mon, 07 Jan 2019 08:31:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BttWZQoZnqRZyHxMFdEOuZXRafzydfBLYBSIF6UEwhQ=; b=gUxVjRAvqsshIV4scXZmbgLYNQ3xrxig566s+8HGyKLOcQ7sGGBKhWTfgVla176ANa nbfMqzDAw9MGOCR8dRRmA4b/b9x7odywgGUd5U9hd+rcbHH2GZRbOK40fu5CTt3Axvaf Qyi0dxjJ8vJt9x3fBN5PgSZFAMD0Y4aDT/Yd8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BttWZQoZnqRZyHxMFdEOuZXRafzydfBLYBSIF6UEwhQ=; b=I6A35eEYyg9u0NeDMWqwBIs7uOFcpaXN3K4pGx0GsSqkllK3QvfRTwbqXMir+sCWrS fNTrMPd+69ROyu+BX0g5xQdAqPbOzkaV4BsQ4h4ogvNRL+aJ40cUcS4ER+xtAl86bp0y RxGmVN599vTo/fHrdLv2/8qrmlZfqcVWQkCjxpFx5RZekY2LoTmGas6Wb6xd35b/IkVc tN5WVuqqoqoZG/fFd3q0CyBY1abC/vvcojLp1qkA3Cw8CNq3OyVpSvGmlAMO30gXhUwv TUslxHPNVNRe9UMWAffPf9JGuER5HiulGOEGXQyNL4XWQM9snMRREjS+owKp/fApEL2j Y3mg== X-Gm-Message-State: AJcUukepsQElBujV5fCAJqEcLB6aviWskS84WsV4GKTmuvwJU91MXIMz o6A2Zn50zASQcqrEk/FpJY9EPJALCxQwtg== X-Google-Smtp-Source: ALg8bN4JFJK7XWWaXa1MOsH5XmFZotIwenv492fruNeewry5H7uLM5f160zJtgT7sb0sh1U7ssQpDA== X-Received: by 2002:a1c:2314:: with SMTP id j20mr9039164wmj.142.1546878693530; Mon, 07 Jan 2019 08:31:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:50 +0000 Message-Id: <20190107163117.16269-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PULL 10/37] gdbstub: add multiprocess support to Xfer:features:read: X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Change the Xfer:features:read: packet handling to support the multiprocess extension. This packet is used to request the XML description of the CPU. In multiprocess mode, different descriptions can be sent for different processes. This function now takes the process to send the description for as a parameter, and use a buffer in the process structure to store the generated description. It takes the first CPU of the process to generate the description. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-9-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 52 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index f70b5a326fe..1f2b155490d 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -300,6 +300,8 @@ typedef struct GDBRegisterState { typedef struct GDBProcess { uint32_t pid; bool attached; + + char target_xml[1024]; } GDBProcess; =20 enum RSState { @@ -812,13 +814,14 @@ static CPUState *gdb_first_attached_cpu(const GDBStat= e *s) return cpu; } =20 -static const char *get_feature_xml(const char *p, const char **newp, - CPUClass *cc) +static const char *get_feature_xml(const GDBState *s, const char *p, + const char **newp, GDBProcess *process) { size_t len; int i; const char *name; - static char target_xml[1024]; + CPUState *cpu =3D get_first_cpu_in_process(s, process); + CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 len =3D 0; while (p[len] && p[len] !=3D ':') @@ -827,36 +830,37 @@ static const char *get_feature_xml(const char *p, con= st char **newp, =20 name =3D NULL; if (strncmp(p, "target.xml", len) =3D=3D 0) { - /* Generate the XML description for this CPU. */ - if (!target_xml[0]) { - GDBRegisterState *r; - CPUState *cpu =3D first_cpu; + char *buf =3D process->target_xml; + const size_t buf_sz =3D sizeof(process->target_xml); =20 - pstrcat(target_xml, sizeof(target_xml), + /* Generate the XML description for this CPU. */ + if (!buf[0]) { + GDBRegisterState *r; + + pstrcat(buf, buf_sz, "" "" ""); if (cc->gdb_arch_name) { gchar *arch =3D cc->gdb_arch_name(cpu); - pstrcat(target_xml, sizeof(target_xml), ""); - pstrcat(target_xml, sizeof(target_xml), arch); - pstrcat(target_xml, sizeof(target_xml), ""); + pstrcat(buf, buf_sz, ""); + pstrcat(buf, buf_sz, arch); + pstrcat(buf, buf_sz, ""); g_free(arch); } - pstrcat(target_xml, sizeof(target_xml), "gdb_core_xml_file); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "gdb_core_xml_file); + pstrcat(buf, buf_sz, "\"/>"); for (r =3D cpu->gdb_regs; r; r =3D r->next) { - pstrcat(target_xml, sizeof(target_xml), "xml); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "xml); + pstrcat(buf, buf_sz, "\"/>"); } - pstrcat(target_xml, sizeof(target_xml), ""); + pstrcat(buf, buf_sz, ""); } - return target_xml; + return buf; } if (cc->gdb_get_dynamic_xml) { - CPUState *cpu =3D first_cpu; char *xmlname =3D g_strndup(p, len); const char *xml =3D cc->gdb_get_dynamic_xml(cpu, xmlname); =20 @@ -1266,6 +1270,7 @@ out: static int gdb_handle_packet(GDBState *s, const char *line_buf) { CPUState *cpu; + GDBProcess *process; CPUClass *cc; const char *p; uint32_t pid, tid; @@ -1650,14 +1655,15 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) const char *xml; target_ulong total_len; =20 - cc =3D CPU_GET_CLASS(first_cpu); + process =3D gdb_get_cpu_process(s, s->g_cpu); + cc =3D CPU_GET_CLASS(s->g_cpu); if (cc->gdb_core_xml_file =3D=3D NULL) { goto unknown_command; } =20 gdb_has_xml =3D true; p +=3D 19; - xml =3D get_feature_xml(p, &p, cc); + xml =3D get_feature_xml(s, p, &p, process); if (!xml) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); @@ -2070,6 +2076,7 @@ static void create_default_process(GDBState *s) =20 process->pid =3D max_pid + 1; process->attached =3D false; + process->target_xml[0] =3D '\0'; } =20 #ifdef CONFIG_USER_ONLY @@ -2345,6 +2352,7 @@ static int find_cpu_clusters(Object *child, void *opa= que) assert(cluster->cluster_id !=3D UINT32_MAX); process->pid =3D cluster->cluster_id + 1; process->attached =3D false; + process->target_xml[0] =3D '\0'; =20 return 0; } --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sHoVLSA2tLPSJ2TzBtejORvIedQQDnk9Co9AD6jwdzM=; b=XO2QSEoT6GLREWLdlXNW2rAdid3xejgPgcgSesrkFgJ1hUopRl88WB6Ij9CLYgd/nG H6yzUVa+4aQ4aLW5ZnwrxKcwqlXGPT5FOhi9Wb4WNwZFelUarRhaJC25uwVYp/lEBr75 lVIWnjgy2a0J1XjUClMZeIAMWa0/3VQteIciA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sHoVLSA2tLPSJ2TzBtejORvIedQQDnk9Co9AD6jwdzM=; b=Xa5KkjlJGvF2BxmVSf8g3SaUurFWOieHYKPjBZdtmX8Xt3/BZ+seU6Bzc1ze0DVHL5 kudtcrvuCvlX7oqtHldGoVoR2GrSLeu0RBAsknz/QVGZwgBfSibAqnDGY8QyKetV8US7 8ePadLtHK5ylLGtyJvD0KltxzQVMlZL6GMRGm64/069Ng2s77RkxELXRdzitpqo/VDlX mfUwGlPGAZybAOiTH85uWgPauuBE4sFQtUoAG1IR0np11b7g64k75LvZXEaVqJFO/hkd 2mnuRg0gfbbB2K5ciYWn8LOZ/dmjAM92umo1EtjAzvsc88EtvvgyeDqGRkCuSkxKou0U cGnQ== X-Gm-Message-State: AJcUukcZA2Znh1Y9guBvTWrUbe5rOn9aCDGNQSbjXH1shcLYvER211QD U/qFcAfk6y4ngit5WeyQoPzzjLeJsuZV6w== X-Google-Smtp-Source: ALg8bN6hQtwuDEqmrYXLOOD2i6wfk7rf3GkKD7kAslN0eEOWtfyCnrNaEBMEFnwRz/b+QtB2L12eIw== X-Received: by 2002:adf:dec4:: with SMTP id i4mr50351454wrn.307.1546878694566; Mon, 07 Jan 2019 08:31:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:51 +0000 Message-Id: <20190107163117.16269-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 11/37] gdbstub: add multiprocess support to gdb_vm_state_change() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add support for multiprocess extension in gdb_vm_state_change() function. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-10-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 1f2b155490d..edee38b6136 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1724,6 +1724,7 @@ static void gdb_vm_state_change(void *opaque, int run= ning, RunState state) GDBState *s =3D gdbserver_state; CPUState *cpu =3D s->c_cpu; char buf[256]; + char thread_id[16]; const char *type; int ret; =20 @@ -1735,6 +1736,14 @@ static void gdb_vm_state_change(void *opaque, int ru= nning, RunState state) put_packet(s, s->syscall_buf); return; } + + if (cpu =3D=3D NULL) { + /* No process attached */ + return; + } + + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id)); + switch (state) { case RUN_STATE_DEBUG: if (cpu->watchpoint_hit) { @@ -1752,8 +1761,8 @@ static void gdb_vm_state_change(void *opaque, int run= ning, RunState state) trace_gdbstub_hit_watchpoint(type, cpu_gdb_index(cpu), (target_ulong)cpu->watchpoint_hit->vaddr); snprintf(buf, sizeof(buf), - "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", - GDB_SIGNAL_TRAP, cpu_gdb_index(cpu), type, + "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";", + GDB_SIGNAL_TRAP, thread_id, type, (target_ulong)cpu->watchpoint_hit->vaddr); cpu->watchpoint_hit =3D NULL; goto send_packet; @@ -1795,7 +1804,7 @@ static void gdb_vm_state_change(void *opaque, int run= ning, RunState state) break; } gdb_set_stop_cpu(cpu); - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, cpu_gdb_index(cpu= )); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", ret, thread_id); =20 send_packet: put_packet(s, buf); --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879215603651.6982922210168; Mon, 7 Jan 2019 08:40:15 -0800 (PST) Received: from localhost ([127.0.0.1]:44367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXwk-0002w3-FX for importer@patchew.org; Mon, 07 Jan 2019 11:40:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoa-00050f-P5 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00025Y-FR for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:37102) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoY-0001rP-5r for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wr1-x430.google.com with SMTP id s12so1079270wrt.4 for ; Mon, 07 Jan 2019 08:31:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1s/FyqcakpdikFoKdyxVjsd1dTTqxskhDVsUDUlN9cs=; b=XTFDdOfY8jNy+vmLzqcuzQcwwWQ8PyKPV+YzF2GK2NGmBLzTvp3ql12ei9XQcK8Dzr yVQrIDxp4vfeHoHwZz+j44UDz3YvQ+BfyU6xL3Jgs9phnGqQSVXS4pliPdYZtIxIHkds xCRpHX1ltMieKvWLcc9T6XIaY2ZJlXyAInNC8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1s/FyqcakpdikFoKdyxVjsd1dTTqxskhDVsUDUlN9cs=; b=cPuJ8yTaqdakWsEEyNWPL3QnAknmVNxuEKlXq2/UORG2fz5i1O8hhMRbvQAFaoeDml iEceWmMj+WtPW6tH93R+HnNdHF9K/Z2GqH2TlyFMjicee9MPywdIHlKRMeST+vA6AsyO RvPCdg5zs9T1llFDF1LIYvqoPGhsjTe/BmCV4P68zu49sTNiJT1E1GDPMaX9qc5so+wI E5Tk4uscEhY8ghtWhblzA4rdaRi3/vkhnwAAuGRKKFdjyshfVKwvbCA0WOvJg87L9HSr i7kbNXM8a35YXuF37AJEH1nCdhTN8fJN6EQ8JTclrvTkftdzyRCv7kCvB3bOw7HyMGv4 iirw== X-Gm-Message-State: AJcUukelO5DmEoiwiu4d2WkHv0pumGSRibxwRCQOpZg7ZVptTfA4dTpx alaYpDKtNM2KIewo1ghrld1t4+HnLiWlVQ== X-Google-Smtp-Source: ALg8bN5kn5su05T0KD99Z99ibUBsbmb4KU9O0H6EIJpOTPBWkaMG/qL77xE2ia9yf6vw9yAensXnPg== X-Received: by 2002:a5d:444a:: with SMTP id x10mr54560311wrr.162.1546878695723; Mon, 07 Jan 2019 08:31:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:52 +0000 Message-Id: <20190107163117.16269-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 12/37] gdbstub: add multiprocess support to 'D' packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel 'D' packets are used by GDB to detach from a process. In multiprocess mode, the PID to detach from is sent in the request. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-11-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index edee38b6136..2c7032f53ab 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1047,6 +1047,24 @@ static int gdb_breakpoint_remove(target_ulong addr, = target_ulong len, int type) } } =20 +static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); +#ifndef CONFIG_USER_ONLY + cpu_watchpoint_remove_all(cpu, BP_GDB); +#endif +} + +static void gdb_process_breakpoint_remove_all(const GDBState *s, GDBProces= s *p) +{ + CPUState *cpu =3D get_first_cpu_in_process(s, p); + + while (cpu) { + gdb_cpu_breakpoint_remove_all(cpu); + cpu =3D gdb_next_cpu_in_process(s, cpu); + } +} + static void gdb_breakpoint_remove_all(void) { CPUState *cpu; @@ -1057,10 +1075,7 @@ static void gdb_breakpoint_remove_all(void) } =20 CPU_FOREACH(cpu) { - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif + gdb_cpu_breakpoint_remove_all(cpu); } } =20 @@ -1339,9 +1354,40 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) exit(0); case 'D': /* Detach packet */ - gdb_breakpoint_remove_all(); - gdb_syscall_mode =3D GDB_SYS_DISABLED; - gdb_continue(s); + pid =3D 1; + + if (s->multiprocess) { + unsigned long lpid; + if (*p !=3D ';') { + put_packet(s, "E22"); + break; + } + + if (qemu_strtoul(p + 1, &p, 16, &lpid)) { + put_packet(s, "E22"); + break; + } + + pid =3D lpid; + } + + process =3D gdb_get_process(s, pid); + gdb_process_breakpoint_remove_all(s, process); + process->attached =3D false; + + if (pid =3D=3D gdb_get_cpu_pid(s, s->c_cpu)) { + s->c_cpu =3D gdb_first_attached_cpu(s); + } + + if (pid =3D=3D gdb_get_cpu_pid(s, s->g_cpu)) { + s->g_cpu =3D gdb_first_attached_cpu(s); + } + + if (s->c_cpu =3D=3D NULL) { + /* No more process attached */ + gdb_syscall_mode =3D GDB_SYS_DISABLED; + gdb_continue(s); + } put_packet(s, "OK"); break; case 's': --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880060836591.265490328607; Mon, 7 Jan 2019 08:54:20 -0800 (PST) Received: from localhost ([127.0.0.1]:47641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYAA-0005Ud-Ed for importer@patchew.org; Mon, 07 Jan 2019 11:54:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoZ-000505-VH for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-000255-An for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:47 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:33478) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoY-0001t1-0B for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wm1-x334.google.com with SMTP id r24so6495577wmh.0 for ; Mon, 07 Jan 2019 08:31:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KDpKGtvo/v3wqjD/NhUG0S90lilluzyMNggPM3w6PTs=; b=O0yhLXCpfh892sDPO47pQ9cP9fuTMBzPiT2MbhptqfIvcPOWCgvBTnzAMVn8Y2vFDn 5sl7A6O71koUM5iiTZtt3/dovyUHWqLrO9wA2kXKyyrl57oZFfFpJVPlK/WPyeswfc++ YXCOBK8qKBwc52BqI0LAGCOhFscHv41rROGo0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KDpKGtvo/v3wqjD/NhUG0S90lilluzyMNggPM3w6PTs=; b=URKx/cERAAZVsLetQdMR1GmKC+fwr9EOmwj9d3+F28GpeE940Q5cK3oqknzY0882MK nXOcs/t9m1RK1YNfuVGEHZwVqpMNJgA3xWEAdCElj30dSmKQydj4wZOxHN1FmJ7nBXEj U3K6tCUOOSYskC0mbXDy1XzosVqYW9orl0cakTCORmQ1VZEKK6zQ3zYuUkmtaTr/Kgov h/rNUkK6+V1lv23uPeextIXE0KhxaP97mQOEUb3GKAuvI/G97AfsWCr1+mZ4fdAec65U myDhyW/wLuh0eN4XL4WZbVU4cbfGji4hjX4m+nXS4kCIPUiLL1M1r834QoPTnEH4yJ1V fs4w== X-Gm-Message-State: AJcUukf3CeZ1OPyXtrfOsEKLyNtE98b1f52n4k9CljUSz2Rr38pfCFw6 l0qRd1qSMVx2vEJCNZoCSmGgU7qq5loHGA== X-Google-Smtp-Source: ALg8bN675XpeeRvv3Hrb0Bc6jclf5VX7/PQ8cG9YhBzdTk5L4twqcKzyZ442Qb2WVesPegh0aqKdLA== X-Received: by 2002:a1c:af08:: with SMTP id y8mr8575323wme.94.1546878696809; Mon, 07 Jan 2019 08:31:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:53 +0000 Message-Id: <20190107163117.16269-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 13/37] gdbstub: add support for extended mode packet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luc Michel Add support for the '!' extended mode packet. This is required for the multiprocess extension. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20181207090135.7651-12-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 2c7032f53ab..9b6b4d20a02 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1302,6 +1302,9 @@ static int gdb_handle_packet(GDBState *s, const char = *line_buf) p =3D line_buf; ch =3D *p++; switch(ch) { + case '!': + put_packet(s, "OK"); + break; case '?': /* TODO: Make this return the correct value for user-mode. */ snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879738123657.4868835687085; Mon, 7 Jan 2019 08:48:58 -0800 (PST) Received: from localhost ([127.0.0.1]:46366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY50-0001WV-9A for importer@patchew.org; Mon, 07 Jan 2019 11:48:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46290) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoZ-0004zo-Ce for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoX-000244-UW for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:47 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:50232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoX-0001ud-Mn for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:45 -0500 Received: by mail-wm1-x32e.google.com with SMTP id n190so1470222wmd.0 for ; Mon, 07 Jan 2019 08:31:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 14/37] gdbstub: add support for vAttach packets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add support for the vAttach packets. In multiprocess mode, GDB sends them to attach to additional processes. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20181207090135.7651-13-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 9b6b4d20a02..d80af955cea 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1348,6 +1348,41 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) goto unknown_command; } break; + } else if (strncmp(p, "Attach;", 7) =3D=3D 0) { + unsigned long pid; + + p +=3D 7; + + if (qemu_strtoul(p, &p, 16, &pid)) { + put_packet(s, "E22"); + break; + } + + process =3D gdb_get_process(s, pid); + + if (process =3D=3D NULL) { + put_packet(s, "E22"); + break; + } + + cpu =3D get_first_cpu_in_process(s, process); + + if (cpu =3D=3D NULL) { + /* Refuse to attach an empty process */ + put_packet(s, "E22"); + break; + } + + process->attached =3D true; + + s->g_cpu =3D cpu; + s->c_cpu =3D cpu; + + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id= ))); + + put_packet(s, buf); + break; } else { goto unknown_command; } --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879048791664.6805656208983; Mon, 7 Jan 2019 08:37:28 -0800 (PST) Received: from localhost ([127.0.0.1]:43635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXtx-0000UA-Gd for importer@patchew.org; Mon, 07 Jan 2019 11:37:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46350) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoa-00050L-8a for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00024s-BB for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:56147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoX-0001w9-V9 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wm1-x331.google.com with SMTP id y139so1436454wmc.5 for ; Mon, 07 Jan 2019 08:31:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u312PotEuQpWHq94BwRphO7NoGBKFDJhyMDW9Wc9sAM=; b=eGZVl4DTVdUWVa/yZ6b4cpf1yKwJE5zq2lfOTw5TtzjAnHWSu5lxWC/RqJbmVuLTE2 DcSLAdAnUKGGBnR41xEuA0rXYJIS8nYSSi8IEMl7UgSuHZtVxnaXc+jFKF7M/Y3wbeso iRTQHuPpi+gHuaFbCjAY1iuMCRFr1OVelxoDE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u312PotEuQpWHq94BwRphO7NoGBKFDJhyMDW9Wc9sAM=; b=mc+lPA1frYxpreXM3iDbblL+M+2mdmWsTSdpkuwjm36UAnaN3vBRmDJsuUfMy7jYbJ QAwK0iCyB0bfs5RCChP4PjfsbcRN26UcPg5CTmtRHZkF8JlK9wCuwJDawqg7SPNMnKtW I7/RKbowklqLD4exHnXmL26e3YSYnfrGoAu+UAdiNm20eh4AZkdWfo3iBUDV/tJDNBT/ +iB7cVo0/sWGT+crpqtBlqND05JseiQjca1J5VWvcO4UkDfzPGv3eVZi/IoCiUa10vmr qhJtufpYVCfWnVQmu/fHQOVTI+wGq4zUq/HrtYvhcf7TlG8hyOteZ9dDRbDcz47/gwrZ 6JmA== X-Gm-Message-State: AJcUukcoAC18udNy71+NJ46IA8NDNO+DljebG5PIysnwOirZbkNoC6Pz 2UVRwyE+Mf32ZKS7OpjP+vC618QqrIoT7g== X-Google-Smtp-Source: ALg8bN4YeRRUVMr4I6IRmvlkx3OTuNSI78f2da3GkBuUWQXkWyyOBKi5NhXMzSgsV2Ot5sN9WNpjbw== X-Received: by 2002:a1c:2408:: with SMTP id k8mr8833662wmk.110.1546878698989; Mon, 07 Jan 2019 08:31:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:55 +0000 Message-Id: <20190107163117.16269-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 Subject: [Qemu-devel] [PULL 15/37] gdbstub: processes initialization on new peer connection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel When a new connection is established, we set the first process to be attached, and the others detached. The first CPU of the first process is selected as the current CPU. Signed-off-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20181207090135.7651-14-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index d80af955cea..432e7d2f7da 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2267,9 +2267,10 @@ static bool gdb_accept(void) } =20 s =3D g_malloc0(sizeof(GDBState)); - s->c_cpu =3D first_cpu; - s->g_cpu =3D first_cpu; create_default_process(s); + s->processes[0].attached =3D true; + s->c_cpu =3D gdb_first_attached_cpu(s); + s->g_cpu =3D s->c_cpu; s->fd =3D fd; gdb_has_xml =3D false; =20 @@ -2355,8 +2356,19 @@ static void gdb_chr_receive(void *opaque, const uint= 8_t *buf, int size) =20 static void gdb_chr_event(void *opaque, int event) { + int i; + GDBState *s =3D (GDBState *) opaque; + switch (event) { case CHR_EVENT_OPENED: + /* Start with first process attached, others detached */ + for (i =3D 0; i < s->process_num; i++) { + s->processes[i].attached =3D !i; + } + + s->c_cpu =3D gdb_first_attached_cpu(s); + s->g_cpu =3D s->c_cpu; + vm_stop(RUN_STATE_PAUSED); gdb_has_xml =3D false; break; @@ -2546,15 +2558,13 @@ int gdbserver_start(const char *device) memset(s, 0, sizeof(GDBState)); s->mon_chr =3D mon_chr; } - s->c_cpu =3D first_cpu; - s->g_cpu =3D first_cpu; =20 create_processes(s); =20 if (chr) { qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_rec= eive, - gdb_chr_event, NULL, NULL, NULL, true); + gdb_chr_event, NULL, s, NULL, true); } s->state =3D chr ? RS_IDLE : RS_INACTIVE; s->mon_chr =3D mon_chr; --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 154687940343821.72093120062607; Mon, 7 Jan 2019 08:43:23 -0800 (PST) Received: from localhost ([127.0.0.1]:45104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXzc-0005Wd-Dz for importer@patchew.org; Mon, 07 Jan 2019 11:43:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46437) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXod-00053O-4E for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00026T-Ph for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:52648) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoY-0001xm-Bq for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wm1-x335.google.com with SMTP id m1so1470079wml.2 for ; Mon, 07 Jan 2019 08:31:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DggtY6HHQ9duEuWdFgn35E494xOLm+nkWBc8Po6gMWI=; b=DcyYB1mk5591/ecgG1AtOgceH6cqAVlsj1nMSeKLQxVCdqpZiUUCfdNnP+8WY/6YyH v3a4GYpHLru6EMGVZZHkKXKPzEdl+ow/vTvfynsOUGUryEjlT1AA8VU1cWV6MTnUnC5Z oIsMISeYlOkF4Nc1iWxrZN4dMh3bDmKkxVpM8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DggtY6HHQ9duEuWdFgn35E494xOLm+nkWBc8Po6gMWI=; b=b5cyF9jTtHMAngAsKp18MGoTJ1mEDh3Mu8HnavlYzNN17xzzVvCS/iDVQKRVIIdUr4 kygETTbJtDyzhLgyhRuUYfXea4rT7kOJKpVcxp2yiShfFLBkb+EMo7G9mY+uj3jXBg9p dSd3cTQIbYZU6l/2qsxuTvHnlA0A0cApzPL2s6ti3eRCwMMzqHGlE7wDo9rdCw1XXcMI tJrS6lGdTOy0JbT2Ifl4OKdZKdNwZFW/gnIPf36slL5Mx/jJpoGkGmLOZmACMkEv92Qa RKIqyB9tE0wbWPyPTbsIpDcJ2btvWvOJP+cUUtIPLQZi9BWVnoPwZq3syUSYxU5CA0SW dWSA== X-Gm-Message-State: AJcUukfdqDBS0FiyMEkRnDrZe2skkB/aHdcLGaqQLIcsheRsmRmfF2kn r01J8Ie+pxjtWcsg/0PZPqkyLpflAEjnmw== X-Google-Smtp-Source: ALg8bN5NV5OoXcrdXu3TlLb8sVlbSsAFwP7ED8vtJU2rrrWWHG/MipK4btyr0aGf8IZ0Mtwg8bTLFw== X-Received: by 2002:a1c:1b8d:: with SMTP id b135mr9298964wmb.115.1546878700101; Mon, 07 Jan 2019 08:31:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:56 +0000 Message-Id: <20190107163117.16269-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 16/37] gdbstub: gdb_set_stop_cpu: ignore request when process is not attached X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luc Michel When gdb_set_stop_cpu() is called with a CPU associated to a process currently not attached by the GDB client, return without modifying the stop CPU. Otherwise, GDB gets confused if it receives packets with a thread-id it does not know about. Signed-off-by: Luc Michel Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-15-luc.michel@greensocs.com [PMM: fix checkpatch comment style nit] Signed-off-by: Peter Maydell --- gdbstub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 432e7d2f7da..1517563abe1 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1798,6 +1798,16 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) =20 void gdb_set_stop_cpu(CPUState *cpu) { + GDBProcess *p =3D gdb_get_cpu_process(gdbserver_state, cpu); + + if (!p->attached) { + /* + * Having a stop CPU corresponding to a process that is not attach= ed + * confuses GDB. So we ignore the request. + */ + return; + } + gdbserver_state->c_cpu =3D cpu; gdbserver_state->g_cpu =3D cpu; } --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879900698330.7806973157104; Mon, 7 Jan 2019 08:51:40 -0800 (PST) Received: from localhost ([127.0.0.1]:47007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY7n-0003bZ-Mr for importer@patchew.org; Mon, 07 Jan 2019 11:51:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46361) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoa-00050W-GZ for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00024n-AS for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:36226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoX-0001yU-Tt for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wm1-x335.google.com with SMTP id p6so1528405wmc.1 for ; Mon, 07 Jan 2019 08:31:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.40 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dV9FgMcSij0NL5Y8EajzqIS8bpID78HptYmcxeEKzgY=; b=Fc/9bGyA1EnkHoUPtBmlaaaj/tQjxx+8cyHjp8wEnNl7/YuabRT8GRmH1uwuDXvrwm PxRB1O2zhyMzofw9mOHp775aztjf1jZGzvoFtVWdBmnKarZKetJS5hSSWqsgAtGgjgFT 7cpoEEu2wBC+M9C+GgkVajFKGoiLaiqzFNNBs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dV9FgMcSij0NL5Y8EajzqIS8bpID78HptYmcxeEKzgY=; b=UOf859doTgc8348X8Z2tiMs+LieM9QuMJSRmck35HUYsPyKTr0ySnA7E1t9I5Y1SvQ 9On5P/Puxz35mt6o/6pC1wLCVN4kgkWm734fdowaRzy1M0jclSZvYPo1IGshrwndyZ+B xdP/BVIYQomZzKuzI9k8w4HA5uce9/SOlNuLP/qd4JZscIxaSeWJgZIQ/QINuVP/OQi8 kk0hpGbUaVyLtI70t37QHHG4Li5GBMVgh2QBoMgEiAS9PdUSY/wVC4Y+/MokEcLyiXD/ r9v0orzfSln85gELCsPTQw1M5VMtKW4L4pVCeqFYN+YluAbC2av4yOzzeA0Os3WyvVMA 9wRg== X-Gm-Message-State: AJcUukdn8cZ6wbX46WSTVsHuw0T6Wp3AMBZGWsyLJtoys0se+2lSbSxZ RleJSPqcuojpbOGQILbwpGe+rYmSYjdtQA== X-Google-Smtp-Source: ALg8bN7FzZXwKzuOpCbIoZQxAGe5IGuFz6S0m/HDgIgOAORcTvPiOWzTLge28IWLKRzwwRc+A9Xlpg== X-Received: by 2002:a1c:d14d:: with SMTP id i74mr8698501wmg.100.1546878701268; Mon, 07 Jan 2019 08:31:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:57 +0000 Message-Id: <20190107163117.16269-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 17/37] gdbstub: add multiprocess extension support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Add multiprocess extension support by enabling multiprocess mode when the peer requests it, and by replying that we actually support it in the qSupported reply packet. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20181207090135.7651-16-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 1517563abe1..bfc7afb5096 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1732,6 +1732,12 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) if (cc->gdb_core_xml_file !=3D NULL) { pstrcat(buf, sizeof(buf), ";qXfer:features:read+"); } + + if (strstr(p, "multiprocess+")) { + s->multiprocess =3D true; + } + pstrcat(buf, sizeof(buf), ";multiprocess+"); + put_packet(s, buf); break; } --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879624576886.8561118524176; Mon, 7 Jan 2019 08:47:04 -0800 (PST) Received: from localhost ([127.0.0.1]:45981 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY3L-0000KR-JK for importer@patchew.org; Mon, 07 Jan 2019 11:47:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoa-00050c-Mk for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00024x-BH for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:38980) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoX-0001zh-Ta for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wr1-x436.google.com with SMTP id t27so1065564wra.6 for ; Mon, 07 Jan 2019 08:31:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1Nj4Qd8AQBRrQsNtstFrCaiBGY7evGJTMBUrYASOjQY=; b=Ql5qOs4lojalis6L7DCbJA0TKdb8Ur9pgqq4fABRylRsIRMKe8mNUcXWdzn15PhXsu 9CTOVhlLkIKQh0bq8ESKb0Cy3JGs+BYtDB6DnFN0HL3CQyul6RYia6d6dg/q/yW5i/MQ nuoekyqyhVayaIDffYZM5GVeuJVByVAYhs+NY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Nj4Qd8AQBRrQsNtstFrCaiBGY7evGJTMBUrYASOjQY=; b=LtQlSAD1udoeM/q8HhwW0QYcvkOp8+bWWhNF9+ejgdEic89ltzkBkOXBx8+A1CiRdQ /YYE7J+VN0mpErTp3x+Pjh004n8Kf8G87v2H0QnmPbgfhZAWhIz31DLFZVdgr71XVfHc MLs2qjcK+Hih4+vyaGbWzkA1U8tQgKYHbwa2xWWi9RBarp9yhjCsosmzsXrrptpUFc+W 5ezPy7GieiZHAs1JrV2zursjfYTvDhyYIKmhA3yb1Tx2/ewUnEtb+e8+uASiHx10tkmM zTGY3QOabThQjvVgLnC1EbP95JxfoqxOsce/3CdO3GtrzcMUCVqctUigIIFYOiStDsnz XfBQ== X-Gm-Message-State: AJcUuketUT+S+svM+DLUG1+tpyBaOQRDF90Mck/cEaC8NBOr65MhLZBl JiJRAPDbjiRtcYWmmwH5HC5ZCX6TM8VkmQ== X-Google-Smtp-Source: ALg8bN4ZxRTUnDKsD/3QphYshDU0GdNnUswx+LeNrH8M50N96bMULu0pvTGynBgZHGOFGkD6V5dPfg== X-Received: by 2002:a5d:6244:: with SMTP id m4mr41723574wrv.314.1546878702505; Mon, 07 Jan 2019 08:31:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:58 +0000 Message-Id: <20190107163117.16269-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 18/37] arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Luc Michel Create two separate CPU clusters for APUs and RPUs. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20181207090135.7651-17-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 3 +++ hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 98f925ab84a..591515c7600 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -31,6 +31,7 @@ #include "hw/display/xlnx_dp.h" #include "hw/intc/xlnx-zynqmp-ipi.h" #include "hw/timer/xlnx-zynqmp-rtc.h" +#include "hw/cpu/cluster.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -77,6 +78,8 @@ typedef struct XlnxZynqMPState { DeviceState parent_obj; =20 /*< public >*/ + CPUClusterState apu_cluster; + CPUClusterState rpu_cluster; ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c1950403505..c67ac2e64ac 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -178,12 +178,19 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s= , const char *boot_cpu, int i; int num_rpus =3D MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_= NUM_RPU_CPUS); =20 + object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, + sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); + for (i =3D 0; i < num_rpus; i++) { char *name; =20 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), "cortex-r5f-" TYPE_ARM_CPU); - object_property_add_child(OBJECT(s), "rpu-cpu[*]", + object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), &error_abort); =20 name =3D object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]= )); @@ -213,10 +220,16 @@ static void xlnx_zynqmp_init(Object *obj) int i; int num_apus =3D MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); =20 + object_initialize_child(obj, "apu-cluster", &s->apu_cluster, + sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + for (i =3D 0; i < num_apus; i++) { - object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i], - sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, = NULL); + object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", + &s->apu_cpu[i], sizeof(s->apu_cpu[i]), + "cortex-a53-" TYPE_ARM_CPU, &error_abort, + NULL); } =20 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), @@ -333,6 +346,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); =20 + qdev_init_nofail(DEVICE(&s->apu_cluster)); + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i =3D 0; i < num_apus; i++) { char *name; --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880194455587.5090335296137; Mon, 7 Jan 2019 08:56:34 -0800 (PST) Received: from localhost ([127.0.0.1]:48264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYCX-0007aA-BK for importer@patchew.org; Mon, 07 Jan 2019 11:56:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXob-000511-43 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00024Q-5p for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:47 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:41386) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoX-000216-S4 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wr1-x435.google.com with SMTP id x10so1052510wrs.8 for ; Mon, 07 Jan 2019 08:31:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AAj13xPTkFQmjBETJwyujJHJPgr2Q5uzYWYEkzn2Pyc=; b=jJXiIS8tZ7cbF+GhDWqMBzFgxgKPqEvEknDLNLsC0hsK1pBM0KcpG16qdQ2TwpvzKD SxJW0fkM7kAgvOqnLiUCo9iWwkaBMgbdWfRu2m32suVTdUITGvMsZFnEsJ4qxQFfKZ+o vxlqVv1xbwwLoLuKRl1yDSouAawJ2TNpwaJVs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AAj13xPTkFQmjBETJwyujJHJPgr2Q5uzYWYEkzn2Pyc=; b=ITX9oJScujYpEFf6CmHYySINgrOo54j24srH07kbokhF6zPlxa2jpdQmL0o2yK4hR/ V8AKKxx3mi7796UTPYbiNpUt8N4uMXE9ei9upIHReY64u+Z4qaip/wcQnBoYm7Mrs6tW EBpmY7yOvOsJzRxAtvuq5/FsTo0Y80qOH739CP3Zh8lMydi4N9IkZKJjo0hJi8JnxM68 2GNPfsO5EB3SxCMop0RUlV7dE2dIttH3rWZaq2xCe3KjzI3Yf1v0+aVl+u10vcLUkg0S 9BnNepdlWepXi4EMWfdxAMcrQ/LWF8bqlfEoezjd+0hvXPuvKwe9xEiOMsOcWlU2T3LS CZlw== X-Gm-Message-State: AJcUukfUZFZfFKn+psGoJM8GDf5gkCzHn7eu2pJ0bhgw3IZ4t9m+T9xl wDQX/45I1jScxoBRGZcjAtbupPqW475uwQ== X-Google-Smtp-Source: ALg8bN6J+euivRLiKNSJof3KmVch85tWYxu9Z5IvNY7WPo3ZtuK/RD/ILjTsYJLtzxDp0RrC9vthjw== X-Received: by 2002:adf:9484:: with SMTP id 4mr48986478wrr.98.1546878703644; Mon, 07 Jan 2019 08:31:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:30:59 +0000 Message-Id: <20190107163117.16269-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 Subject: [Qemu-devel] [PULL 19/37] Revert "armv7m: Guard against no -kernel argument" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stefan Hajnoczi This reverts commit 01fd41ab3fb69971c24a69ed49cde96086d81278. The generic loader device (-device loader,file=3Dkernel.bin) can be used to load a kernel instead of the -kernel option. Some boards have flash memory (pflash) that is set via the -pflash or -drive options. Allow starting QEMU without the -kernel option to accommodate these scenarios. Suggested-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103144124.18917-1-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/armv7m.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 4bf9131b81e..f4446528307 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -285,11 +285,6 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kerne= l_filename, int mem_size) big_endian =3D 0; #endif =20 - if (!kernel_filename && !qtest_enabled()) { - error_report("Guest image must be specified (using -kernel)"); - exit(1); - } - if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { asidx =3D ARMASIdx_S; } else { --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154688033807648.42124419802917; Mon, 7 Jan 2019 08:58:58 -0800 (PST) Received: from localhost ([127.0.0.1]:48901 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYEr-0001D6-33 for importer@patchew.org; Mon, 07 Jan 2019 11:58:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46386) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXob-00050x-2k for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoY-00026r-Se for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:33875) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoY-00022a-DR for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:46 -0500 Received: by mail-wm1-x341.google.com with SMTP id y185so6500503wmd.1 for ; Mon, 07 Jan 2019 08:31:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3EDWJiaFbSIgmkYxpZHI/vzgm7ATTJ6Z/riMYlEZu88=; b=HlQnMkIW4jtHclKqlUfm8KoVdVLKQ9iGRoBbO6k1IAj9ed18HMRf92sj1YF1VrHHAM /HdrsYM4kkwZkBlxc1vnQIUlO/B3c+6mvHANVf96fW6OMO9qtpDI4L8BtpbW2Hbipq7y xaxYLQqtHkQQ4kcvweDZ2vrK/42kQLhWxt/7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3EDWJiaFbSIgmkYxpZHI/vzgm7ATTJ6Z/riMYlEZu88=; b=e22BPNkLq2AaAY6enlY5y6KrqrzRFTzOmC0Xt9dL+a0BAnrqwi5wstY3HikzZ55ofu M5QtuMgnC4QgA6H0inb0PfkACUD3bRYpUWkGMyjTH5kaqShCM/WvbcfBVY1y/BIiYgSJ Mv8JzMrjW3WldeP8SaxGyMGSVmcCpDNwbi1AmZFU3V6Kmi3mMZ+juFd+RxNWxt9UIFLU /ARwyXaoz4v+PpXP8WBgiLt2BCKFCAPpVZN8/0fjPN2ZGtOwPDr5P/3oov8lNhePB5dB 5CbfDHR7BIQtSURGxXWlbOXP0w2AP9RArT5Ty1uVbGiFu9Wu8kHSoxLJiLSW1BNIakPL Gdow== X-Gm-Message-State: AJcUukdfxjzgUmVwk/s9Bgckk75OSblZuVFLe0qJc7tAZvZ/7AaM0G6Z wjxr5GZPbcFSMFDQePn8/G8u27X4DFqS/Q== X-Google-Smtp-Source: ALg8bN76Rzfw+SlNYPh/GjfaqCJy8B3MqYON+09tx/xyelQj9CchKra8MafJv/Vgi8lzdahb6giBIA== X-Received: by 2002:a1c:8791:: with SMTP id j139mr8891158wmd.86.1546878704691; Mon, 07 Jan 2019 08:31:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:00 +0000 Message-Id: <20190107163117.16269-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 20/37] hw/arm: versal: Plug memory leaks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: "Edgar E. Iglesias" Plug a couple of "board creation time" memory leaks. Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board") Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index c6feeac532f..f95fde2309b 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -130,6 +130,7 @@ static void fdt_add_gic_nodes(VersalVirt *s) 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); + g_free(nodename); } =20 static void fdt_add_timer_nodes(VersalVirt *s) @@ -364,6 +365,7 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); + g_free(name); } =20 for (i =3D 0; i < NUM_VIRTIO_TRANSPORT; i++) { --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880515053477.16241803497087; Mon, 7 Jan 2019 09:01:55 -0800 (PST) Received: from localhost ([127.0.0.1]:49576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYHg-0003UL-Qy for importer@patchew.org; Mon, 07 Jan 2019 12:01:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXod-00053S-Ay for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoZ-00029E-Oz for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoZ-000266-Fz for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:47 -0500 Received: by mail-wr1-x42a.google.com with SMTP id x10so1052628wrs.8 for ; Mon, 07 Jan 2019 08:31:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K6gRcPHJotk1qJugmg0T5V5Ijg7F2u3bPPHU1sURI7A=; b=fk/BVTlDB8DYxk9gC2a1yohJoLwzC15GUiqbWPeUg/6VIWEeF9VmdbNz6bNNq/HNMm iJHuHowp8fxehaJ99mVxhJDkDdEa/0FUWcSwxiZBnAcLU6wagBL42ZaZVifssug/h+jV nGU5l2+8rFzy1yZBXCVdvaZ186qW7Xvn3xg8c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K6gRcPHJotk1qJugmg0T5V5Ijg7F2u3bPPHU1sURI7A=; b=synWuAiIdZ9HLNXbg/f6s7/dOhu0r6cxBR8v74+anjH4s+Zcb0i59vp8HoN6dT/+Kr gwE6gjvO3UsXWCqm+I9IWXklf9W6xJM9aIwpZwenTFr352rfXUOzjQU898zFweFvZhKH nIELBnm1ryhGMX8hVJ3MAksX9LwL7UDUgskGPiGnhRo3w2AOBl/VmP5XY1KKO/1uGOGr xItTRjPWTKtHrnRZyNkGHLmLHic3zQOWF7yuwcUsNaKHO+QfpiXK//Kh3V3/31ZlBaxH pclA7gaKU1y8zTXqOLEaIuNAkE9o4w+uq3QXOrElnIDGLIDwWRKBEHIJPftSTtLryL0i Ru9w== X-Gm-Message-State: AJcUukfWsdyHC0hLRWr5rD8bKDTodkJYjoJ5MhLFEkd65ruYysm3fmiB 3Qzg679gRzm1XnN/hzKchyb8HauMxhii6g== X-Google-Smtp-Source: ALg8bN6H62vK/iP+9lK3PMXkCswLdSPvrhvf6XCejMMs9MKsuTCFz/u4nUGjbYdQJvir0+OuoO8RuQ== X-Received: by 2002:adf:8464:: with SMTP id 91mr55484156wrf.251.1546878705867; Mon, 07 Jan 2019 08:31:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:01 +0000 Message-Id: <20190107163117.16269-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 21/37] MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Thomas Huth Some of the files in hw/input/, hw/misc/ and hw/timer/ are only used by one of the ARM machines, so we can assign these files to the corresponding boards. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1546433583-18397-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell --- MAINTAINERS | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 471161742de..0bfd95a4ef7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -515,6 +515,7 @@ F: hw/intc/arm* F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c +F: hw/misc/arm_l2x0.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -587,6 +588,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/integratorcp.c F: hw/misc/arm_integrator_debug.c +F: include/hw/misc/arm_integrator_debug.h =20 MCIMX6UL EVK / i.MX6ul M: Peter Maydell @@ -606,7 +608,9 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/mcimx7d-sabre.c F: hw/arm/fsl-imx7.c +F: hw/misc/imx7_*.c F: include/hw/arm/fsl-imx7.h +F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h =20 @@ -640,6 +644,10 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/nseries.c +F: hw/input/lm832x.c +F: hw/input/tsc2005.c +F: hw/misc/cbus.c +F: hw/timer/twl92230.c =20 Palm M: Andrzej Zaborowski @@ -647,6 +655,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/palm.c +F: hw/input/tsc210x.c =20 Raspberry Pi M: Peter Maydell @@ -683,6 +692,7 @@ F: hw/display/tc6393xb.c F: hw/gpio/max7310.c F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c +F: hw/misc/max111x.c F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h =20 @@ -693,10 +703,10 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/sabrelite.c F: hw/arm/fsl-imx6.c -F: hw/misc/imx6_src.c +F: hw/misc/imx6_*.c F: hw/ssi/imx_spi.c F: include/hw/arm/fsl-imx6.h -F: include/hw/misc/imx6_src.h +F: include/hw/misc/imx6_*.h F: include/hw/ssi/imx_spi.h =20 Sharp SL-5500 (Collie) PDA @@ -807,7 +817,9 @@ R: Joel Stanley L: qemu-arm@nongnu.org S: Maintained F: hw/*/*aspeed* +F: hw/misc/pca9552.c F: include/hw/*/*aspeed* +F: include/hw/misc/pca9552*.h F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h =20 --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879795279337.2929153895752; Mon, 7 Jan 2019 08:49:55 -0800 (PST) Received: from localhost ([127.0.0.1]:46580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY66-0002Hk-5x for importer@patchew.org; Mon, 07 Jan 2019 11:49:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXod-00053K-25 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoa-0002Bg-Pl for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:50 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38747) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoa-00029M-Ep for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:48 -0500 Received: by mail-wr1-x42c.google.com with SMTP id v13so1074532wrw.5 for ; Mon, 07 Jan 2019 08:31:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TOtzORjw7YC4m6L0fj5Wo5LEgSmQNqLx7l1bWVlv6Zs=; b=OBoSISdh8OdMe08k6MDfolscA1raoDNnsZgRiIdvyfMczU2GSKjd6OaOZgu6LgVhmg uYU94Yv/o6gber87zgGPvhY2+c3Qdgd74RZ1yEDdza3kIyEar7zBbrcRsTdM4KirNgu7 NPgDd/saCOJ8UatmBJQNhZejH+WjzmcirMCLM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TOtzORjw7YC4m6L0fj5Wo5LEgSmQNqLx7l1bWVlv6Zs=; b=DJgL0qNOo4X3jvMg7z/JcCgw5UmmLY8sYSYor62IDRLuPA9B0vSrwMUTmijH1scWdw 9sFk/q5WH6oiKZRCE09RB+yMl+nEej1fg1A6BpCavnPUfD8J/hAnqbzAObPLB18X+U+J uT8yXWYWEwTKXv5AMNFr4i8lWehlYF+M2c7EuEP52LXeDUYK8aOU76TLaBDzoBiJhYlv Ra9ddLcUF/tAFjE4DtBx7hgcK7M5WnH+f4+U2EA0m8KKItGhKYBowQQQXCHT4YSBoqvn ymuNqXrQ159HUlaERvrJT1OLoA/MhqmKzi9qEAHS9CsmURdA5MLhbIGD45jPk9+5LJcW SXhw== X-Gm-Message-State: AJcUukfCWTcDXQK0DOd3LLyPyCBHxHyBWztcKj9c1l7vw5RAgWW5pXfX hTLPELS8z8zHpm8WgzvRjjc0wala0kKRuw== X-Google-Smtp-Source: ALg8bN6fTma+6kjVuvE3UxzDKJNFhtqRlAOY8ESIyV42ISZvmDIIVA0JnWkET6fwqaBoxPWi86/d6A== X-Received: by 2002:a5d:6450:: with SMTP id d16mr52215154wrw.64.1546878707068; Mon, 07 Jan 2019 08:31:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:02 +0000 Message-Id: <20190107163117.16269-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 22/37] cpus.c: Fix race condition in cpu_stop_current() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We use cpu_stop_current() to ensure the current CPU has stopped from places like qemu_system_reset_request(). Unfortunately its current implementation has a race. It calls qemu_cpu_stop(), which sets cpu->stopped to true even though the CPU hasn't actually stopped yet. The main thread will look at the flags set by qemu_system_reset_request() and call pause_all_vcpus(). pause_all_vcpus() waits for every cpu to have cpu->stopped true, so it can continue (and we will start the system reset operation) before the vcpu thread has got back to its top level loop. Instead, just set cpu->stop and call cpu_exit(). This will cause the vcpu to exit back to the top level loop, and there (as part of the wait_io_event code) it will call qemu_cpu_stop(). This fixes bugs where the reset request appeared to be ignored or the CPU misbehaved because the reset operation started to change vcpu state while the vcpu thread was still using it. Signed-off-by: Peter Maydell Reviewed-by: Emilio G. Cota Tested-by: Jaap Crezee Message-id: 20181207155911.12710-1-peter.maydell@linaro.org --- cpus.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpus.c b/cpus.c index 0ddeeefc14f..b09b7027126 100644 --- a/cpus.c +++ b/cpus.c @@ -2100,7 +2100,8 @@ void qemu_init_vcpu(CPUState *cpu) void cpu_stop_current(void) { if (current_cpu) { - qemu_cpu_stop(current_cpu, true); + current_cpu->stop =3D true; + cpu_exit(current_cpu); } } =20 --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879571476566.7272622941927; Mon, 7 Jan 2019 08:46:11 -0800 (PST) Received: from localhost ([127.0.0.1]:45789 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY2U-00086T-E1 for importer@patchew.org; Mon, 07 Jan 2019 11:46:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoi-00056A-97 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXof-0002HQ-5I for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:54 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:35433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXod-0002C4-6S for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:52 -0500 Received: by mail-wr1-x42f.google.com with SMTP id 96so1090368wrb.2 for ; Mon, 07 Jan 2019 08:31:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=soNeqI2oAtZuvZ9bY0TG6Kpl0kFjvNdpLzIG+q3lAxk=; b=G95b6NKcfR9FUZESNlfnQ6RcOJU7jcYebIe/tQZMqk/JOYo36MjhP7uJP2WBBW09/3 6GMDCHKTXeOE4k0geccRuf+zrwZg7AqptawiVLKguWazbJrru4+cATEG1kuNJVEXXVPB QDY+7NbiMmGWQSOt0l6A3zSKXRCZl8MD2ll10= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=soNeqI2oAtZuvZ9bY0TG6Kpl0kFjvNdpLzIG+q3lAxk=; b=ZUrPBuIAJvSpA1GFlWAQ1dvFZ6LTsYPCrE37X4bTGTH0d5yx8ZeCRCT9RWRJcvU/4J hevnKYUISSJyYLuFYxV6uPBVDFHHgvVgO6REx1iI6sLe6O+YI1Rt/t7qiHm0IFAujiDk /RA//PrJODmEkfQBS0hcZ3tWn6B1BU3WNs1rhTD23aakFoI72DelvAWnbVRDSvN+z27S g8DQR/NrZewIrUiH9K03M/HsKueZuWdb9MnQDrzOP0pQFAVSBg6D8RjISCJ/WrnaIoeD 2Oa8EfNixGj+nOtdJp1cyeYYfflMx2cZnR17hP0dWXpiCSDWyOBl9YoJWXg9C0L1WfY9 755g== X-Gm-Message-State: AJcUukfwAxyonBXFBxykQeBmkmp4jGTbWbCkvPDodoo+LxxQrVjGqNSK niqxa83dort449p+Kce/ZYIoqXnmMC0vbA== X-Google-Smtp-Source: ALg8bN4s2Yn2HN+0aVnl8o96yZfNyOEisDQkR85ABqdy5CCQjyG8C3SybPhlESiLqer/XGvUi7O+yA== X-Received: by 2002:adf:e846:: with SMTP id d6mr54581666wrn.72.1546878708311; Mon, 07 Jan 2019 08:31:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:03 +0000 Message-Id: <20190107163117.16269-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 23/37] hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply defi= ne the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite Tested-by: Charlie Smurthwaite Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190104142921.878-1-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-a10.h | 1 + hw/arm/allwinner-a10.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index efb8fc81236..389e128d0fc 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -35,6 +35,7 @@ typedef struct AwA10State { AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; + MemoryRegion sram_a; } AwA10State; =20 #define ALLWINNER_H_ diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875cdb5e..df0d079ad0a 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/devices.h" #include "hw/arm/allwinner-a10.h" +#include "hw/misc/unimp.h" =20 static void aw_a10_init(Object *obj) { @@ -85,6 +86,11 @@ static void aw_a10_realize(DeviceState *dev, Error **err= p) sysbus_connect_irq(sysbusdev, 4, s->irq[67]); sysbus_connect_irq(sysbusdev, 5, s->irq[68]); =20 + memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, + &error_fatal); + memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_= a); + create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); + /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880712995631.397775069833; Mon, 7 Jan 2019 09:05:12 -0800 (PST) Received: from localhost ([127.0.0.1]:49846 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYKl-0005h6-52 for importer@patchew.org; Mon, 07 Jan 2019 12:05:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoi-00056k-HT for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoe-0002Gm-UV for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:56 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:44265) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXod-0002DU-2H for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:51 -0500 Received: by mail-wr1-x42b.google.com with SMTP id z5so1034408wrt.11 for ; Mon, 07 Jan 2019 08:31:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ve0B8kcL9xi8WPnq11WzGB1BxRiHUSFLk/M8udS3Wzw=; b=cNGnadjijC8aO/VlReFo7ujfxOJbSAaf1EuJi9jqY8qvYHF1ZpC74nbX5hFwft29hq INcvKJ2+01ATSQvRUGVE4sn3Q/22G2fst/Z/cxFL367s6yF6dTG/pRGUhhRMK5yoGPIR MeC/4t59j73t53zxhJRzliGrc2JbBs/6i4n6E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ve0B8kcL9xi8WPnq11WzGB1BxRiHUSFLk/M8udS3Wzw=; b=tr7Sn2j5M0J18c/glUHg204duHHT3JGTfm04NVWHFZgv2Dg6TrHtCnFnmyfN2hwTBp iYCUZLMOomivdlWZrfSiLHwQDCKLJhuMH2p46zb0naZVmv/X/A6BL0/Krbg+1L/O1frj mQhb2RdA5fIxD1v6pfcvD18gMdYekbmM38na9Sv5+uB1TTmlfu9TCoh6zLiC3fsJPgb/ 5VFYHknNa/GCcvK6eI2OY9ji5QDTHLYYs1r9NlwEIcnmr+hgCziYUgQo2XjjqlWYa5nr zsVqLs/b/1GEAiFfKWtecX2C0TBAEcTlgt/B4zd7t1HEI5p6mpIS/zUbTHEivRtYaiFb Ta0w== X-Gm-Message-State: AJcUukcFYhXWGjV4XM1T4rngcKNWWfV9rK29apd1M8Puc4TEUTmo1ct+ Wpb8l5Y6kxZAMpdXzBqZ/c4b6k+1WgX7Bw== X-Google-Smtp-Source: ALg8bN4QSksf/jouuvetaabzf3OD3gRG7I7PXyXFVuKkThTXjG34LaGqJIHZXA7Iz7V8JmuB0UZs8Q== X-Received: by 2002:a5d:4b01:: with SMTP id v1mr49734060wrq.5.1546878709459; Mon, 07 Jan 2019 08:31:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:04 +0000 Message-Id: <20190107163117.16269-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 24/37] qtest: Add set_irq_in command to set IRQ/GPIO level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Adds a new qtest command "set_irq_in" which allows to set qemu gpio lines to a given level. Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html which never got merged. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-2-stefanha@redhat.com Originally-by: Matthew Ogilvie Reviewed-by: Stefan Hajnoczi Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier Signed-off-by: Stefan Hajnoczi Signed-off-by: Peter Maydell --- tests/libqtest.h | 13 +++++++++++++ qtest.c | 43 +++++++++++++++++++++++++++++++++++++++++++ tests/libqtest.c | 10 ++++++++++ 3 files changed, 66 insertions(+) diff --git a/tests/libqtest.h b/tests/libqtest.h index 9758c51be61..7ea94139b0c 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -230,6 +230,19 @@ void qtest_irq_intercept_in(QTestState *s, const char = *string); */ void qtest_irq_intercept_out(QTestState *s, const char *string); =20 +/** + * qtest_set_irq_in: + * @s: QTestState instance to operate on. + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/irq GPIO-in pin to the given level. + */ +void qtest_set_irq_in(QTestState *s, const char *string, const char *name, + int irq, int level); + /** * qtest_outb: * @s: #QTestState instance to operate on. diff --git a/qtest.c b/qtest.c index 69b9e9962b5..451696b5dae 100644 --- a/qtest.c +++ b/qtest.c @@ -164,6 +164,17 @@ static bool qtest_opened; * where NUM is an IRQ number. For the PC, interrupts can be intercepted * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with * NUM=3D0 even though it is remapped to GSI 2). + * + * Setting interrupt level: + * + * > set_irq_in QOM-PATH NAME NUM LEVEL + * < OK + * + * where NAME is the name of the irq/gpio list, NUM is an IRQ number and + * LEVEL is an signed integer IRQ level. + * + * Forcibly set the given interrupt pin to the given level. + * */ =20 static int hex2nib(char ch) @@ -326,7 +337,39 @@ static void qtest_process_command(CharBackend *chr, gc= har **words) irq_intercept_dev =3D dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "set_irq_in") =3D=3D 0) { + DeviceState *dev; + qemu_irq irq; + char *name; + int ret; + int num; + int level; =20 + g_assert(words[1] && words[2] && words[3] && words[4]); + + dev =3D DEVICE(object_resolve_path(words[1], NULL)); + if (!dev) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown device\n"); + return; + } + + if (strcmp(words[2], "unnamed-gpio-in") =3D=3D 0) { + name =3D NULL; + } else { + name =3D words[2]; + } + + ret =3D qemu_strtoi(words[3], NULL, 0, &num); + g_assert(!ret); + ret =3D qemu_strtoi(words[4], NULL, 0, &level); + g_assert(!ret); + + irq =3D qdev_get_gpio_in_named(dev, name, num); + + qemu_set_irq(irq, level); + qtest_send_prefix(chr); + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") =3D=3D 0 || strcmp(words[0], "outw") =3D=3D 0 || strcmp(words[0], "outl") =3D=3D 0) { diff --git a/tests/libqtest.c b/tests/libqtest.c index 1d75d3c9363..55750dd68de 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -753,6 +753,16 @@ void qtest_irq_intercept_in(QTestState *s, const char = *qom_path) qtest_rsp(s, 0); } =20 +void qtest_set_irq_in(QTestState *s, const char *qom_path, const char *nam= e, + int num, int level) +{ + if (!name) { + name =3D "unnamed-gpio-in"; + } + qtest_sendf(s, "set_irq_in %s %s %d %d\n", qom_path, name, num, level); + qtest_rsp(s, 0); +} + static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint3= 2_t value) { qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value); --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880099418414.62394590369206; Mon, 7 Jan 2019 08:54:59 -0800 (PST) Received: from localhost ([127.0.0.1]:47864 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYB0-0006Dq-AM for importer@patchew.org; Mon, 07 Jan 2019 11:54:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXok-000592-G7 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXoi-0002Kv-7d for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:57 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXof-0002FG-6W for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:53 -0500 Received: by mail-wr1-x443.google.com with SMTP id t6so1025832wrr.12 for ; Mon, 07 Jan 2019 08:31:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aoJhloQbPryNA5qvMLJTb544BXc+pdlFTsnDtd737a0=; b=Jk4fe1hAdUZinb9W3U+hTYIzB3AQsQysfeY67g9IsvIyuy+5lAngEgtEQEtIP3lYdQ vP1nWm7nP8C+UPP7Zper9r3dsLc65m3vHjtFJod8JxWox5oR/4bjRqg3J6LYX0qRGdYs gvNGopgQukoCIO0kg2FKjpa75g1thSBmQqbD0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aoJhloQbPryNA5qvMLJTb544BXc+pdlFTsnDtd737a0=; b=eeHPgHEjySMrJhGZIagiBcGl9U4nP7P/DzOVGcKbKCnIA9oHVKBU21ho03gqravuZT rsEbElgUwwGOrpLB3PYW7SSkNHUBisuxy1ZtyXHH/XeCfGhBkLy+6L1fZn/d960N88Q9 K71M2MwvE1t9ZuNUM6r9ONPmLnXqBYH5pTHAv4yjhMHvSzsdI3F/JAHUkMBgwRCCByP7 q0I3U81o2mVEDZsnISfi2Fu2wwq++KtdtuycZwZxAuGCv2gZti5OQrmH+ORzo6fliXTl QdbPxNHXnC13mCa1+6KbOPhQSDbIaLX6r8gukRewqWHrt3rQRkF4DaD+CCCMfiUcRVNi YxHg== X-Gm-Message-State: AJcUukew7idU7BH7FNEq0QwfDqEx1R16eb9xsH5jZtrmr7/x8FTjBoke QY+TFEIlIAwKYTATrRwANzxQZYfY09S9tw== X-Google-Smtp-Source: ALg8bN5hCAhG5xm9r9CzS9L8iNRSnDRznkGT3TZblPvOhcWMBBy68EoWNbadWo8/vruPS+VSsLLUxQ== X-Received: by 2002:adf:f1cb:: with SMTP id z11mr44748595wro.35.1546878710653; Mon, 07 Jan 2019 08:31:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:05 +0000 Message-Id: <20190107163117.16269-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 25/37] arm: Add header to host common definition for nRF51 SOC peripherals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-3-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51.h | 45 ++++++++++++++++++++++++++++++++++++ include/hw/char/nrf51_uart.h | 1 - hw/arm/nrf51_soc.c | 33 ++++++++++---------------- 3 files changed, 57 insertions(+), 22 deletions(-) create mode 100644 include/hw/arm/nrf51.h diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h new file mode 100644 index 00000000000..175bb6c301e --- /dev/null +++ b/include/hw/arm/nrf51.h @@ -0,0 +1,45 @@ +/* + * Nordic Semiconductor nRF51 Series SOC Common Defines + * + * This file hosts generic defines used in various nRF51 peripheral device= s. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_H +#define NRF51_H + +#define NRF51_FLASH_BASE 0x00000000 +#define NRF51_FICR_BASE 0x10000000 +#define NRF51_FICR_SIZE 0x00000100 +#define NRF51_UICR_BASE 0x10001000 +#define NRF51_SRAM_BASE 0x20000000 + +#define NRF51_IOMEM_BASE 0x40000000 +#define NRF51_IOMEM_SIZE 0x20000000 + +#define NRF51_UART_BASE 0x40002000 +#define NRF51_TIMER_BASE 0x40008000 +#define NRF51_TIMER_SIZE 0x00001000 +#define NRF51_RNG_BASE 0x4000D000 +#define NRF51_NVMC_BASE 0x4001E000 +#define NRF51_GPIO_BASE 0x50000000 + +#define NRF51_PRIVATE_BASE 0xF0000000 +#define NRF51_PRIVATE_SIZE 0x10000000 + +#define NRF51_PAGE_SIZE 1024 + +/* Trigger */ +#define NRF51_TRIGGER_TASK 0x01 + +/* Events */ +#define NRF51_EVENT_CLEAR 0x00 + +#endif diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h index e3ecb7c81c2..eb1c15b490b 100644 --- a/include/hw/char/nrf51_uart.h +++ b/include/hw/char/nrf51_uart.h @@ -16,7 +16,6 @@ #include "hw/registerfields.h" =20 #define UART_FIFO_LENGTH 6 -#define UART_BASE 0x40002000 #define UART_SIZE 0x1000 =20 #define TYPE_NRF51_UART "nrf51_soc.uart" diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bdea08..55f8eaafcb0 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,27 +21,16 @@ #include "qemu/log.h" #include "cpu.h" =20 +#include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" =20 -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - -#define FLASH_BASE 0x00000000 -#define SRAM_BASE 0x20000000 - -#define PRIVATE_BASE 0xF0000000 -#define PRIVATE_SIZE 0x10000000 - /* * The size and base is for the NRF51822 part. If other parts * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) =20 @@ -76,14 +65,14 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash= ); =20 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); if (err) { error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); =20 /* UART */ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); @@ -92,15 +81,17 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr= , 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), - BASE_TO_IRQ(UART_BASE))); + BASE_TO_IRQ(NRF51_UART_BASE))); =20 - create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, + NRF51_IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, + NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", - PRIVATE_BASE, PRIVATE_SIZE); + NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } =20 static void nrf51_soc_init(Object *obj) --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154688087309565.78348405601832; Mon, 7 Jan 2019 09:07:53 -0800 (PST) Received: from localhost ([127.0.0.1]:50376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYNU-0007jx-1U for importer@patchew.org; Mon, 07 Jan 2019 12:07:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoq-0005Fe-LF for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXok-0002OM-Em for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:02 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39741) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXoi-0002GY-8s for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:31:56 -0500 Received: by mail-wm1-x334.google.com with SMTP id f81so1510966wmd.4 for ; Mon, 07 Jan 2019 08:31:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZG1ERp+/USLfyfNp6gYdXOw0W5fRiZ5jT4xT5OEh+C4=; b=HrwZiG10HT1R4MYmqyARigVRMrMP9q1tT7VqdT0Z4d4q4iHpLyKFHXg8es7Hhn90Cq z7G3HbIXm9UibBBIvYHapM0sXGQ/WvNlq8D2uDQP/xgeHn4wqHWESJx5fseiFenXCteY M5Mk06AoeV4GLzLKMiI5kPgZSDOLr0Wf3GQrY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZG1ERp+/USLfyfNp6gYdXOw0W5fRiZ5jT4xT5OEh+C4=; b=X2iqa1/ylpI7ItVjTSnzApMjQ8fEKmrze2gqUGPhWvcL1hRZ4FZQ9c1qOhaD6tFtBr leYe4Rz+B73Kox1ub8Pw82YMk0Bw5imX/x9mHMy2YJeglNQJ2+1QQuHuEqTbL4Kt+Yr4 8B9lbA5AJqi866Q0+kaOY1QBf+i4MEsFGvBotVZecm1Pm1IrvRCKgvor+eCVFozJ1gNu YqUO5b4kPVG020yvqRUQ4bhXYT+5gjNTj4yXHq/uscVQEzKmdogzYXYo3IuS5NSEhwuH IIglPfxv/ag1qPnKZDYj3P1FE5xv9D8dYL+u6ZupkYE9rSk0fziDMVN3ZWqLFFzP5+AP rM7A== X-Gm-Message-State: AJcUukdR+lWw/TEd5DbIympDkPpWkP4DC+drGjMvPglU0Fm4xzefDTJv 6NETN47rV4huCoK0k9hRXbhW8g9YLghGqg== X-Google-Smtp-Source: ALg8bN6oGQ0XaK6c7kYFhB2eV/JCIoxGmneEKAZ8cPlyRVZsQG4ZBP8c3h9di6fEtFETpRkVyLXbAw== X-Received: by 2002:a1c:ac85:: with SMTP id v127mr8319914wme.62.1546878711946; Mon, 07 Jan 2019 08:31:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:06 +0000 Message-Id: <20190107163117.16269-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 26/37] hw/misc/nrf51_rng: Add NRF51 random number generator peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Add a model of the NRF51 random number generator peripheral. This is a simple random generator that continuously generates new random values after startup. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-4-stefanha@redhat.com Signed-off-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + include/hw/misc/nrf51_rng.h | 83 ++++++++++++ hw/misc/nrf51_rng.c | 262 ++++++++++++++++++++++++++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 include/hw/misc/nrf51_rng.h create mode 100644 hw/misc/nrf51_rng.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 680350b3c3b..04f3bfa516e 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -74,3 +74,4 @@ obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o diff --git a/include/hw/misc/nrf51_rng.h b/include/hw/misc/nrf51_rng.h new file mode 100644 index 00000000000..3d6bf799977 --- /dev/null +++ b/include/hw/misc/nrf51_rng.h @@ -0,0 +1,83 @@ +/* + * nRF51 Random Number Generator + * + * QEMU interface: + * + Property "period_unfiltered_us": Time between two biased values in + * microseconds. + * + Property "period_filtered_us": Time between two unbiased values in + * microseconds. + * + sysbus MMIO regions 0: Memory Region with tasks, events and registers + * to be mapped to the peripherals instance address by the SOC. + * + Named GPIO output "irq": Interrupt line of the peripheral. Must be + * connected to the associated peripheral interrupt line of the NVIC. + * + Named GPIO output "eep_valrdy": Event set when new random value is re= ady + * to be read. + * + Named GPIO input "tep_start": Task that triggers start of continuous + * generation of random values. + * + Named GPIO input "tep_stop": Task that ends continuous generation of + * random values. + * + * Accuracy of the peripheral model: + * + Stochastic properties of different configurations of the random source + * are not modeled. + * + Generation of unfiltered and filtered random values take at least the + * average generation time stated in the production specification; + * non-deterministic generation times are not modeled. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_RNG_H +#define NRF51_RNG_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_RNG "nrf51_soc.rng" +#define NRF51_RNG(obj) OBJECT_CHECK(NRF51RNGState, (obj), TYPE_NRF51_RNG) + +#define NRF51_RNG_SIZE 0x1000 + +#define NRF51_RNG_TASK_START 0x000 +#define NRF51_RNG_TASK_STOP 0x004 +#define NRF51_RNG_EVENT_VALRDY 0x100 +#define NRF51_RNG_REG_SHORTS 0x200 +#define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0 +#define NRF51_RNG_REG_INTEN 0x300 +#define NRF51_RNG_REG_INTEN_VALRDY 0 +#define NRF51_RNG_REG_INTENSET 0x304 +#define NRF51_RNG_REG_INTENCLR 0x308 +#define NRF51_RNG_REG_CONFIG 0x504 +#define NRF51_RNG_REG_CONFIG_DECEN 0 +#define NRF51_RNG_REG_VALUE 0x508 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + /* Event End Points */ + qemu_irq eep_valrdy; + + QEMUTimer timer; + + /* Time between generation of successive unfiltered values in us */ + uint16_t period_unfiltered_us; + /* Time between generation of successive filtered values in us */ + uint16_t period_filtered_us; + + uint8_t value; + + uint32_t active; + uint32_t event_valrdy; + uint32_t shortcut_stop_on_valrdy; + uint32_t interrupt_enabled; + uint32_t filter_enabled; + +} NRF51RNGState; + + +#endif /* NRF51_RNG_H_ */ diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c new file mode 100644 index 00000000000..d188f044f4c --- /dev/null +++ b/hw/misc/nrf51_rng.c @@ -0,0 +1,262 @@ +/* + * nRF51 Random Number Generator + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.= pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/arm/nrf51.h" +#include "hw/misc/nrf51_rng.h" +#include "crypto/random.h" + +static void update_irq(NRF51RNGState *s) +{ + bool irq =3D s->interrupt_enabled && s->event_valrdy; + qemu_set_irq(s->irq, irq); +} + +static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_RNG_EVENT_VALRDY: + r =3D s->event_valrdy; + break; + case NRF51_RNG_REG_SHORTS: + r =3D s->shortcut_stop_on_valrdy; + break; + case NRF51_RNG_REG_INTEN: + case NRF51_RNG_REG_INTENSET: + case NRF51_RNG_REG_INTENCLR: + r =3D s->interrupt_enabled; + break; + case NRF51_RNG_REG_CONFIG: + r =3D s->filter_enabled; + break; + case NRF51_RNG_REG_VALUE: + r =3D s->value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + return r; +} + +static int64_t calc_next_timeout(NRF51RNGState *s) +{ + int64_t timeout =3D qemu_clock_get_us(QEMU_CLOCK_VIRTUAL); + if (s->filter_enabled) { + timeout +=3D s->period_filtered_us; + } else { + timeout +=3D s->period_unfiltered_us; + } + + return timeout; +} + + +static void rng_update_timer(NRF51RNGState *s) +{ + if (s->active) { + timer_mod(&s->timer, calc_next_timeout(s)); + } else { + timer_del(&s->timer); + } +} + + +static void rng_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + switch (offset) { + case NRF51_RNG_TASK_START: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->active =3D 1; + rng_update_timer(s); + } + break; + case NRF51_RNG_TASK_STOP: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->active =3D 0; + rng_update_timer(s); + } + break; + case NRF51_RNG_EVENT_VALRDY: + if (value =3D=3D NRF51_EVENT_CLEAR) { + s->event_valrdy =3D 0; + } + break; + case NRF51_RNG_REG_SHORTS: + s->shortcut_stop_on_valrdy =3D + (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 := 0; + break; + case NRF51_RNG_REG_INTEN: + s->interrupt_enabled =3D + (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTENSET: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled =3D 1; + } + break; + case NRF51_RNG_REG_INTENCLR: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled =3D 0; + } + break; + case NRF51_RNG_REG_CONFIG: + s->filter_enabled =3D + (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 := 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops =3D { + .read =3D rng_read, + .write =3D rng_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4 +}; + +static void nrf51_rng_timer_expire(void *opaque) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + qcrypto_random_bytes(&s->value, 1, &error_abort); + + s->event_valrdy =3D 1; + qemu_set_irq(s->eep_valrdy, 1); + + if (s->shortcut_stop_on_valrdy) { + s->active =3D 0; + } + + rng_update_timer(s); + update_irq(s); +} + +static void nrf51_rng_tep_start(void *opaque, int n, int level) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + if (level) { + s->active =3D 1; + rng_update_timer(s); + } +} + +static void nrf51_rng_tep_stop(void *opaque, int n, int level) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + if (level) { + s->active =3D 0; + rng_update_timer(s); + } +} + + +static void nrf51_rng_init(Object *obj) +{ + NRF51RNGState *s =3D NRF51_RNG(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &rng_ops, s, + TYPE_NRF51_RNG, NRF51_RNG_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s= ); + + sysbus_init_irq(sbd, &s->irq); + + /* Tasks */ + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1= ); + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1); + + /* Events */ + qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1); +} + +static void nrf51_rng_reset(DeviceState *dev) +{ + NRF51RNGState *s =3D NRF51_RNG(dev); + + s->value =3D 0; + s->active =3D 0; + s->event_valrdy =3D 0; + s->shortcut_stop_on_valrdy =3D 0; + s->interrupt_enabled =3D 0; + s->filter_enabled =3D 0; + + rng_update_timer(s); +} + + +static Property nrf51_rng_properties[] =3D { + DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState, + period_unfiltered_us, 167), + DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState, + period_filtered_us, 660), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_rng =3D { + .name =3D "nrf51_soc.rng", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(active, NRF51RNGState), + VMSTATE_UINT32(event_valrdy, NRF51RNGState), + VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState), + VMSTATE_UINT32(interrupt_enabled, NRF51RNGState), + VMSTATE_UINT32(filter_enabled, NRF51RNGState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_rng_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D nrf51_rng_properties; + dc->vmsd =3D &vmstate_rng; + dc->reset =3D nrf51_rng_reset; +} + +static const TypeInfo nrf51_rng_info =3D { + .name =3D TYPE_NRF51_RNG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51RNGState), + .instance_init =3D nrf51_rng_init, + .class_init =3D nrf51_rng_class_init +}; + +static void nrf51_rng_register_types(void) +{ + type_register_static(&nrf51_rng_info); +} + +type_init(nrf51_rng_register_types) --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XymL7pcCKQT8uzmAs4HmJG8FvkXF5Ktuexr4yE01WvA=; b=HK1ftAeN3CoMP4wGqYpse+HOEep3D+zWXBrP9y+Zniy55WTkhs2sFZy0z512LRxVlM W5jPpK5GC4SA1UZTGcMRSNprItjGVcBzVcaFRQDT9jPJPhGVe9+gVJlZZqjoxDE2jJcd 2q7eis4o+zTRJrgYSTE0btnYhH4ezlG4No1rc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XymL7pcCKQT8uzmAs4HmJG8FvkXF5Ktuexr4yE01WvA=; b=dEKXWaNVKg3rikfc6z3SXDK1zU3mjHrYYar2ib7kS9ObIq3fS9V/NqQy8O+ZRdzJ+T qSqddt1qKeWVSxrXwn+HxnDQUar0sS9fLSv4Dy5qBEObmFdfbpbbrdmpB5pCDpKzgED/ reHbsG7IMfZQn/aEXe5ipHEjjL1OCPr8QXTILrHzi0l43ufZYO7jd3joCKjqr27WDXXP IfhN660YqryJFr5uAAhaJOdIYIxuLIhv1M6n0tLISHsLoI400oevf6V4cELALLGt1dDx qPoZG1t1+79BWHIUnfgGLgVa6qtafeaCE4GNOsoSK3KM+rQFbFJfMACDw+jIpB4buSLv wDGA== X-Gm-Message-State: AJcUuke79+n3sQPjdKgwp7bGphVTF+nGd2Zne6xpsMvkz7/VzRvJLRv2 JyhZnXof0m/R0p/cc+TGll3mjZaiYXyLww== X-Google-Smtp-Source: ALg8bN5D3HNTULXqYaKhC4ZC51q0ft1i3dglxWbvLsPo39epgQAF39wG1uFqmPTZBDui/BFwdHW2wg== X-Received: by 2002:a1c:910e:: with SMTP id t14mr9056378wmd.111.1546878713160; Mon, 07 Jan 2019 08:31:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:07 +0000 Message-Id: <20190107163117.16269-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 27/37] arm: Instantiate NRF51 random number generator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Use RNG in SOC. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-5-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 73fc92e9a8d..9e3ba916bd0 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" +#include "hw/misc/nrf51_rng.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -26,6 +27,7 @@ typedef struct NRF51State { ARMv7MState cpu; =20 NRF51UARTState uart; + NRF51RNGState rng; =20 MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 55f8eaafcb0..d2a19b8eadd 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -86,6 +86,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_UART_BASE))); =20 + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr,= 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(NRF51_RNG_BASE))); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -110,6 +123,9 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_UART); object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", &error_abort); + + sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_NRF51_RNG); } =20 static Property nrf51_soc_properties[] =3D { --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546880252476357.57871882320046; Mon, 7 Jan 2019 08:57:32 -0800 (PST) Received: from localhost ([127.0.0.1]:48522 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYDT-0008Rt-A3 for importer@patchew.org; Mon, 07 Jan 2019 11:57:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXpN-0005fQ-4P for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXpK-00038x-33 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:35 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:42853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXpG-0002KK-6N for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:32 -0500 Received: by mail-wr1-x434.google.com with SMTP id q18so1048717wrx.9 for ; Mon, 07 Jan 2019 08:31:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K4G4en5CZrdXfv5pe8Z+g+gS1rF1AOdP0MUzboLucIE=; b=T0IzQMaLGXxk0WKn1DQG96UyUG5Or/7p/Wx8KKOvV65nJc4Qc5TkG2N0d+hWRfMuw+ aIuqCZfP5T/OqtedY23iM5q52+ZqSJEyQcEA2mY+abZ0AIqGsFAX8W4brTBnzM8JswNY O0xMyjcgngdiO/G4akqOSmpjCk9ARbGdPTM4U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K4G4en5CZrdXfv5pe8Z+g+gS1rF1AOdP0MUzboLucIE=; b=If0+wS3lM1/kAE3QTekF/v1W2PDY19nbERce8nY9uXUaosD7brDFwTfz3kMQwobkBl s75o01qWc7b09/OQhW+rD4myiFQ1Tfqw2LXdbHSSeemgUJqaR/e9lHwjLyR4bHga+wz3 XmakfFpd4yatbIHFHBUrNFkPyi2NN+6hrSumZleFIeZJyb0zkHnb76xtfiZeo25eTcPg iIo35cuEl3dTLRK2/wNc9sJ3dqCr9K/4wRd7xk64wmI9Yp3Xt7hvy8Ps94aTZWSZoesx w9Sqb/1OvR9HTIXdeGgBDHJYNXMTAFcBgYQBKGO1c6CSlANz40HXl6dMF5udH+a8EsV0 pgXg== X-Gm-Message-State: AJcUukfGe17pkJ2xY4QO7ieYzveR68qMz5JBvMwVjzjJMwBHl/24U/0b gh4HfOYyy1SfUXr13j/ELZ4bheI+YDpgPA== X-Google-Smtp-Source: ALg8bN5KDcyFMPcI3oOTzIXyz7zod/2jPXE+5xtZgkrA64CAUi0zmdzv66aQStVD0VYjPZIQd6PLmw== X-Received: by 2002:adf:bc02:: with SMTP id s2mr50719998wrg.255.1546878714769; Mon, 07 Jan 2019 08:31:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:08 +0000 Message-Id: <20190107163117.16269-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 28/37] hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz This adds a model of the nRF51 GPIO peripheral. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf The nRF51 series microcontrollers support up to 32 GPIO pins in various con= figurations. The pins can be used as input pins with pull-ups or pull-down. Furthermore, three different output driver modes per level are available (disconnected, standard, high-current). The GPIO-Peripheral has a mechanism for detecting level changes which is not featured in this model. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-6-stefanha@redhat.com Signed-off-by: Peter Maydell --- Makefile.objs | 1 + hw/gpio/Makefile.objs | 1 + include/hw/gpio/nrf51_gpio.h | 69 ++++++++ hw/gpio/nrf51_gpio.c | 300 +++++++++++++++++++++++++++++++++++ hw/gpio/trace-events | 7 + 5 files changed, 378 insertions(+) create mode 100644 include/hw/gpio/nrf51_gpio.h create mode 100644 hw/gpio/nrf51_gpio.c create mode 100644 hw/gpio/trace-events diff --git a/Makefile.objs b/Makefile.objs index bc5b8a8442f..456115992a4 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -184,6 +184,7 @@ trace-events-subdirs +=3D hw/vfio trace-events-subdirs +=3D hw/virtio trace-events-subdirs +=3D hw/watchdog trace-events-subdirs +=3D hw/xen +trace-events-subdirs +=3D hw/gpio trace-events-subdirs +=3D io trace-events-subdirs +=3D linux-user trace-events-subdirs +=3D migration diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index fa0a72e6d0c..e5da0cb54fe 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -8,3 +8,4 @@ common-obj-$(CONFIG_GPIO_KEY) +=3D gpio_key.o obj-$(CONFIG_OMAP) +=3D omap_gpio.o obj-$(CONFIG_IMX) +=3D imx_gpio.o obj-$(CONFIG_RASPI) +=3D bcm2835_gpio.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_gpio.o diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h new file mode 100644 index 00000000000..337ee534bbc --- /dev/null +++ b/include/hw/gpio/nrf51_gpio.h @@ -0,0 +1,69 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin. + * Level -1: Externally Disconnected/Floating; Pull-up/down will be rega= rded + * Level 0: Input externally driven LOW + * Level 1: Input externally driven HIGH + * + Unnamed GPIO outputs 0-31: + * Level -1: Disconnected/Floating + * Level 0: Driven LOW + * Level 1: Driven HIGH + * + * Accuracy of the peripheral model: + * + The nRF51 GPIO output driver supports two modes, standard and high-cu= rrent + * mode. These different drive modes are not modeled and handled the sam= e. + * + Pin SENSEing is not modeled/implemented. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_GPIO_H +#define NRF51_GPIO_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_GPIO "nrf51_soc.gpio" +#define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPI= O) + +#define NRF51_GPIO_PINS 32 + +#define NRF51_GPIO_SIZE 0x1000 + +#define NRF51_GPIO_REG_OUT 0x504 +#define NRF51_GPIO_REG_OUTSET 0x508 +#define NRF51_GPIO_REG_OUTCLR 0x50C +#define NRF51_GPIO_REG_IN 0x510 +#define NRF51_GPIO_REG_DIR 0x514 +#define NRF51_GPIO_REG_DIRSET 0x518 +#define NRF51_GPIO_REG_DIRCLR 0x51C +#define NRF51_GPIO_REG_CNF_START 0x700 +#define NRF51_GPIO_REG_CNF_END 0x77F + +#define NRF51_GPIO_PULLDOWN 1 +#define NRF51_GPIO_PULLUP 3 + +typedef struct NRF51GPIOState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t out; + uint32_t in; + uint32_t in_mask; + uint32_t dir; + uint32_t cnf[NRF51_GPIO_PINS]; + + uint32_t old_out; + uint32_t old_out_connected; + + qemu_irq output[NRF51_GPIO_PINS]; +} NRF51GPIOState; + + +#endif diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c new file mode 100644 index 00000000000..86e047d649f --- /dev/null +++ b/hw/gpio/nrf51_gpio.c @@ -0,0 +1,300 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/gpio/nrf51_gpio.h" +#include "trace.h" + +/* + * Check if the output driver is connected to the direction switch + * given the current configuration and logic level. + * It is not differentiated between standard and "high"(-power) drive mode= s. + */ +static bool is_connected(uint32_t config, uint32_t level) +{ + bool state; + uint32_t drive_config =3D extract32(config, 8, 3); + + switch (drive_config) { + case 0 ... 3: + state =3D true; + break; + case 4 ... 5: + state =3D level !=3D 0; + break; + case 6 ... 7: + state =3D level =3D=3D 0; + break; + default: + g_assert_not_reached(); + break; + } + + return state; +} + +static void update_output_irq(NRF51GPIOState *s, size_t i, + bool connected, bool level) +{ + int64_t irq_level =3D connected ? level : -1; + bool old_connected =3D extract32(s->old_out_connected, i, 1); + bool old_level =3D extract32(s->old_out, i, 1); + + if ((old_connected !=3D connected) || (old_level !=3D level)) { + qemu_set_irq(s->output[i], irq_level); + trace_nrf51_gpio_update_output_irq(i, irq_level); + } + + s->old_out =3D deposit32(s->old_out, i, 1, level); + s->old_out_connected =3D deposit32(s->old_out_connected, i, 1, connect= ed); +} + +static void update_state(NRF51GPIOState *s) +{ + uint32_t pull; + size_t i; + bool connected_out, dir, connected_in, out, input; + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + pull =3D extract32(s->cnf[i], 2, 2); + dir =3D extract32(s->cnf[i], 0, 1); + connected_in =3D extract32(s->in_mask, i, 1); + out =3D extract32(s->out, i, 1); + input =3D !extract32(s->cnf[i], 1, 1); + connected_out =3D is_connected(s->cnf[i], out) && dir; + + update_output_irq(s, i, connected_out, out); + + /* Pin both driven externally and internally */ + if (connected_out && connected_in) { + qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n= ", i); + } + + /* + * Input buffer disconnected from internal/external drives, so + * pull-up/pull-down becomes relevant + */ + if (!input || (input && !connected_in && !connected_out)) { + if (pull =3D=3D NRF51_GPIO_PULLDOWN) { + s->in =3D deposit32(s->in, i, 1, 0); + } else if (pull =3D=3D NRF51_GPIO_PULLUP) { + s->in =3D deposit32(s->in, i, 1, 1); + } + } + + /* Self stimulation through internal output driver */ + if (connected_out && !connected_in && input) { + s->in =3D deposit32(s->in, i, 1, out); + } + } + +} + +/* + * Direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. Reflect bits for pins in DIR + * to individual pin configuration registers. + */ +static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) +{ + size_t i; + + uint32_t value =3D s->dir; + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] =3D (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); + } +} + +static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int = size) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + uint64_t r =3D 0; + size_t idx; + + switch (offset) { + case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: + r =3D s->out; + break; + + case NRF51_GPIO_REG_IN: + r =3D s->in; + break; + + case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: + r =3D s->dir; + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx =3D (offset - NRF51_GPIO_REG_CNF_START) / 4; + r =3D s->cnf[idx]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_gpio_read(offset, r); + + return r; +} + +static void nrf51_gpio_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + size_t idx; + + trace_nrf51_gpio_write(offset, value); + + switch (offset) { + case NRF51_GPIO_REG_OUT: + s->out =3D value; + break; + + case NRF51_GPIO_REG_OUTSET: + s->out |=3D value; + break; + + case NRF51_GPIO_REG_OUTCLR: + s->out &=3D ~value; + break; + + case NRF51_GPIO_REG_DIR: + s->dir =3D value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRSET: + s->dir |=3D value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRCLR: + s->dir &=3D ~value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx =3D (offset - NRF51_GPIO_REG_CNF_START) / 4; + s->cnf[idx] =3D value; + /* + * direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. + */ + s->dir =3D (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_state(s); +} + +static const MemoryRegionOps gpio_ops =3D { + .read =3D nrf51_gpio_read, + .write =3D nrf51_gpio_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void nrf51_gpio_set(void *opaque, int line, int value) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + + trace_nrf51_gpio_set(line, value); + + assert(line >=3D 0 && line < NRF51_GPIO_PINS); + + s->in_mask =3D deposit32(s->in_mask, line, 1, value >=3D 0); + if (value >=3D 0) { + s->in =3D deposit32(s->in, line, 1, value !=3D 0); + } + + update_state(s); +} + +static void nrf51_gpio_reset(DeviceState *dev) +{ + NRF51GPIOState *s =3D NRF51_GPIO(dev); + size_t i; + + s->out =3D 0; + s->old_out =3D 0; + s->old_out_connected =3D 0; + s->in =3D 0; + s->in_mask =3D 0; + s->dir =3D 0; + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] =3D 0x00000002; + } +} + +static const VMStateDescription vmstate_nrf51_gpio =3D { + .name =3D TYPE_NRF51_GPIO, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(out, NRF51GPIOState), + VMSTATE_UINT32(in, NRF51GPIOState), + VMSTATE_UINT32(in_mask, NRF51GPIOState), + VMSTATE_UINT32(dir, NRF51GPIOState), + VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), + VMSTATE_UINT32(old_out, NRF51GPIOState), + VMSTATE_UINT32(old_out_connected, NRF51GPIOState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_gpio_init(Object *obj) +{ + NRF51GPIOState *s =3D NRF51_GPIO(obj); + + memory_region_init_io(&s->mmio, obj, &gpio_ops, s, + TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); + qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); +} + +static void nrf51_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_nrf51_gpio; + dc->reset =3D nrf51_gpio_reset; + dc->desc =3D "nRF51 GPIO"; +} + +static const TypeInfo nrf51_gpio_info =3D { + .name =3D TYPE_NRF51_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51GPIOState), + .instance_init =3D nrf51_gpio_init, + .class_init =3D nrf51_gpio_class_init +}; + +static void nrf51_gpio_register_types(void) +{ + type_register_static(&nrf51_gpio_info); +} + +type_init(nrf51_gpio_register_types) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events new file mode 100644 index 00000000000..cb41a897569 --- /dev/null +++ b/hw/gpio/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/gpio/nrf51_gpio.c +nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0= x%" PRIx64 +nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " va= lue 0x%" PRIx64 +nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRI= i64 +nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 \ No newline at end of file --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VeXnL2tM16F/u9dffjDOKKDeWnJOZ3mNmXRfne7h87U=; b=QWrtw09+6uk1/LXmGovZEBvgnEtUdwvCtJ944kmAMYfx1wd/cjrGRXdegBLsO/rQlb 5oLnnPUnp5m97oQFMGxJjSX3I5A739+JztDUlu650vpi+hiS6DlQDtqMxfHJyu4ty7FO hLMl1IGJE1OCAAtXGAvuiCXWLHvlfJzOhd4CE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VeXnL2tM16F/u9dffjDOKKDeWnJOZ3mNmXRfne7h87U=; b=gmD8powTT3dzCuxsh36SClAQE2xTbH4QAGF27nBKzjpunaH+gfqkpfqNjATZlO4okQ LXIgfNFWI+9OGb+hmmGyJV1UkrOhDkhS6t5flhMojWF+WO9cfBObMrQv1R3ohCEBdWYv AXYBHTb5H2L/Dlpg9HynWKC5FMZsS547bByGSnA4dhpsPJ0E9P4WN7k79wV1v7QjsqDb kWu9cfh6M/w1Oehfts0TyhraJWFqU+Z3hgG1T51Lpzn6fPqQrpDDW67FHsPFPiM3cbo9 pAwKu/XOnuhiJ14fatdKRnt2jGtqokANpwCM585HulRupEnXvaLEJSrNyWFMTusDJ46u YCzg== X-Gm-Message-State: AJcUukdsjcjz/R+bOn8jjhIc/sSxVyt5H8Mz4obl1Wocd8+8l+BQ4UVb Dc84DfwOhWlCC9eYJt8viQGdiJfAM2gMfA== X-Google-Smtp-Source: ALg8bN4/sJYjeJ1MA2n690hKHBwTTMSQY5Mm2/fPdj4Vtvo9s8v0yb+NwXJfsIHgv1DgHb2znvg5uQ== X-Received: by 2002:adf:c452:: with SMTP id a18mr53330748wrg.145.1546878715849; Mon, 07 Jan 2019 08:31:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:09 +0000 Message-Id: <20190107163117.16269-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 29/37] arm: Instantiate NRF51 general purpose I/O X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Instantiates GPIO peripheral model Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-7-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 9e3ba916bd0..84e0278881b 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -14,6 +14,7 @@ #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" +#include "hw/gpio/nrf51_gpio.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -28,6 +29,7 @@ typedef struct NRF51State { =20 NRF51UARTState uart; NRF51RNGState rng; + NRF51GPIOState gpio; =20 MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index d2a19b8eadd..db817fe5064 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -99,6 +99,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); =20 + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr= , 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board = */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -126,6 +139,9 @@ static void nrf51_soc_init(Object *obj) =20 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), TYPE_NRF51_RNG); + + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_NRF51_GPIO); } =20 static Property nrf51_soc_properties[] =3D { --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879273721659.3191570166944; Mon, 7 Jan 2019 08:41:13 -0800 (PST) Received: from localhost ([127.0.0.1]:44621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXxg-0003oX-H3 for importer@patchew.org; Mon, 07 Jan 2019 11:41:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXoq-0005Fi-ND for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXon-0002Ts-RD for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:04 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38747) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXok-0002Np-Lx for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:00 -0500 Received: by mail-wr1-x42a.google.com with SMTP id v13so1075124wrw.5 for ; Mon, 07 Jan 2019 08:31:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pFFnt0PGN+JXnIxcfblwupVgdtnANwbtO3wSuWa/d4k=; b=GdeLa6j1OlylOhhF3+3XBnMlUS/7gRIz3dZ4XIP/E4MwjoOZvHZayEeNMBJNxMx1GW hGC0krN1jaaaWvgwzwC/hdlj/15rdZeeLTuRPe8IAnVENWEqxhkSm3Ai8fUzuDJKHVK7 JYGLWz7mTBBWllijDp3EbyxPSizbY2hBt+R0s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pFFnt0PGN+JXnIxcfblwupVgdtnANwbtO3wSuWa/d4k=; b=mT9Zcidzr+3IF+EvBO/35+DRIyqOQw95heAKHTzyNNR8kR9ZE5XpU5PVhPjAkDotZ6 NpXhjI9XPicfeZ3Pr3GTXlM2fHL455UA4hVh4hPfra5q0cu2aMxFRIK7b7RwRXrRD8oZ XWEtSUW1b9baHMrP+Aviv7bQDXWVWAeGP+2bYC1eBd5Ji+4nhQYEJ/XjdpMSbADpVXT9 5WS0ZVldgJJhs620m1+2R/Nl5+/YKdobNtb1JXp+TXz9qwbH+/AhWmm7kJB+yGbeBD7Y 8zedfxMzrqhLvekU1WSpm0UipALzXi+UZT9floynkRnJtxxoSYPy4a3kaZNiZ8sHfOCs /vFA== X-Gm-Message-State: AJcUukfQKXzkY3rNFQOKPPWx89xv0fcYx2fIvGglzvSpgutuIS5cyehk Rrjt3mzOY9FmySRVRGoGl/y7iFR1fXIqmg== X-Google-Smtp-Source: ALg8bN5sj5uns1sAwwz+oFovhAtOWOWzEhsfQmcwfIUlSHdkusAsMqROdaJhAI3SqN3qeZZKbTRQ7g== X-Received: by 2002:adf:e846:: with SMTP id d6mr54582144wrn.72.1546878717152; Mon, 07 Jan 2019 08:31:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:10 +0000 Message-Id: <20190107163117.16269-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 30/37] tests/microbit-test: Add Tests for nRF51 GPIO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz The test suite for the nRF51 GPIO peripheral for now only tests initial state. Additionally a set of tests testing an implementation detail of the model are included. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-8-stefanha@redhat.com [PMM: fixed stray space at start of file] Signed-off-by: Peter Maydell --- tests/Makefile.include | 2 + tests/microbit-test.c | 160 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) create mode 100644 tests/microbit-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index 3f5a1d0c308..9c84bbd8296 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -277,6 +277,7 @@ check-qtest-sparc64-y +=3D tests/boot-serial-test$(EXES= UF) check-qtest-arm-y +=3D tests/tmp105-test$(EXESUF) check-qtest-arm-y +=3D tests/pca9552-test$(EXESUF) check-qtest-arm-y +=3D tests/ds1338-test$(EXESUF) +check-qtest-arm-y +=3D tests/microbit-test$(EXESUF) check-qtest-arm-y +=3D tests/m25p80-test$(EXESUF) check-qtest-arm-y +=3D tests/virtio-blk-test$(EXESUF) check-qtest-arm-y +=3D tests/test-arm-mptimer$(EXESUF) @@ -708,6 +709,7 @@ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-se= ctor.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/microbit-test.c b/tests/microbit-test.c new file mode 100644 index 00000000000..f0a180cbc6f --- /dev/null +++ b/tests/microbit-test.c @@ -0,0 +1,160 @@ +/* + * QTest testcase for Microbit board using the Nordic Semiconductor nRF51 = SoC. + * + * nRF51: + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Microbit Board: http://microbit.org/ + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "libqtest.h" + +#include "hw/arm/nrf51.h" +#include "hw/gpio/nrf51_gpio.h" + +static void test_nrf51_gpio(void) +{ + size_t i; + uint32_t actual, expected; + + struct { + hwaddr addr; + uint32_t expected; + } const reset_state[] =3D { + {NRF51_GPIO_REG_OUT, 0x00000000}, {NRF51_GPIO_REG_OUTSET, 0x000000= 00}, + {NRF51_GPIO_REG_OUTCLR, 0x00000000}, {NRF51_GPIO_REG_IN, 0x0000000= 0}, + {NRF51_GPIO_REG_DIR, 0x00000000}, {NRF51_GPIO_REG_DIRSET, 0x000000= 00}, + {NRF51_GPIO_REG_DIRCLR, 0x00000000} + }; + + /* Check reset state */ + for (i =3D 0; i < ARRAY_SIZE(reset_state); i++) { + expected =3D reset_state[i].expected; + actual =3D readl(NRF51_GPIO_BASE + reset_state[i].addr); + g_assert_cmpuint(actual, =3D=3D, expected); + } + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + expected =3D 0x00000002; + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * = 4); + g_assert_cmpuint(actual, =3D=3D, expected); + } + + /* Check dir bit consistency between dir and cnf */ + /* Check set via DIRSET */ + expected =3D 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + /* Check clear via DIRCLR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, 0x00000000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + + /* Check set via DIR */ + expected =3D 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + /* Reset DIR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); + + /* Check Input propagates */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 1); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= -1); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-up working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-down working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 1); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= -1); + + /* Check Output propagates */ + irq_intercept_out("/machine/nrf51"); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + g_assert_true(get_irq(0)); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + g_assert_false(get_irq(0)); + + /* Check self-stimulation */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + + /* + * Check short-circuit - generates an guest_error which must be checked + * manually as long as qtest can not scan qemu_log messages + */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + global_qtest =3D qtest_initf("-machine microbit"); + + qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + + ret =3D g_test_run(); + + qtest_quit(global_qtest); + return ret; +} --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546881061904691.5336611080827; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cG8p5TrhEnfEX/Ht6f0JMxYUYW9ftu0xiFRk6CK6OaI=; b=jYbfCzQpH3cT13GB7t6zlIFhXDwD/JATfIH99zb09Rv0pU1XLgEOhudbW1VdHhHCTG 18l2JOqelJV/TgUJdPU+4Go4RCWR2ihETBZtswUwndby/nTGkWLlGHQ/i+acSGau4tzV RpaLrb9LvR3Bp6WqrPUIRkuYmoRPfS6s0T6CI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cG8p5TrhEnfEX/Ht6f0JMxYUYW9ftu0xiFRk6CK6OaI=; b=sZc+Ndx1sqFca+imGeyXv33/tdysGMLiZ03o/LSvtbYWUIvMbPnvTW0t/JAUcpL9eq LyRJze6by0IbFFNYhBQaLTypL0XLbocxWRyDgVbWr+JEjjwh6UuvEFsKO7gYeEGaI8j+ EQEbqcpgwBrisooW7mM9u7/0ueeoYbk5/0X9S1yQcF9EV5Iq65vnqTHG704ii0lj/UsH FiNUThFjzs3E4CGdbm+enowOdt7X7QtH07AOGh62bCzZ8lcSW2h4K5QfAF1xbWxoIBOr SgNKcmJwpEX81PC4/aw2WZUimOrs+4s8tv8eaeSf3x91H5uc010IvyvrM/zRGmVRTxq1 56WA== X-Gm-Message-State: AJcUukdeM1SPByDazeDuWq5svy8MuFC4OD/uEMvuIDxacPqUx/bThVzg Ls6Yxkz2SwhoIcPWxs9cBid7VVs+UA6uPA== X-Google-Smtp-Source: ALg8bN4G+a1LneupwD3KO2wQxYk92gG1Rlz8s7N35e/Q8zlsd8jCfx4gs2M2taAoUei0XkckW3Vr/g== X-Received: by 2002:a1c:13d1:: with SMTP id 200mr9079980wmt.4.1546878718618; Mon, 07 Jan 2019 08:31:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:11 +0000 Message-Id: <20190107163117.16269-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 31/37] hw/timer/nrf51_timer: Add nRF51 Timer peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz This patch adds the model for the nRF51 timer peripheral. Currently, only the TIMER mode is implemented. Signed-off-by: Steffen G=C3=B6rtz Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-9-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/Makefile.objs | 1 + include/hw/timer/nrf51_timer.h | 80 +++++++ hw/timer/nrf51_timer.c | 393 +++++++++++++++++++++++++++++++++ hw/timer/trace-events | 5 + 4 files changed, 479 insertions(+) create mode 100644 include/hw/timer/nrf51_timer.h create mode 100644 hw/timer/nrf51_timer.c diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index b32194d153d..0e9a4530f84 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_IMX) +=3D imx_gpt.o common-obj-$(CONFIG_LM32) +=3D lm32_timer.o common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-rtc.o +common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_timer.o =20 obj-$(CONFIG_ALTERA_TIMER) +=3D altera_timer.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_mct.o diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h new file mode 100644 index 00000000000..85cad2300df --- /dev/null +++ b/include/hw/timer/nrf51_timer.h @@ -0,0 +1,80 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + sysbus irq + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef NRF51_TIMER_H +#define NRF51_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_TIMER "nrf51_soc.timer" +#define NRF51_TIMER(obj) OBJECT_CHECK(NRF51TimerState, (obj), TYPE_NRF51_T= IMER) + +#define NRF51_TIMER_REG_COUNT 4 + +#define NRF51_TIMER_TASK_START 0x000 +#define NRF51_TIMER_TASK_STOP 0x004 +#define NRF51_TIMER_TASK_COUNT 0x008 +#define NRF51_TIMER_TASK_CLEAR 0x00C +#define NRF51_TIMER_TASK_SHUTDOWN 0x010 +#define NRF51_TIMER_TASK_CAPTURE_0 0x040 +#define NRF51_TIMER_TASK_CAPTURE_3 0x04C + +#define NRF51_TIMER_EVENT_COMPARE_0 0x140 +#define NRF51_TIMER_EVENT_COMPARE_1 0x144 +#define NRF51_TIMER_EVENT_COMPARE_2 0x148 +#define NRF51_TIMER_EVENT_COMPARE_3 0x14C + +#define NRF51_TIMER_REG_SHORTS 0x200 +#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f +#define NRF51_TIMER_REG_INTENSET 0x304 +#define NRF51_TIMER_REG_INTENCLR 0x308 +#define NRF51_TIMER_REG_INTEN_MASK 0xf0000 +#define NRF51_TIMER_REG_MODE 0x504 +#define NRF51_TIMER_REG_MODE_MASK 0x01 +#define NRF51_TIMER_TIMER 0 +#define NRF51_TIMER_COUNTER 1 +#define NRF51_TIMER_REG_BITMODE 0x508 +#define NRF51_TIMER_REG_BITMODE_MASK 0x03 +#define NRF51_TIMER_WIDTH_16 0 +#define NRF51_TIMER_WIDTH_8 1 +#define NRF51_TIMER_WIDTH_24 2 +#define NRF51_TIMER_WIDTH_32 3 +#define NRF51_TIMER_REG_PRESCALER 0x510 +#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F +#define NRF51_TIMER_REG_CC0 0x540 +#define NRF51_TIMER_REG_CC3 0x54C + +typedef struct NRF51TimerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + QEMUTimer timer; + int64_t timer_start_ns; + int64_t update_counter_ns; + uint32_t counter; + + bool running; + + uint8_t events_compare[NRF51_TIMER_REG_COUNT]; + uint32_t cc[NRF51_TIMER_REG_COUNT]; + uint32_t shorts; + uint32_t inten; + uint32_t mode; + uint32_t bitmode; + uint32_t prescaler; + +} NRF51TimerState; + + +#endif diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c new file mode 100644 index 00000000000..0c90662896e --- /dev/null +++ b/hw/timer/nrf51_timer.c @@ -0,0 +1,393 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * Copyright (c) 2019 Red Hat, Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/arm/nrf51.h" +#include "hw/timer/nrf51_timer.h" +#include "trace.h" + +#define TIMER_CLK_FREQ 16000000UL + +static uint32_t const bitwidths[] =3D {16, 8, 24, 32}; + +static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns) +{ + uint32_t freq =3D TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ns, freq, NANOSECONDS_PER_SECOND); +} + +static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks) +{ + uint32_t freq =3D TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ticks, NANOSECONDS_PER_SECOND, freq); +} + +/* Returns number of ticks since last call */ +static uint32_t update_counter(NRF51TimerState *s, int64_t now) +{ + uint32_t ticks =3D ns_to_ticks(s, now - s->update_counter_ns); + + s->counter =3D (s->counter + ticks) % BIT(bitwidths[s->bitmode]); + s->update_counter_ns =3D now; + return ticks; +} + +/* Assumes s->counter is up-to-date */ +static void rearm_timer(NRF51TimerState *s, int64_t now) +{ + int64_t min_ns =3D INT64_MAX; + size_t i; + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + int64_t delta_ns; + + if (s->events_compare[i]) { + continue; /* already expired, ignore it for now */ + } + + if (s->cc[i] <=3D s->counter) { + delta_ns =3D ticks_to_ns(s, BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]); + } else { + delta_ns =3D ticks_to_ns(s, s->cc[i] - s->counter); + } + + if (delta_ns < min_ns) { + min_ns =3D delta_ns; + } + } + + if (min_ns !=3D INT64_MAX) { + timer_mod_ns(&s->timer, now + min_ns); + } +} + +static void update_irq(NRF51TimerState *s) +{ + bool flag =3D false; + size_t i; + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + flag |=3D s->events_compare[i] && extract32(s->inten, 16 + i, 1); + } + qemu_set_irq(s->irq, flag); +} + +static void timer_expire(void *opaque) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t cc_remaining[NRF51_TIMER_REG_COUNT]; + bool should_stop =3D false; + uint32_t ticks; + size_t i; + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (s->cc[i] > s->counter) { + cc_remaining[i] =3D s->cc[i] - s->counter; + } else { + cc_remaining[i] =3D BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]; + } + } + + ticks =3D update_counter(s, now); + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (cc_remaining[i] <=3D ticks) { + s->events_compare[i] =3D 1; + + if (s->shorts & BIT(i)) { + s->timer_start_ns =3D now; + s->update_counter_ns =3D s->timer_start_ns; + s->counter =3D 0; + } + + should_stop |=3D s->shorts & BIT(i + 8); + } + } + + update_irq(s); + + if (should_stop) { + s->running =3D false; + timer_del(&s->timer); + } else { + rearm_timer(s, now); + } +} + +static void counter_compare(NRF51TimerState *s) +{ + uint32_t counter =3D s->counter; + size_t i; + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (counter =3D=3D s->cc[i]) { + s->events_compare[i] =3D 1; + + if (s->shorts & BIT(i)) { + s->counter =3D 0; + } + } + } +} + +static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int= size) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + r =3D s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4= ]; + break; + case NRF51_TIMER_REG_SHORTS: + r =3D s->shorts; + break; + case NRF51_TIMER_REG_INTENSET: + r =3D s->inten; + break; + case NRF51_TIMER_REG_INTENCLR: + r =3D s->inten; + break; + case NRF51_TIMER_REG_MODE: + r =3D s->mode; + break; + case NRF51_TIMER_REG_BITMODE: + r =3D s->bitmode; + break; + case NRF51_TIMER_REG_PRESCALER: + r =3D s->prescaler; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + r =3D s->cc[(offset - NRF51_TIMER_REG_CC0) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_timer_read(offset, r, size); + + return r; +} + +static void nrf51_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + size_t idx; + + trace_nrf51_timer_write(offset, value, size); + + switch (offset) { + case NRF51_TIMER_TASK_START: + if (value =3D=3D NRF51_TRIGGER_TASK && s->mode =3D=3D NRF51_TIMER_= TIMER) { + s->running =3D true; + s->timer_start_ns =3D now - ticks_to_ns(s, s->counter); + s->update_counter_ns =3D s->timer_start_ns; + rearm_timer(s, now); + } + break; + case NRF51_TIMER_TASK_STOP: + case NRF51_TIMER_TASK_SHUTDOWN: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->running =3D false; + timer_del(&s->timer); + } + break; + case NRF51_TIMER_TASK_COUNT: + if (value =3D=3D NRF51_TRIGGER_TASK && s->mode =3D=3D NRF51_TIMER_= COUNTER) { + s->counter =3D (s->counter + 1) % BIT(bitwidths[s->bitmode]); + counter_compare(s); + } + break; + case NRF51_TIMER_TASK_CLEAR: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->timer_start_ns =3D now; + s->update_counter_ns =3D s->timer_start_ns; + s->counter =3D 0; + if (s->running) { + rearm_timer(s, now); + } + } + break; + case NRF51_TIMER_TASK_CAPTURE_0 ... NRF51_TIMER_TASK_CAPTURE_3: + if (value =3D=3D NRF51_TRIGGER_TASK) { + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + + idx =3D (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4; + s->cc[idx] =3D s->counter; + } + break; + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + if (value =3D=3D NRF51_EVENT_CLEAR) { + s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4] = =3D 0; + + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + } + break; + case NRF51_TIMER_REG_SHORTS: + s->shorts =3D value & NRF51_TIMER_REG_SHORTS_MASK; + break; + case NRF51_TIMER_REG_INTENSET: + s->inten |=3D value & NRF51_TIMER_REG_INTEN_MASK; + break; + case NRF51_TIMER_REG_INTENCLR: + s->inten &=3D ~(value & NRF51_TIMER_REG_INTEN_MASK); + break; + case NRF51_TIMER_REG_MODE: + s->mode =3D value; + break; + case NRF51_TIMER_REG_BITMODE: + if (s->mode =3D=3D NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of BITMODE while timer is runnin= g\n", + __func__); + } + s->bitmode =3D value & NRF51_TIMER_REG_BITMODE_MASK; + break; + case NRF51_TIMER_REG_PRESCALER: + if (s->mode =3D=3D NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of PRESCALER while timer is running\= n", + __func__); + } + s->prescaler =3D value & NRF51_TIMER_REG_PRESCALER_MASK; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + if (s->running) { + timer_expire(s); /* update counter */ + } + + idx =3D (offset - NRF51_TIMER_REG_CC0) / 4; + s->cc[idx] =3D value % BIT(bitwidths[s->bitmode]); + + if (s->running) { + rearm_timer(s, now); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops =3D { + .read =3D nrf51_timer_read, + .write =3D nrf51_timer_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void nrf51_timer_init(Object *obj) +{ + NRF51TimerState *s =3D NRF51_TIMER(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &rng_ops, s, + TYPE_NRF51_TIMER, NRF51_TIMER_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, timer_expire, s); +} + +static void nrf51_timer_reset(DeviceState *dev) +{ + NRF51TimerState *s =3D NRF51_TIMER(dev); + + timer_del(&s->timer); + s->timer_start_ns =3D 0x00; + s->update_counter_ns =3D 0x00; + s->counter =3D 0x00; + s->running =3D false; + + memset(s->events_compare, 0x00, sizeof(s->events_compare)); + memset(s->cc, 0x00, sizeof(s->cc)); + + s->shorts =3D 0x00; + s->inten =3D 0x00; + s->mode =3D 0x00; + s->bitmode =3D 0x00; + s->prescaler =3D 0x00; +} + +static int nrf51_timer_post_load(void *opaque, int version_id) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + + if (s->running && s->mode =3D=3D NRF51_TIMER_TIMER) { + timer_expire(s); + } + return 0; +} + +static const VMStateDescription vmstate_nrf51_timer =3D { + .name =3D TYPE_NRF51_TIMER, + .version_id =3D 1, + .post_load =3D nrf51_timer_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_TIMER(timer, NRF51TimerState), + VMSTATE_INT64(timer_start_ns, NRF51TimerState), + VMSTATE_INT64(update_counter_ns, NRF51TimerState), + VMSTATE_UINT32(counter, NRF51TimerState), + VMSTATE_BOOL(running, NRF51TimerState), + VMSTATE_UINT8_ARRAY(events_compare, NRF51TimerState, + NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32_ARRAY(cc, NRF51TimerState, NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32(shorts, NRF51TimerState), + VMSTATE_UINT32(inten, NRF51TimerState), + VMSTATE_UINT32(mode, NRF51TimerState), + VMSTATE_UINT32(bitmode, NRF51TimerState), + VMSTATE_UINT32(prescaler, NRF51TimerState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nrf51_timer_reset; + dc->vmsd =3D &vmstate_nrf51_timer; +} + +static const TypeInfo nrf51_timer_info =3D { + .name =3D TYPE_NRF51_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51TimerState), + .instance_init =3D nrf51_timer_init, + .class_init =3D nrf51_timer_class_init +}; + +static void nrf51_timer_register_types(void) +{ + type_register_static(&nrf51_timer_info); +} + +type_init(nrf51_timer_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 75bd3b1042a..0144a68951c 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -72,3 +72,8 @@ sun4v_rtc_write(uint64_t addr, uint64_t value) "write: ad= dr 0x%" PRIx64 " value =20 # hw/timer/xlnx-zynqmp-rtc.c xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, i= nt sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" + +# hw/timer/nrf51_timer.c +nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr = 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write add= r 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.31.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nSkm073Bx3v9fUPp9jrgyRE1qp1za0Zg46AppemHHTE=; b=EHSyO3wB6b4KeEEYHTGvq33+JEJ0bLd6RtOHBTYvQOtATdQ55d7eFaJLtSgRqlzH8X nvRxBzw30ftKSHis1niXmtzIjAbxcm2kOQcY4Q9Nauneah4r6QRMY8BhAz974D1z/WCF wfhi+DMpWyfS2bv+iyxNoFkKpRT5KJLUrQLtk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nSkm073Bx3v9fUPp9jrgyRE1qp1za0Zg46AppemHHTE=; b=Iq311QciDiByEJggu/Vb6tLI+AR6N28UXr6nLRwb0wWlev8mZjLGGRUyE/F1cfze2a qKJ4NicaVZZE7TFugxR3u1uGU4kUYRgUIaXAt1Cl31fn71nwBezMBIadwcU2g7n1UdVU HTgDpzw1U+zJREMudvIcYZnLes2895kBXtj+byDEOKP0Rlk4BEJ7OxnI7gXgxapkWRR8 eqPVGae8egK2oXNhVJhOeNn0Kj/IFPUOPqNuG1jaKOxl8wa2YBTUSk6vKm2Ymyzfrs17 ug1qaH5Olt4Ro1qkAUuG4Ev3YHZRXMOLAsWpkDMY8e+GRT25HjSohTjg0+JwejE40uui 7q1w== X-Gm-Message-State: AJcUukc4O/Sf76gaLLJOco1PpfYj74X79fM+rRexfiKjG68IBSFlk9Tc oUgtBhTwQcOMLxKpW4TxOcWJoXV4hgeC/g== X-Google-Smtp-Source: ALg8bN77Rn7q21ijy+t7nhSJ5/1/ri+WXxZhD8tla0Bg/+TBnSBJQ1x5iFYnd+1/KskOqxsjv7BiUQ== X-Received: by 2002:adf:8323:: with SMTP id 32mr50251797wrd.176.1546878720059; Mon, 07 Jan 2019 08:32:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:12 +0000 Message-Id: <20190107163117.16269-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 32/37] arm: Instantiate NRF51 Timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-10-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 4 ++++ hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 84e0278881b..39e613e1c97 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -15,11 +15,14 @@ #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) =20 +#define NRF51_NUM_TIMERS 3 + typedef struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -30,6 +33,7 @@ typedef struct NRF51State { NRF51UARTState uart; NRF51RNGState rng; NRF51GPIOState gpio; + NRF51TimerState timer[NRF51_NUM_TIMERS]; =20 MemoryRegion iomem; MemoryRegion sram; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index db817fe5064..ef70bd62fa4 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -39,6 +39,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) NRF51State *s =3D NRF51_SOC(dev_soc); MemoryRegion *mr; Error *err =3D NULL; + uint8_t i =3D 0; + hwaddr base_addr =3D 0; =20 if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -112,6 +114,22 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) /* Pass all GPIOs to the SOC layer so they are available to the board = */ qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); =20 + /* TIMER */ + for (i =3D 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &= err); + if (err) { + error_propagate(errp, err); + return; + } + + base_addr =3D NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(base_addr))); + } + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -122,6 +140,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) =20 static void nrf51_soc_init(Object *obj) { + uint8_t i =3D 0; + NRF51State *s =3D NRF51_SOC(obj); =20 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); @@ -142,6 +162,12 @@ static void nrf51_soc_init(Object *obj) =20 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); + + for (i =3D 0; i < NRF51_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_NRF51_TIMER); + + } } =20 static Property nrf51_soc_properties[] =3D { --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3nnR4nEBbhqKliNZdMczAgOP+r6YxxrbRQTA/sysIkQ=; b=e1EuNChTkWtKpRHsUD8O4470vaWtCPG7XF1kn2VvgOS8KtqUAj/IInMD52jiiIEA/h 534FAYBNvkg49r8CpFlg8a5tCF590iQIzsLr43MiE6awJtZCC5UD/mkXObPC7xeaZ/xR 5duz0TKR11KvZ8j6nMAfR5wQTentYkhHGurtM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3nnR4nEBbhqKliNZdMczAgOP+r6YxxrbRQTA/sysIkQ=; b=N7bzmhCqfgSEj6jsZOqWlybV5k6HI+hsaqRR2k0Ws5i9MJKGt/jnBXywjm0jzJP3zj iA7mkmraONPdoq8z9Q5TuC4u1yKj5RV9vf/cC6VAvfnciRaTzqljFYuE18Goh6epFHnT yiY++fm0KuhHQ2bb4nHNJgYh3TgSPRf9Ksd85eYNYyX1wxZZZtT72CfGgUvhtpgJdRkm zaUEF1ZwCeaw9U6W+zoyLzeJ0gZk4sB6uE2I+D1C+w+e6t+r7eBCaYr4/feRntLxaYOo 1yskCeMBesGoaD/pwYl4EyfbLnZ87dvLop8bX5fax8CHNlgyM9f/m/2ZaKjDYki/X7UN 6adQ== X-Gm-Message-State: AJcUukdv2gLyByDDDlwOpPPTzw6exfBoySCc0YrHD4Zt9gxU7Zwgjk7T YTQvtpGYHEVTywC7ph6mq/xNahqt+XmIeg== X-Google-Smtp-Source: ALg8bN6RlcvZ/uORk12qH2CAf4YAeNuAvlibwt4ZAxmBCDC1/jQRLtACE2l1XEnrc1j/EYcKIX6dQA== X-Received: by 2002:a05:6000:12c4:: with SMTP id l4mr50624622wrx.134.1546878721254; Mon, 07 Jan 2019 08:32:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:13 +0000 Message-Id: <20190107163117.16269-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 33/37] tests/microbit-test: Add Tests for nRF51 Timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Basic tests for nRF51 Timer Peripheral. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-11-stefanha@redhat.com Signed-off-by: Peter Maydell --- tests/microbit-test.c | 95 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index f0a180cbc6f..0c125535f64 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -20,6 +20,7 @@ =20 #include "hw/arm/nrf51.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" =20 static void test_nrf51_gpio(void) { @@ -143,6 +144,99 @@ static void test_nrf51_gpio(void) qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); } =20 +static void timer_task(hwaddr task) +{ + writel(NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); +} + +static void timer_clear_event(hwaddr event) +{ + writel(NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); +} + +static void timer_set_bitmode(uint8_t mode) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); +} + +static void timer_set_prescaler(uint8_t prescaler) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, prescaler); +} + +static void timer_set_cc(size_t idx, uint32_t value) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, value); +} + +static void timer_assert_events(uint32_t ev0, uint32_t ev1, uint32_t ev2, + uint32_t ev3) +{ + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_0) =3D=3D = ev0); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_1) =3D=3D = ev1); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_2) =3D=3D = ev2); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_3) =3D=3D = ev3); +} + +static void test_nrf51_timer(void) +{ + uint32_t steps_to_overflow =3D 408; + + /* Compare Match */ + timer_task(NRF51_TIMER_TASK_STOP); + timer_task(NRF51_TIMER_TASK_CLEAR); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + + timer_set_bitmode(NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ + timer_set_prescaler(0); + /* Swept over in first step */ + timer_set_cc(0, 2); + /* Barely miss on first step */ + timer_set_cc(1, 162); + /* Spot on on third step */ + timer_set_cc(2, 480); + + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_START); + clock_step(10000); + timer_assert_events(1, 0, 0, 0); + + /* Swept over on first overflow */ + timer_set_cc(3, 114); + + clock_step(10000); + timer_assert_events(1, 1, 0, 0); + + clock_step(10000); + timer_assert_events(1, 1, 1, 0); + + /* Wrap time until internal counter overflows */ + while (steps_to_overflow--) { + timer_assert_events(1, 1, 1, 0); + clock_step(10000); + } + + timer_assert_events(1, 1, 1, 1); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_STOP); + + /* Test Proposal: Stop/Shutdown */ + /* Test Proposal: Shortcut Compare -> Clear */ + /* Test Proposal: Shortcut Compare -> Stop */ + /* Test Proposal: Counter Mode */ +} + int main(int argc, char **argv) { int ret; @@ -152,6 +246,7 @@ int main(int argc, char **argv) global_qtest =3D qtest_initf("-machine microbit"); =20 qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); =20 ret =3D g_test_run(); =20 --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4hneVY5bvDrk+gY/Cf1fDIxMbZ+fK4EQN84PywEKNfg=; b=bDwTanHiTO91EhSbmndRgY/mlaIuLOlFRNNGG/GJ/CfmzF7SqTkCML7B3MZsUtjLTe WY4HedlIdsFjArNxtzmDAYIOjYw4iV7bC0pid6ikm2uK4JdA7qdxFLCpHOf7e8oJY4dH pHJ7trxdZY+mpP70duGPPJVUJDiqR7lNk+OhY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4hneVY5bvDrk+gY/Cf1fDIxMbZ+fK4EQN84PywEKNfg=; b=Iy5RGw4o6ZsArVod33H1qQZCuIh5SsRHJivryKXZCUBAjab/e1Ug3c/IXfFsUu0Ndh etuw21J7JeAZv8GOUer5GjXcsT9lBW9skLiP8R4VSZOWKN6l35sqsdDAdbAg1qa+IqNh CJVdB3L3/CARgKnYCGiqhTNk189yOgS7nDXd01fN7StLBJ8SxcwwIXXinpOAtHG2WpgN 17lhp9X+XuntDPo8Csmdm3irq6bDu0caQ973sgDPXBdtmbA3I6eSYvTDnvgbGcvJveni TFzr4ZTWdlQpvSIvLHZe9grMavuV/hA0WBdU+N0JBK4JwxUB7yGYMGhgZrmTD2gvIrDq GGeA== X-Gm-Message-State: AJcUukdMOM571Gte310M+q8PWHgy22udnhElaIhwul5LyMiWIeaTUSFt JF2QdQiruDgobnmCly/Ek0jY6exrVvrakQ== X-Google-Smtp-Source: ALg8bN5QL7OYBxUo5HdFipMNhiZu5dL1qihbOqCgvLguaozX/7YwoMuWkXu03dlXbhPBbL33GEoCBw== X-Received: by 2002:a1c:f319:: with SMTP id q25mr9446718wmq.151.1546878722571; Mon, 07 Jan 2019 08:32:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:14 +0000 Message-Id: <20190107163117.16269-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 34/37] arm: Add Clock peripheral stub to NRF51 SOC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190103091119.9367-12-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 1 + hw/arm/nrf51_soc.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 39e613e1c97..e06f0304b48 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -38,6 +38,7 @@ typedef struct NRF51State { MemoryRegion iomem; MemoryRegion sram; MemoryRegion flash; + MemoryRegion clock; =20 uint32_t sram_size; uint32_t flash_size; diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index ef70bd62fa4..1630c275940 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -34,6 +34,26 @@ =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) =20 +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]= \n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops =3D { + .read =3D clock_read, + .write =3D clock_write +}; + + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); @@ -130,6 +150,12 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) BASE_TO_IRQ(base_addr))); } =20 + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, + NRF51_IOMEM_BASE, &s->clock, -1); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546879455095429.7126725694767; Mon, 7 Jan 2019 08:44:15 -0800 (PST) Received: from localhost ([127.0.0.1]:45310 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggY0c-0006Ne-0Z for importer@patchew.org; Mon, 07 Jan 2019 11:44:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXpR-0005jc-9X for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXpP-0003Gq-7H for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:41 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:42854) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXpN-0002X6-95 for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:38 -0500 Received: by mail-wr1-x434.google.com with SMTP id q18so1049192wrx.9 for ; Mon, 07 Jan 2019 08:32:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4t2j3JlI3wCS/gpNiHag2Gqqa/xd788Q4yu+HY0+oFg=; b=S2dKX0rG9bBZGfYTRP5EPiT+G9Xa/k6L47Ny7ttoUunw9oJI+02JfQArwShtbFzjbG Mm3/gyRSoeccSUHc/+EhhjkziR6I7ZBgAB3Il1uP0xz50JIRlHdASPM93UZS8uQszHeE ux9U72mXhHWGru4ylstyaCK31eIQ6SFvBXIuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4t2j3JlI3wCS/gpNiHag2Gqqa/xd788Q4yu+HY0+oFg=; b=c7Bx8XkHtcUz3vIIl95QAP/3ejzVXI+h+ihNBcG1ke9dyN010E7LaTEPhtPMlFedDi iArK+s9PP07p4hL+6wK47bzr63C5eU9Z9g29PX1L47eGg2PUylaEjzFnlR4fJu5r1fKi mOHuFu1gdz6p9FeXDx2jWjzuiHBUvAl5y2OPVgAngoSV1OltWHtVvayXHfFp/7+dYR0E QlaALKv7yAxMRklYRoSIRWmCu1RbEB/3jHmZEXbXSgJuWF1pFf8Yk7WZ3AYQRzI1jhXC OawsHq1IotjDu5P8qKgM4Da78uoNTlR7JneL6ZtDkx4xyV6YQdF92mAjtJ7Q0VZr0N0G zhtQ== X-Gm-Message-State: AJcUukeUOD4GdfEIC47V3krEkndqXXn/5+NIFHgNnV+TGYUsYUPU/fPC JLILe3cOuwnxAZL44vAcW5xJs1Y6j/RnJQ== X-Google-Smtp-Source: ALg8bN5AJtgXoFTbHxNINqm9PKc5SIL8vMctu2YB3iWUDolOzsQcJUuZF4NJRHeC8l6ZCouo2H61XQ== X-Received: by 2002:a5d:6244:: with SMTP id m4mr41724613wrv.314.1546878723673; Mon, 07 Jan 2019 08:32:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:15 +0000 Message-Id: <20190107163117.16269-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 35/37] target/arm: Emit barriers for A32/T32 load-acquire/store-release insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Now that MTTCG is here, the comment in the 32-bit Arm decoder that "Since the emulation does not have barriers, the acquire/release semantics need no special handling" is no longer true. Emit the correct barriers for the load-acquire/store-release insns, as we already do in the A64 decoder. Signed-off-by: Peter Maydell Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ed3db0c3946..66cf28c8cbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,6 +9733,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) rd =3D (insn >> 12) & 0xf; if (insn & (1 << 23)) { /* load/store exclusive */ + bool is_ld =3D extract32(insn, 20, 1); + bool is_lasr =3D !extract32(insn, 8, 1); int op2 =3D (insn >> 8) & 3; op1 =3D (insn >> 21) & 0x3; =20 @@ -9760,11 +9762,12 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) addr =3D tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); =20 - /* Since the emulation does not have barriers, - the acquire/release semantics need no special - handling */ + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + if (op2 =3D=3D 0) { - if (insn & (1 << 20)) { + if (is_ld) { tmp =3D tcg_temp_new_i32(); switch (op1) { case 0: /* lda */ @@ -9810,7 +9813,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { switch (op1) { case 0: /* ldrex */ gen_load_exclusive(s, rd, 15, addr, 2); @@ -9847,6 +9850,10 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } else if ((insn & 0x00300f00) =3D=3D 0) { /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx * - SWP, SWPB @@ -10862,6 +10869,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_gen_addi_i32(tmp, tmp, s->pc); store_reg(s, 15, tmp); } else { + bool is_lasr =3D false; + bool is_ld =3D extract32(insn, 20, 1); int op2 =3D (insn >> 6) & 0x3; op =3D (insn >> 4) & 0x3; switch (op2) { @@ -10883,12 +10892,18 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) case 3: /* Load-acquire/store-release exclusive */ ARCH(8); + is_lasr =3D true; break; } + + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + addr =3D tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); if (!(op2 & 1)) { - if (insn & (1 << 20)) { + if (is_ld) { tmp =3D tcg_temp_new_i32(); switch (op) { case 0: /* ldab */ @@ -10927,12 +10942,16 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { gen_load_exclusive(s, rs, rd, addr, op); } else { gen_store_exclusive(s, rm, rs, rd, addr, op); } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } } else { /* Load/store multiple, RFE, SRS. */ --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15468804015290.5594474806221115; Mon, 7 Jan 2019 09:00:01 -0800 (PST) Received: from localhost ([127.0.0.1]:49143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYFh-0001xo-Hf for importer@patchew.org; Mon, 07 Jan 2019 11:59:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXpT-0005lt-Gy for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXpR-0003Jt-Bx for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:43 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:34557) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXpP-0002Ya-9X for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:41 -0500 Received: by mail-wm1-x330.google.com with SMTP id y185so6501230wmd.1 for ; Mon, 07 Jan 2019 08:32:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sV9hC86VR1BwwXtur8ugDHh5zaLnT6kGUvr9DsHA44A=; b=MRmnZ7//wQxNBmlC1nh8DnVtqFq7gX27iH08KtlUOK8UaBzZFMmGd2gCleuVaPfm2h Spxernas4aGlf4LESatRr2E7Sr51wvEfdw1xXIBiOdHWy8XRTb+Y0+45l4S7J7/9LxLb ePbejMTlvxYUn5Kuw9L9IVZ1Vx8wOOb92FF9U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sV9hC86VR1BwwXtur8ugDHh5zaLnT6kGUvr9DsHA44A=; b=Z2s1JD1WnSkcHE4fXZIC9g6MrUmFaM5lCLm+fy8FaZN81eBTILa3ZgyblK9KatnBNW J8DEspuDan0W3B3ZZrmC4TRYUseeTGY+SITLhtKBixjRBfa2YjJPXvJr5nIq0bTp6+9Y hch2CaEbfD5EpTDHnYp28JNTBUmEESsT3m7ztW3gXRz8Cvrl2FupwK676i+kA6gXBHuD DLErXZs+5gV7Boz52TmKw78ilcK/+TjCQx8NC6o7Hc58dTZ0lAmRHVT0eLeGbxMLLIRf paQWSEfKNsaGjHzevgLt4EaMBYN4UdlyPL/2Zz07sI0+vU5iadw2VJ0PZTeSvUtwPAfC HDBQ== X-Gm-Message-State: AJcUukeMIURQ8flPwQh/htlPQ1IYgaVJCoNUrUN/IX9XavLfElEvfqwv 3WQG/Q/KiolR9mXErBMm+98pTHCANs8XUQ== X-Google-Smtp-Source: ALg8bN4dnYdbSXANEgEoNMVvzgP072QhoIjLsJUlYFi2li9VGtct6Iu4MB7H+BKVJA6xiqikUxuR+g== X-Received: by 2002:a1c:4c10:: with SMTP id z16mr9666886wmf.117.1546878724629; Mon, 07 Jan 2019 08:32:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:16 +0000 Message-Id: <20190107163117.16269-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 36/37] hw/misc/tz-mpc: Fix value of BLK_MAX register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In the TZ Memory Protection Controller, the BLK_MAX register is supposed to return the maximum permitted value of the BLK_IDX register. Our implementation incorrectly returned max+1 (ie the total number of valid index values, since BLK_IDX is zero-based). Correct this off-by-one error. Since we consistently initialize and use s->blk_max throughout the implementation as the 'size' of the LUT, just adjust the value we return when the guest reads the BLK_MAX register, rather than trying to change the semantics of the s->blk_max internal struct field. Fixes: https://bugs.launchpad.net/qemu/+bug/1806824 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181213183249.3468-1-peter.maydell@linaro.org --- hw/misc/tz-mpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index fb48a1540b9..9a84be75ed6 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -150,7 +150,7 @@ static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr= addr, r =3D s->ctrl; break; case A_BLK_MAX: - r =3D s->blk_max; + r =3D s->blk_max - 1; break; case A_BLK_CFG: /* We are never in "init in progress state", so this just indicates --=20 2.19.2 From nobody Mon May 13 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1546881212093112.72590044973595; Mon, 7 Jan 2019 09:13:32 -0800 (PST) Received: from localhost ([127.0.0.1]:51959 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggYSw-0004JO-Et for importer@patchew.org; Mon, 07 Jan 2019 12:13:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggXpO-0005gW-4K for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggXpK-00038p-3B for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:35 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:36299) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ggXpG-0002a2-5w for qemu-devel@nongnu.org; Mon, 07 Jan 2019 11:32:32 -0500 Received: by mail-wr1-x443.google.com with SMTP id u4so1091630wrp.3 for ; Mon, 07 Jan 2019 08:32:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j14sm46039759wrv.96.2019.01.07.08.32.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jan 2019 08:32:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cDFB1Ur65EARuRk/dPzzE6tv5eNAyb1OwUrHB1LwiDY=; b=DbdHnwn2NB2Wv4Rxick+QBawJM7fCbBdQleBqfsoAbSAQcARf0aTjjxyEx37gOQX32 XM1V4WiLHQQXOLBQc+Z77Y+lrJ44V18cN8K5MAXhSD/vGYJ8mME9kpUwxNOqdQpnLIPF QuSZiXg3tyC7EL/KDBPBx84xjKs1J5N3/+ZOg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cDFB1Ur65EARuRk/dPzzE6tv5eNAyb1OwUrHB1LwiDY=; b=ec2lbuGusiybgJlUB253ceRdCfHWkMr58sAMG6sM2WolLlaQ7iZFFFNdIuj5fgr7GG yP6knYzFdLnhSyjnPoyhrXRw/NPFCv1swSdD/2pHWtYw8Xm+A83CDhIK1i03+mwkjF65 T6ygkmSID64E3SywIMMegwMWe4xFlDtS/1o8NMAS6F/W5HATJYK6ycu1I8r1rgtuPNqh Jd3RqasskusGYkVttLyuCvScLlQ3OTlvzTZ3TPblLm7+4AweylRd+m5LgbrRLz6ANDlT HDxkG/CszFfpjIxSz6leiXydZ6rUfi9Ge0O/p3yzBVZgmXFxizPezicNbaJ3OQsmVZdF tREQ== X-Gm-Message-State: AJcUukfV2RstSyCTuFVVi+rYVdW+ixKLqzSJyHyAlp/Qt0dHazi253R2 3njHas8Rjo8dNrvhEAG6lqCD3EuOcBL5Xw== X-Google-Smtp-Source: ALg8bN4tfbkjr8v29EYueJnHSj46FjuAu6XqIiSWDe6xHK+7hNXk1jOvUwlzPfkodyvoie8hzcvrUA== X-Received: by 2002:adf:9c8a:: with SMTP id d10mr28094632wre.244.1546878725943; Mon, 07 Jan 2019 08:32:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 7 Jan 2019 16:31:17 +0000 Message-Id: <20190107163117.16269-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190107163117.16269-1-peter.maydell@linaro.org> References: <20190107163117.16269-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 37/37] Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Nick Hudson noload kernels are loaded with the u-boot image header and as a result the header size needs adding to the entry point. Fake up a hdr so the kernel image is loaded at the right address and the entry point is adjusted appropriately. The default location for the uboot file is 32MiB above bottom of DRAM. This matches the recommendation in Documentation/arm/Booting. Clarify the load_uimage API to state the passing of a load address when an image doesn't specify one, or when loading a ramdisk is expected. Adjust callers of load_uimage, etc. Signed-off-by: Nick Hudson Message-id: 11488a08-1fe0-a278-2210-deb64731107f@gmx.co.uk Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/core/uboot_image.h | 1 + include/hw/loader.h | 7 ++++++- hw/arm/boot.c | 8 +++++--- hw/core/loader.c | 19 ++++++++++++++++--- hw/microblaze/boot.c | 2 +- hw/nios2/boot.c | 2 +- hw/ppc/e500.c | 1 + hw/ppc/ppc440_bamboo.c | 2 +- hw/ppc/sam460ex.c | 2 +- 9 files changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h index 34c11a70a67..608022de6ec 100644 --- a/hw/core/uboot_image.h +++ b/hw/core/uboot_image.h @@ -124,6 +124,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image (noload) */ =20 /* * Compression Types diff --git a/include/hw/loader.h b/include/hw/loader.h index 0a0ad808ea3..de8a29603b0 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -175,10 +175,15 @@ void load_elf_hdr(const char *filename, void *hdr, bo= ol *is64, Error **errp); int load_aout(const char *filename, hwaddr addr, int max_sz, int bswap_needed, hwaddr target_page_size); =20 +#define LOAD_UIMAGE_LOADADDR_INVALID (-1) + /** load_uimage_as: * @filename: Path of uimage file * @ep: Populated with program entry point. Ignored if NULL. - * @loadaddr: Populated with the load address. Ignored if NULL. + * @loadaddr: load address if none specified in the image or when loading a + * ramdisk. Populated with the load address. Ignored if NULL or + * LOAD_UIMAGE_LOADADDR_INVALID (images which do not specify a = load + * address will not be loadable). * @is_linux: Is set to true if the image loaded is Linux. Ignored if NULL. * @translate_fn: optional function to translate load addresses * @translate_opaque: opaque data passed to @translate_fn diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 94fce128028..c7a67af7a97 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -30,8 +30,9 @@ * Documentation/arm/Booting and Documentation/arm64/booting.txt * They have different preferred image load offsets from system RAM base. */ -#define KERNEL_ARGS_ADDR 0x100 -#define KERNEL_LOAD_ADDR 0x00010000 +#define KERNEL_ARGS_ADDR 0x100 +#define KERNEL_NOLOAD_ADDR 0x02000000 +#define KERNEL_LOAD_ADDR 0x00010000 #define KERNEL64_LOAD_ADDR 0x00080000 =20 #define ARM64_TEXT_OFFSET_OFFSET 8 @@ -1082,7 +1083,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) } entry =3D elf_entry; if (kernel_size < 0) { - kernel_size =3D load_uimage_as(info->kernel_filename, &entry, NULL, + uint64_t loadaddr =3D info->loader_start + KERNEL_NOLOAD_ADDR; + kernel_size =3D load_uimage_as(info->kernel_filename, &entry, &loa= daddr, &is_linux, NULL, NULL, as); } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { diff --git a/hw/core/loader.c b/hw/core/loader.c index fa41842280a..c7182dfa64b 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -613,13 +613,26 @@ static int load_uboot_image(const char *filename, hwa= ddr *ep, hwaddr *loadaddr, goto out; =20 if (hdr->ih_type !=3D image_type) { - fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type, - image_type); - goto out; + if (!(image_type =3D=3D IH_TYPE_KERNEL && + hdr->ih_type =3D=3D IH_TYPE_KERNEL_NOLOAD)) { + fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_= type, + image_type); + goto out; + } } =20 /* TODO: Implement other image types. */ switch (hdr->ih_type) { + case IH_TYPE_KERNEL_NOLOAD: + if (!loadaddr || *loadaddr =3D=3D LOAD_UIMAGE_LOADADDR_INVALID) { + fprintf(stderr, "this image format (kernel_noload) cannot be " + "loaded on this machine type"); + goto out; + } + + hdr->ih_load =3D *loadaddr + sizeof(*hdr); + hdr->ih_ep +=3D hdr->ih_load; + /* fall through */ case IH_TYPE_KERNEL: address =3D hdr->ih_load; if (translate_fn) { diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index 35bfeda7aa7..489ab839b7c 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -156,7 +156,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr = ddr_base, =20 /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr =3D LOAD_UIMAGE_LOADADDR_INVALID; =20 kernel_size =3D load_uimage(kernel_filename, &uentry, &loadadd= r, 0, NULL, NULL); diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index 4bb5b601d3a..ed5cb28e942 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -161,7 +161,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, =20 /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr =3D LOAD_UIMAGE_LOADADDR_INVALID; =20 kernel_size =3D load_uimage(kernel_filename, &uentry, &loadadd= r, 0, NULL, NULL); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b20fea0dfce..0581e9e3d4c 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -995,6 +995,7 @@ void ppce500_init(MachineState *machine) * Hrm. No ELF image? Try a uImage, maybe someone is giving us an * ePAPR compliant kernel */ + loadaddr =3D LOAD_UIMAGE_LOADADDR_INVALID; payload_size =3D load_uimage(filename, &bios_entry, &loadaddr, NUL= L, NULL, NULL); if (payload_size < 0) { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b8aa55d5266..fc061915887 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -179,7 +179,7 @@ static void bamboo_init(MachineState *machine) CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; - hwaddr loadaddr =3D 0; + hwaddr loadaddr =3D LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size =3D 0; DeviceState *dev; int success; diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4b051c0950a..84ea592749c 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -402,7 +402,7 @@ static void sam460ex_init(MachineState *machine) CPUPPCState *env; PPC4xxI2CState *i2c[2]; hwaddr entry =3D UBOOT_ENTRY; - hwaddr loadaddr =3D 0; + hwaddr loadaddr =3D LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size =3D 0; DeviceState *dev; SysBusDevice *sbdev; --=20 2.19.2