From nobody Thu Oct 2 10:13:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 154577186630947.5123204092813; Tue, 25 Dec 2018 13:04:26 -0800 (PST) Received: from localhost ([127.0.0.1]:43077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gbts8-0004Am-Cx for importer@patchew.org; Tue, 25 Dec 2018 16:04:16 -0500 Received: from eggs.gnu.org ([208.118.235.92]:49645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gbtkl-0004MN-JA for qemu-devel@nongnu.org; Tue, 25 Dec 2018 15:56:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gbtki-00074S-5B for qemu-devel@nongnu.org; Tue, 25 Dec 2018 15:56:39 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:37252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gbtkh-00073c-Vy for qemu-devel@nongnu.org; Tue, 25 Dec 2018 15:56:36 -0500 Received: by mail-pf1-x436.google.com with SMTP id y126so7080818pfb.4 for ; Tue, 25 Dec 2018 12:56:35 -0800 (PST) Received: from cloudburst.home (c211-28-135-144.sunsh3.vic.optusnet.com.au. [211.28.135.144]) by smtp.gmail.com with ESMTPSA id t21sm48501628pgg.24.2018.12.25.12.56.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Dec 2018 12:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bnSWepPpVuVUtley4KR6qFD+yjuup1LG9VJXZPML7WA=; b=e70911WFXcYxRdEZQYo0ZRP9bP8N2WdbrVDPBp5uFbcr701BypsJa0fQ6IbhihLJNo 7Meds6ZbUpgxRlF5n3V7CGuQGoZlTy9hIsaBU/ooYGIBWUlbMexZxMHnFxb7ZEDPT1YJ MoPsLSQXFJN6o4MmQ02hnCWm5sDA5RXBNPBao= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bnSWepPpVuVUtley4KR6qFD+yjuup1LG9VJXZPML7WA=; b=D7ka/KyN1JYC4fBmnROAiU5oWh5Qm6qStOxmezLbQH0tInpAG9q5CO6e7uVlcAWzR2 gkGXyIOlTuxx1OdhO2rRgwplbaMkQtMYRDys6JZVUwGRhi9X44HHVxaryVRGezoz/bb7 z62yWSojfP0q3q5O9Gna1uAmocx+0Q8vfx9yilL6RFCWI5ELrzjk3xLQJxQkkt/a1cTb Wc3TXRa9IoaTIFJLVyd9hioj719p4BgtgcgJbhgkmLa2ThbasWklmru875JS3Hfpdpvm B2EIU0xxuGvKpALdIZ3nVqw+8Zzho3D79YM220Bi0nc4tqNwFs1U2CYcWmc5iQHmiDy0 o5wg== X-Gm-Message-State: AA+aEWbOmAGgJ1/JjOUPPILTBAFMUtSc+O9hr4jylmlay71sqZKgQROr yRM3tyDCpr4MxwrrSGpIKAqnT2XffV4= X-Google-Smtp-Source: AFSGD/Xs0SkEAzRHqc91MAE5rG1W22nSD4DnNXI3xRbfBghHROt3FUODgIW3vOLU13oe0QhBypr5NA== X-Received: by 2002:a62:b24a:: with SMTP id x71mr18148585pfe.148.1545771394546; Tue, 25 Dec 2018 12:56:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:54:54 +1100 Message-Id: <20181225205529.10874-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Richard Henderson Message-Id: Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.inc.c | 168 +++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 6c969e3973..f853d01803 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -116,3 +116,171 @@ static const int tcg_target_call_oarg_regs[] =3D { TCG_REG_A0, TCG_REG_A1, }; + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_M12 0x800 + +static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + return sextract32(val, pos, len); + } else { + return sextract64(val, pos, len); + } +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType typ= e) +{ + switch (*ct_str++) { + case 'r': + ct->ct |=3D TCG_CT_REG; + ct->u.regs =3D 0xffffffff; + break; + case 'L': + /* qemu_ld/qemu_st constraint */ + ct->ct |=3D TCG_CT_REG; + ct->u.regs =3D 0xffffffff; + /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ +#if defined(CONFIG_SOFTMMU) + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); +#endif + break; + case 'I': + ct->ct |=3D TCG_CT_CONST_S12; + break; + case 'N': + ct->ct |=3D TCG_CT_CONST_N12; + break; + case 'M': + ct->ct |=3D TCG_CT_CONST_M12; + break; + case 'Z': + /* we can use a zero immediate as a zero register argument. */ + ct->ct |=3D TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct =3D arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val =3D=3D 0) { + return 1; + } + if ((ct & TCG_CT_CONST_S12) && val =3D=3D sextreg(val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_N12) && -val =3D=3D sextreg(-val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_M12) && val >=3D -0xfff && val <=3D 0xfff) { + return 1; + } + return 0; +} + +/* + * RISC-V Base ISA opcodes (IM) + */ + +typedef enum { + OPC_ADD =3D 0x33, + OPC_ADDI =3D 0x13, + OPC_AND =3D 0x7033, + OPC_ANDI =3D 0x7013, + OPC_AUIPC =3D 0x17, + OPC_BEQ =3D 0x63, + OPC_BGE =3D 0x5063, + OPC_BGEU =3D 0x7063, + OPC_BLT =3D 0x4063, + OPC_BLTU =3D 0x6063, + OPC_BNE =3D 0x1063, + OPC_DIV =3D 0x2004033, + OPC_DIVU =3D 0x2005033, + OPC_JAL =3D 0x6f, + OPC_JALR =3D 0x67, + OPC_LB =3D 0x3, + OPC_LBU =3D 0x4003, + OPC_LD =3D 0x3003, + OPC_LH =3D 0x1003, + OPC_LHU =3D 0x5003, + OPC_LUI =3D 0x37, + OPC_LW =3D 0x2003, + OPC_LWU =3D 0x6003, + OPC_MUL =3D 0x2000033, + OPC_MULH =3D 0x2001033, + OPC_MULHSU =3D 0x2002033, + OPC_MULHU =3D 0x2003033, + OPC_OR =3D 0x6033, + OPC_ORI =3D 0x6013, + OPC_REM =3D 0x2006033, + OPC_REMU =3D 0x2007033, + OPC_SB =3D 0x23, + OPC_SD =3D 0x3023, + OPC_SH =3D 0x1023, + OPC_SLL =3D 0x1033, + OPC_SLLI =3D 0x1013, + OPC_SLT =3D 0x2033, + OPC_SLTI =3D 0x2013, + OPC_SLTIU =3D 0x3013, + OPC_SLTU =3D 0x3033, + OPC_SRA =3D 0x40005033, + OPC_SRAI =3D 0x40005013, + OPC_SRL =3D 0x5033, + OPC_SRLI =3D 0x5013, + OPC_SUB =3D 0x40000033, + OPC_SW =3D 0x2023, + OPC_XOR =3D 0x4033, + OPC_XORI =3D 0x4013, + +#if TCG_TARGET_REG_BITS =3D=3D 64 + OPC_ADDIW =3D 0x1b, + OPC_ADDW =3D 0x3b, + OPC_DIVUW =3D 0x200503b, + OPC_DIVW =3D 0x200403b, + OPC_MULW =3D 0x200003b, + OPC_REMUW =3D 0x200703b, + OPC_REMW =3D 0x200603b, + OPC_SLLIW =3D 0x101b, + OPC_SLLW =3D 0x103b, + OPC_SRAIW =3D 0x4000501b, + OPC_SRAW =3D 0x4000503b, + OPC_SRLIW =3D 0x501b, + OPC_SRLW =3D 0x503b, + OPC_SUBW =3D 0x4000003b, +#else + /* Simplify code throughout by defining aliases for RV32. */ + OPC_ADDIW =3D OPC_ADDI, + OPC_ADDW =3D OPC_ADD, + OPC_DIVUW =3D OPC_DIVU, + OPC_DIVW =3D OPC_DIV, + OPC_MULW =3D OPC_MUL, + OPC_REMUW =3D OPC_REMU, + OPC_REMW =3D OPC_REM, + OPC_SLLIW =3D OPC_SLLI, + OPC_SLLW =3D OPC_SLL, + OPC_SRAIW =3D OPC_SRAI, + OPC_SRAW =3D OPC_SRA, + OPC_SRLIW =3D OPC_SRLI, + OPC_SRLW =3D OPC_SRL, + OPC_SUBW =3D OPC_SUB, +#endif + + OPC_FENCE =3D 0x0000000f, +} RISCVInsn; --=20 2.17.2