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[211.28.135.144]) by smtp.gmail.com with ESMTPSA id t21sm48501628pgg.24.2018.12.25.12.59.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Dec 2018 12:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rFyVT3+Q74xkj2Qe1vgfvSjqk0XbFRCtmL1wHv80Mks=; b=I9Q1OrMSXm4UVqn7Ig51ErgEaoaNugnsKCYG+37Huz5IcqU1C42vKA3gyXnEmQVK0S m6O20fWRURTlqs0juaQowc7vHILz5LDFuw3IUz180NuXkp+HoxoO3Z+h3yzl4Zv0MLTI Imuyuk8CjLvSTbbZ5Y/S/YQmiggiC1OA69BkI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rFyVT3+Q74xkj2Qe1vgfvSjqk0XbFRCtmL1wHv80Mks=; b=F4IkG2Xf1bkSTFAqIZANHQZ+2wXhMnGe+mZPzRFO74ZpIy8Qozfa3HxlAsELUZAMb6 /JKfTx8J6RjE+ye0k0GsMeWlP6jnUaZJBJpwcnB+DpI/Hdo3bTF69R8f6wgM3r1YQvGZ DtkNIL3C9kNJ/5AG2Wi5hBk/ktsX9aPUadHB49qvp0tRmGjdrpefaDa+pZ1B9cRQyEDP lWn5D6b1+N7vBRepETRlCz5xgD1az2IB89CcHzq4xaozedf2zb9PVn22pM1UJPDcINFr t5+TBrXLZsPyZ47ctYYEhCBThY7zCVTGJ5SE2YfHaPISjLVvbw56f0PkbWG5KFbTms3u DQgw== X-Gm-Message-State: AJcUukdYVmuPiuk0d6/DQlONvG9CdZJADxPNgV/n24wgWzfs/SzChQ1b z+/Sgg1yipXnKP8ms+mlF1VvyvMg7lw= X-Google-Smtp-Source: ALg8bN56ZtO1b4ZMxb57erF+49UypVVqnb+86tKywl3OhKFbLH47pp4N1KN5PXIeJHdw2pIXrvsmug== X-Received: by 2002:a17:902:3f81:: with SMTP id a1mr17267385pld.258.1545771557117; Tue, 25 Dec 2018 12:59:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:55:17 +1100 Message-Id: <20181225205529.10874-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This new argument will aid register allocation by indicating how the temporary will be used in future. If the preference cannot be satisfied, fall back to the constraints of the current insn. Short circuit the preference when it cannot be satisfied or if it does not further constrain the operation. With an eye toward optimizing function call sequences, optimize for the preferred_reg set containing a single register. For the moment, all users pass 0 for preference. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.c | 103 ++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 81 insertions(+), 22 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index d2be550ab4..210bd5c6b9 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1887,6 +1887,20 @@ static const char * const alignment_name[(MO_AMASK >= > MO_ASHIFT) + 1] =3D { [MO_ALIGN_64 >> MO_ASHIFT] =3D "al64+", }; =20 +static inline bool tcg_regset_single(TCGRegSet d) +{ + return (d & (d - 1)) =3D=3D 0; +} + +static inline TCGReg tcg_regset_first(TCGRegSet d) +{ + if (TCG_TARGET_NB_REGS <=3D 32) { + return ctz32(d); + } else { + return ctz64(d); + } +} + void tcg_dump_ops(TCGContext *s) { char buf[128]; @@ -1902,6 +1916,7 @@ void tcg_dump_ops(TCGContext *s) def =3D &tcg_op_defs[c]; =20 if (c =3D=3D INDEX_op_insn_start) { + nb_oargs =3D 0; col +=3D qemu_log("\n ----"); =20 for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { @@ -2902,31 +2917,72 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg,= TCGRegSet allocated_regs) } } =20 -/* Allocate a register belonging to reg1 & ~reg2 */ -static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, - TCGRegSet allocated_regs, bool rev) +/** + * tcg_reg_alloc: + * @required_regs: Set of registers in which we must allocate. + * @allocated_regs: Set of registers which must be avoided. + * @preferred_regs: Set of registers we should prefer. + * @rev: True if we search the registers in "indirect" order. + * + * The allocated register must be in @required_regs & ~@allocated_regs, + * but if we can put it in @preferred_regs we may save a move later. + */ +static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, + TCGRegSet allocated_regs, + TCGRegSet preferred_regs, bool rev) { - int i, n =3D ARRAY_SIZE(tcg_target_reg_alloc_order); + int i, j, f, n =3D ARRAY_SIZE(tcg_target_reg_alloc_order); + TCGRegSet reg_ct[2]; const int *order; - TCGReg reg; - TCGRegSet reg_ct; =20 - reg_ct =3D desired_regs & ~allocated_regs; + reg_ct[1] =3D required_regs & ~allocated_regs; + tcg_debug_assert(reg_ct[1] !=3D 0); + reg_ct[0] =3D reg_ct[1] & preferred_regs; + + /* Skip the preferred_regs option if it cannot be satisfied, + or if the preference made no difference. */ + f =3D reg_ct[0] =3D=3D 0 || reg_ct[0] =3D=3D reg_ct[1]; + order =3D rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; =20 - /* first try free registers */ - for(i =3D 0; i < n; i++) { - reg =3D order[i]; - if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] =3D=3D= NULL) - return reg; + /* Try free registers, preferences first. */ + for (j =3D f; j < 2; j++) { + TCGRegSet set =3D reg_ct[j]; + + if (tcg_regset_single(set)) { + /* One register in the set. */ + TCGReg reg =3D tcg_regset_first(set); + if (s->reg_to_temp[reg] =3D=3D NULL) { + return reg; + } + } else { + for (i =3D 0; i < n; i++) { + TCGReg reg =3D order[i]; + if (s->reg_to_temp[reg] =3D=3D NULL && + tcg_regset_test_reg(set, reg)) { + return reg; + } + } + } } =20 - /* XXX: do better spill choice */ - for(i =3D 0; i < n; i++) { - reg =3D order[i]; - if (tcg_regset_test_reg(reg_ct, reg)) { + /* We must spill something. */ + for (j =3D f; j < 2; j++) { + TCGRegSet set =3D reg_ct[j]; + + if (tcg_regset_single(set)) { + /* One register in the set. */ + TCGReg reg =3D tcg_regset_first(set); tcg_reg_free(s, reg, allocated_regs); return reg; + } else { + for (i =3D 0; i < n; i++) { + TCGReg reg =3D order[i]; + if (tcg_regset_test_reg(set, reg)) { + tcg_reg_free(s, reg, allocated_regs); + return reg; + } + } } } =20 @@ -2944,12 +3000,14 @@ static void temp_load(TCGContext *s, TCGTemp *ts, T= CGRegSet desired_regs, case TEMP_VAL_REG: return; case TEMP_VAL_CONST: - reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirec= t_base); + reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, + 0, ts->indirect_base); tcg_out_movi(s, ts->type, reg, ts->val); ts->mem_coherent =3D 0; break; case TEMP_VAL_MEM: - reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirec= t_base); + reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, + 0, ts->indirect_base); tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); ts->mem_coherent =3D 1; break; @@ -3109,7 +3167,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) input one. */ tcg_regset_set_reg(allocated_regs, ts->reg); ots->reg =3D tcg_reg_alloc(s, tcg_target_available_regs[ot= ype], - allocated_regs, ots->indirect_bas= e); + allocated_regs, 0, + ots->indirect_base); } tcg_out_mov(s, otype, ots->reg, ts->reg); } @@ -3197,7 +3256,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) /* allocate a new register matching the constraint=20 and move the temporary register into it */ reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, - ts->indirect_base); + 0, ts->indirect_base); tcg_out_mov(s, ts->type, reg, ts->reg); } new_args[i] =3D reg; @@ -3242,7 +3301,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) } else if (arg_ct->ct & TCG_CT_NEWREG) { reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs | o_allocated_regs, - ts->indirect_base); + 0, ts->indirect_base); } else { /* if fixed register, we try to use it */ reg =3D ts->reg; @@ -3251,7 +3310,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) goto oarg_end; } reg =3D tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, - ts->indirect_base); + 0, ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); /* if a fixed register is used, then a move will be done after= wards */ --=20 2.17.2