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[211.28.135.144]) by smtp.gmail.com with ESMTPSA id t21sm48501628pgg.24.2018.12.25.12.58.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Dec 2018 12:58:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JsZcBFYMSdp+4zdJxNkrDTpJo5A7UGR4ZaFTrSGM0S8=; b=h6Lyok2RgRFGjFKhWlcnpAsEklWbxj86Nc+b3OReKVOxK7qQTXkfjAMBsd9iWgUBdU WRb5S7WDWXaGKItrbDL45pVcAjIcU6I7pBIBKzIV2TNU7Pf0/fES+dtiRj+LcMgF9Lwf 4oYtyWGjTG2SFgB1W2UDG1sfqTwVYHzECcRZo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JsZcBFYMSdp+4zdJxNkrDTpJo5A7UGR4ZaFTrSGM0S8=; b=HOPIYLVErh1k17X2ZGOg/69hZRLeBkatW32q21YPj1VZalLlpr5STeqyfWbjs8WBhM UQFPFfHyKsTYV3fa69Ww/42x2PphUFPR3ca8JHGAK5UKFVUTEpJGIYT3U/OhNn/N+NMd uacmSG/eeFiP7qqGPEBOu3rTdClFw1yBh4qKucGJKeOrTeHCxXft66FDRo6XlVxpBPQC V4/kZc7KDV4at+F5QSMPbDV9mOVVgznz47lUFRzVMKhfahHUFIWuAE4Y2GOu5oPEGKsX CPrgZrVSRKN4Jfx3R9IAfdYYZLxoPuVP9HRJznNE+t50CX3taLreikRz3qs0ArS0r8kW XhLw== X-Gm-Message-State: AJcUukef/1ch7kgw1NbtYjaJaIsqsIqjn42IiPcNkfWJetzkYm/swx4v 50Fh5KTVcvdmV15hGdisF7hT9YMCSo4= X-Google-Smtp-Source: ALg8bN5KY6mLcl3RGuvkK/Z7o+Z/wkMfR/t1EczKv8ie+JmDs6dJso2o9ilIc+sSS6+8Ll3YG5KgGg== X-Received: by 2002:a63:374e:: with SMTP id g14mr16984151pgn.59.1545771488594; Tue, 25 Dec 2018 12:58:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:55:06 +1100 Message-Id: <20181225205529.10874-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Richard Henderson Message-Id: Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.inc.c | 111 +++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 014c5287f5..8a5f1deefc 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1805,3 +1805,114 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) return NULL; } } + +static const int tcg_target_callee_save_regs[] =3D { + TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + TCG_REG_RA, /* should be last for ABI compliance */ +}; + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZ= E) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); + + /* TB prologue */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + for (i =3D 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + +#if !defined(CONFIG_SOFTMMU) + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); +#endif + + /* Call generated code */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1= ], 0); + + /* Return path for goto_ptr. Set return value to 0 */ + s->code_gen_epilogue =3D s->code_ptr; + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); + + /* TB epilogue */ + tb_ret_addr =3D s->code_ptr; + for (i =3D 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_RISCV + +static const DebugFrame debug_frame =3D { + .h.cie.len =3D sizeof(DebugFrameCIE) - 4, /* length after .len member = */ + .h.cie.id =3D -1, + .h.cie.version =3D 1, + .h.cie.code_align =3D 1, + .h.cie.data_align =3D -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.return_column =3D TCG_REG_RA, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len =3D sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_off= set), + + .fde_def_cfa =3D { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs =3D { + 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ + 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ + 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ + 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ + 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ + 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ + 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ + 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ + 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ + 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ + 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ + 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} --=20 2.17.2