From nobody Fri Nov 7 03:54:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154532678668177.88281542923414; Thu, 20 Dec 2018 09:26:26 -0800 (PST) Received: from localhost ([::1]:38590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ga1K9-00032d-40 for importer@patchew.org; Thu, 20 Dec 2018 11:37:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ga1Eg-0007pl-Ki for qemu-devel@nongnu.org; Thu, 20 Dec 2018 11:31:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ga1Ef-0000nY-Ss for qemu-devel@nongnu.org; Thu, 20 Dec 2018 11:31:46 -0500 Received: from chuckie.co.uk ([82.165.15.123]:37294 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ga1Ef-0000ml-J6; Thu, 20 Dec 2018 11:31:45 -0500 Received: from host86-177-178-114.range86-177.btcentralplus.com ([86.177.178.114] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1ga1Et-0000iB-JQ; Thu, 20 Dec 2018 16:32:01 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, richard.henderson@linaro.org, david@gibson.dropbear.id.au Date: Thu, 20 Dec 2018 16:31:20 +0000 Message-Id: <20181220163123.9233-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181220163123.9233-1-mark.cave-ayland@ilande.co.uk> References: <20181220163123.9233-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.178.114 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH v3 6/9] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of accessing the FPR, VMX and VSX registers through static arrays of TCGv_i64 globals, remove them and change the helpers to load/store data dir= ectly within cpu_env. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c | 59 ++++++++++-----------------------= ---- target/ppc/translate/vsx-impl.inc.c | 4 +-- 2 files changed, 18 insertions(+), 45 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa3e8dc114..5923c688cd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -55,15 +55,9 @@ /* global register indexes */ static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ - + 10*4 + 22*5 /* FPR */ - + 2*(10*6 + 22*7) /* AVRh, AVRl */ - + 10*5 + 22*6 /* VSR */ + 8*5 /* CRF */]; static TCGv cpu_gpr[32]; static TCGv cpu_gprh[32]; -static TCGv_i64 cpu_fpr[32]; -static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; -static TCGv_i64 cpu_vsr[32]; static TCGv_i32 cpu_crf[8]; static TCGv cpu_nip; static TCGv cpu_msr; @@ -108,39 +102,6 @@ void ppc_translate_init(void) offsetof(CPUPPCState, gprh[i]), p= ); p +=3D (i < 10) ? 4 : 5; cpu_reg_names_size -=3D (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "fp%d", i); - cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, fpr[i]),= p); - p +=3D (i < 10) ? 4 : 5; - cpu_reg_names_size -=3D (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "avr%dH", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrh[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[0]), p); -#else - cpu_avrh[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[1]), p); -#endif - p +=3D (i < 10) ? 6 : 7; - cpu_reg_names_size -=3D (i < 10) ? 6 : 7; - - snprintf(p, cpu_reg_names_size, "avr%dL", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrl[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[1]), p); -#else - cpu_avrl[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[0]), p); -#endif - p +=3D (i < 10) ? 6 : 7; - cpu_reg_names_size -=3D (i < 10) ? 6 : 7; - snprintf(p, cpu_reg_names_size, "vsr%d", i); - cpu_vsr[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, vsr[i]),= p); - p +=3D (i < 10) ? 5 : 6; - cpu_reg_names_size -=3D (i < 10) ? 5 : 6; } =20 cpu_nip =3D tcg_global_mem_new(cpu_env, @@ -6696,22 +6657,34 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_mov_i64(dst, cpu_fpr[regno]); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, fpr[regno])); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_mov_i64(cpu_fpr[regno], src); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, fpr[regno])); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { - tcg_gen_mov_i64(dst, (high ? cpu_avrh : cpu_avrl)[regno]); +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 1 : 0)])); +#endif } =20 static inline void set_avr64(int regno, TCGv_i64 src, bool high) { - tcg_gen_mov_i64((high ? cpu_avrh : cpu_avrl)[regno], src); +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 1 : 0)])); +#endif } =20 #include "translate/fp-impl.inc.c" diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index f0665df1a5..7eaa36b4d5 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -2,12 +2,12 @@ =20 static inline void get_vsr(TCGv_i64 dst, int n) { - tcg_gen_mov_i64(dst, cpu_vsr[n]); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n])); } =20 static inline void set_vsr(int n, TCGv_i64 src) { - tcg_gen_mov_i64(cpu_vsr[n], src); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n])); } =20 static inline void get_cpu_vsrh(TCGv_i64 dst, int n) --=20 2.11.0