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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id f64sm47287228pfh.0.2018.12.18.20.21.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 20:21:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jzabKvrmTWISY3KB/ab08L0zuoOLLDdoLb1OMab5kDU=; b=WeK7t7C30rVzlfptIN9x1dEOq1B1ZU1xEqIWpZl9glKj00kRa7bWTUKvFyJmtdzGDt pacZrMoAdQ6TgYw/2oQ1t4l4NzsjMVaFiavA1yQaX+W3LIpj0go0R5AAiElHs31eCTbm i83HfEjBozV13Aw4A1m8wsZj3QL3387XwG3g4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jzabKvrmTWISY3KB/ab08L0zuoOLLDdoLb1OMab5kDU=; b=H2hEI2sz255Wf26tBt36nM00a6DKEfdgYuiklxziHr5eqaaaHlniClXpOrBrI5BNXa QLhvbwXmAaZ8y7Oq+/wTIoX830KFUncLacihlUyqAEzkpzr0rYDykxXV3k5tRGoTVdOl x3aFSPZpHgVS2ZmV6ABGJnEXSUebVlZgnQvB3gGaBN6aBCjfGdL/3Lm6KC0dfOu6z3c/ yX74uNWqXnAlgtZBnbD0aGSphHdyfgHGoV2NNXEWoAWCkxJ41H4Dpy0IJtc/dDXQevcE cMSqCg0ncz88nPBoSgjjhnUgSURNmd4yrTWwfGWLkvSwbd52VLSW4oPon7wa0lXVT5bM U8aQ== X-Gm-Message-State: AA+aEWZpqjCp+1z37b+z/Jruw3cF2o5sunrsMlRJ8ccpobygLEJia9i1 mz1XxYDB3+KG8ya9Rai5Rnim2esZuUU= X-Google-Smtp-Source: AFSGD/WIuI/cuCHDAWY+ylagNmZ+sj0tV2Ae4MIaC+3jrFiQSaJaaWkOC7gbUN1hpAjmbUkZZyHBCQ== X-Received: by 2002:a17:902:66e6:: with SMTP id e93mr18437607plk.92.1545193279831; Tue, 18 Dec 2018 20:21:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Dec 2018 20:21:08 -0800 Message-Id: <20181219042113.7364-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181219042113.7364-1-richard.henderson@linaro.org> References: <20181219042113.7364-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v5 3/8] linux-user: Reduce regpairs_aligned & target_offset64 ifdefs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/syscall.c | 54 ++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 7118f07441..d4c11c3e93 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -474,37 +474,38 @@ static inline int next_free_host_timer(void) } #endif =20 -/* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers= */ +/* + * Returns true if syscall NUM expects 64bit types aligned even + * on pairs of registers. + */ +static inline bool regpairs_aligned(void *cpu_env, int num) +{ #ifdef TARGET_ARM -static inline int regpairs_aligned(void *cpu_env, int num) -{ - return ((((CPUARMState *)cpu_env)->eabi) =3D=3D 1) ; -} -#elif defined(TARGET_MIPS) && (TARGET_ABI_BITS =3D=3D 32) -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } + return ((CPUARMState *)cpu_env)->eabi; +#elif defined(TARGET_MIPS) && TARGET_ABI_BITS =3D=3D 32 + return true; #elif defined(TARGET_PPC) && !defined(TARGET_PPC64) -/* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pa= irs - * of registers which translates to the same as ARM/MIPS, because we start= with - * r3 as arg1 */ -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } + /* + * SysV AVI for PPC32 expects 64bit parameters to be passed on + * odd/even pairs of registers which translates to the same as + * we start with r3 as arg1. + */ + return true; #elif defined(TARGET_SH4) -/* SH4 doesn't align register pairs, except for p{read,write}64 */ -static inline int regpairs_aligned(void *cpu_env, int num) -{ + /* SH4 doesn't align register pairs, except for p{read,write}64. */ switch (num) { case TARGET_NR_pread64: case TARGET_NR_pwrite64: - return 1; - + return true; default: - return 0; + return false; } -} #elif defined(TARGET_XTENSA) -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } + return true; #else -static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } + return false; #endif +} =20 #define ERRNO_TABLE_SIZE 1200 =20 @@ -6066,21 +6067,16 @@ void syscall_init(void) } } =20 -#if TARGET_ABI_BITS =3D=3D 32 -static inline uint64_t target_offset64(uint32_t word0, uint32_t word1) +static inline uint64_t target_offset64(abi_ulong word0, abi_ulong word1) { -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_ABI_BITS =3D=3D 64 + return word0; +#elif defined(TARGET_WORDS_BIGENDIAN) return ((uint64_t)word0 << 32) | word1; #else return ((uint64_t)word1 << 32) | word0; #endif } -#else /* TARGET_ABI_BITS =3D=3D 32 */ -static inline uint64_t target_offset64(uint64_t word0, uint64_t word1) -{ - return word0; -} -#endif /* TARGET_ABI_BITS !=3D 32 */ =20 #ifdef TARGET_NR_truncate64 static inline abi_long target_truncate64(void *cpu_env, const char *arg1, --=20 2.17.2