From nobody Fri Nov 7 02:17:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545162747161338.39478221421064; Tue, 18 Dec 2018 11:52:27 -0800 (PST) Received: from localhost ([::1]:54842 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZI4M-0002SJ-VH for importer@patchew.org; Tue, 18 Dec 2018 11:18:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZHzk-0006wZ-F0 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 11:13:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZHzd-0002tj-9a for qemu-devel@nongnu.org; Tue, 18 Dec 2018 11:13:20 -0500 Received: from mx1.redhat.com ([209.132.183.28]:35300) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZHzc-0002t8-Tq for qemu-devel@nongnu.org; Tue, 18 Dec 2018 11:13:13 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EFE4289ADB; Tue, 18 Dec 2018 16:13:11 +0000 (UTC) Received: from redhat.com (ovpn-120-67.rdu2.redhat.com [10.10.120.67]) by smtp.corp.redhat.com (Postfix) with SMTP id BD0BE60C44; Tue, 18 Dec 2018 16:13:07 +0000 (UTC) Date: Tue, 18 Dec 2018 11:13:07 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181218161008.3882-21-mst@redhat.com> References: <20181218161008.3882-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181218161008.3882-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 18 Dec 2018 16:13:12 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL v2 20/30] intel_iommu: dma read/write draining support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Peter Xu , Yu Wang , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Peter Xu Support DMA read/write draining should be easy for existing VT-d emulation since the emulation itself does not have any request queue there so we don't need to do anything to flush the un-commited queue. What we need to do is to declare the support. These capabilities are required to pass Windows SVVP test program. It is verified that when with parameters "x-aw-bits=3D48,caching-mode=3Doff" we can pass the Windows SVVP test with this patch applied. Otherwise we'll fail with: IOMMU[0] - DWD (DMA write draining) not supported IOMMU[0] - DWD (DMA read draining) not supported Segment 0 has no DMA remapping capable IOMMU units However since these bits are not declared support for QEMU<=3D3.1, we'll need a compatibility bit for it and we turn this on by default only for QEMU>=3D4.0. Please refer to VT-d spec 6.5.4 for more information. CC: Yu Wang Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=3D1654550 Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 3 +++ include/hw/i386/intel_iommu.h | 1 + include/hw/i386/pc.h | 5 +++++ hw/i386/intel_iommu.c | 4 ++++ 4 files changed, 13 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index d084099ed9..00e9edbc66 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -203,6 +203,9 @@ #define VTD_CAP_MAMV (VTD_MAMV << 48) #define VTD_CAP_PSI (1ULL << 39) #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) +#define VTD_CAP_DRAIN_WRITE (1ULL << 54) +#define VTD_CAP_DRAIN_READ (1ULL << 55) +#define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WR= ITE) #define VTD_CAP_CM (1ULL << 7) =20 /* Supported Adjusted Guest Address Widths */ diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index ed4e758273..a321cc9691 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -245,6 +245,7 @@ struct IntelIOMMUState { OnOffAuto intr_eim; /* Toggle for EIM cabability */ bool buggy_eim; /* Force buggy EIM unless eim=3Doff */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ + bool dma_drain; /* Whether DMA r/w draining enabled */ =20 /* * Protects IOMMU states in general. Currently it protects the diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 9d29c4b1df..c7c0c944e8 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -296,6 +296,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_= t *); =20 #define PC_COMPAT_3_1 \ HW_COMPAT_3_1 \ + {\ + .driver =3D "intel-iommu",\ + .property =3D "dma-drain",\ + .value =3D "off",\ + }, =20 #define PC_COMPAT_3_0 \ HW_COMPAT_3_0 \ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4806d7edb4..26cc731c7b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2659,6 +2659,7 @@ static Property vtd_properties[] =3D { DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState, aw_bits, VTD_HOST_ADDRESS_WIDTH), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), + DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -3147,6 +3148,9 @@ static void vtd_init(IntelIOMMUState *s) s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits); + if (s->dma_drain) { + s->cap |=3D VTD_CAP_DRAIN; + } if (s->aw_bits =3D=3D VTD_HOST_AW_48BIT) { s->cap |=3D VTD_CAP_SAGAW_48bit; } --=20 MST