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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ID7FIZGaJQwmRQTNTunXnGYY3XJ2vCL6udRBHw0u68A=; b=ge24hGTBfsdMHDymsPFRP2MnV6V00YW7Q9TJ+IM8aNKC6pC/vLutGU/PAGZqGCC0kc e2gPkPsa/ABL2P6wS/IFDSduHsyNJu94I/DZO3gMasDnvBqtqAPcDKjH0AqkwJ4rJORy r8E1EVRyR+oSrtKEJSUJYHSGgQ/HArql5isQY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ID7FIZGaJQwmRQTNTunXnGYY3XJ2vCL6udRBHw0u68A=; b=Sr4E0MqRbx4RAAJ20pdUF3ygNtEHXZ8HYvcBCZ1+2GlNNfkwcoKEjAs8Yq3dJyIrkP fxe6GudX8Yz2EH7s/22ddBt0FpCrFJZNxXiuCTrA8VnoxAwYpG6FRClgWbVIiRJL2lum Z2KSY8/JKceSD+Pl8xdkFKhsaQwZZCQ87GANyAB0qXcETgMg9Gy//bDgmgSI678px/87 cAEhEWxKAN1qzJsZ5NH1G1zatzhpibSRUa24wJmSQyKLoOvb24y1WmLbyTpiyk6hwD6x Le/5OoQB0iCstbv41ObQoltd4hdUwD//3qzhLtX/xqXSaHFWqGWWGuQ2rgnGAVGw0vpU XH+g== X-Gm-Message-State: AA+aEWYJGdmkitlf0KX5Y2/FvDmXdFfBdpEEX3G4QlWof5VGR9QbJb8b 7cSwKRxIBA+cq3iTNmmIWbYE4QE81aM= X-Google-Smtp-Source: AFSGD/WM/eW8koAlcZ911GjSZfyrcaN6JKimPBFGSviwHsG/SQEsdjBLEgZwGrFTbOh620HYFv4b+Q== X-Received: by 2002:a17:902:765:: with SMTP id 92mr15406336pli.242.1545115196631; Mon, 17 Dec 2018 22:39:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:09 -0800 Message-Id: <20181218063911.2112-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change the representation of VSCR_SAT such that it is easy to set from vector code. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/cpu.h | 4 +++- target/ppc/int_helper.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a2fe6058b1..26d2e16720 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1063,10 +1063,12 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Vector status and control register */ + /* Vector status and control register, minus VSCR_SAT. */ uint32_t vscr; /* VSX registers (including FP and AVR) */ ppc_vsr_t vsr[64] QEMU_ALIGNED(16); + /* Non-zero if and only if VSCR_SAT should be set. */ + ppc_vsr_t vscr_sat; /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 38aa3e85a6..9dbcbcd87a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -471,18 +471,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh) =20 void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { - env->vscr =3D vscr; + env->vscr =3D vscr & ~(1u << VSCR_SAT); + /* Which bit we set is completely arbitrary, but clear the rest. */ + env->vscr_sat.u64[0] =3D vscr & (1u << VSCR_SAT); + env->vscr_sat.u64[1] =3D 0; set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } =20 uint32_t helper_mfvscr(CPUPPCState *env) { - return env->vscr; + uint32_t sat =3D (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) !=3D 0; + return env->vscr | (sat << VSCR_SAT); } =20 static inline void set_vscr_sat(CPUPPCState *env) { - env->vscr |=3D 1 << VSCR_SAT; + /* The choice of non-zero value is arbitrary. */ + env->vscr_sat.u32[0] =3D 1; } =20 void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) --=20 2.17.2