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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e9sbYZtWNeSqAkktYrwPzYVucFa+O20EgxyH5iSp3Ug=; b=igL+oZVf0MHYg40/KlUAOjV2R5/6vxtWK+jKDmWEFf7hltLnsyE9HTy7h/bVNjRHmL OYlY4D+1TCVDck4MAm+IGAGQ3eWEXyMkJioAJ+3fVwKaWtoMGlUa5LvIOFnM4uutLIGX JWnyN+LWsBhoPj9YEVjSpsudyRw5N3xDZ4Vcg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e9sbYZtWNeSqAkktYrwPzYVucFa+O20EgxyH5iSp3Ug=; b=AfxZKg4vzESg/2TBNomlryjR39GSFYWT4+zn9dWjoQ6bGZ24+uta+Av26izxsQ9DSu cErSvbgFWJcxSABE4ZHJWx5KLkO4ybbSQCLUB6W4xz7tvHkX3KsbsVa4qT+OxrRpMmHa wd+UTij/JsUOjJe70C5NLbksHPIDtuX3zWorx6I6jcJAw+4hqM3MBZGLGARVxNeRL+jq Blw7ZUvO4T8RjY807AEX5zaCliV4JDpd0NUkQ/3CXLrrpmjHwqY9BtGu84GZSw7Sc7BK 6KLwm0xbOO5It8SYsrO9+RnnoVcrNp21OiPXvshx3EMMto36s41HnlMQrZYevo/frALH gvsw== X-Gm-Message-State: AA+aEWYIj3fzweKigdG4MXdhN10fqCqgxThefRuNg1CTWqVKcRKxelQE 11Jxd9ud0OeyLnc+I2DZfJq5g3RZA0U= X-Google-Smtp-Source: AFSGD/VWcWqZs8I2tJyGbil9hAZzR32E6ThXe1uIYwpjmX6CnGolhlpayAdcNBw/pg7+O4fF5HqI6Q== X-Received: by 2002:a63:6150:: with SMTP id v77mr14467051pgb.266.1545115186890; Mon, 17 Dec 2018 22:39:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:02 -0800 Message-Id: <20181218063911.2112-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 55 ++++++++++++++--------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index a040038ed4..dc32471cd7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1280,40 +1280,39 @@ static void glue(gen_, name)(DisasContext * ctx) = \ VSX_XXMRG(xxmrghw, 1) VSX_XXMRG(xxmrglw, 0) =20 +static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) +{ + tcg_gen_and_i64(b, b, c); + tcg_gen_andc_i64(a, a, c); + tcg_gen_or_i64(t, a, b); +} + +static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a, + TCGv_vec b, TCGv_vec c) +{ + tcg_gen_and_vec(vece, b, b, c); + tcg_gen_andc_vec(vece, a, a, c); + tcg_gen_or_vec(vece, t, a, b); +} + static void gen_xxsel(DisasContext * ctx) { - TCGv_i64 a, b, c, tmp; + static const GVecGen4 g =3D { + .fni8 =3D xxsel_i64, + .fniv =3D xxsel_vec, + .vece =3D MO_64, + }; + int rt =3D xT(ctx->opcode); + int ra =3D xA(ctx->opcode); + int rb =3D xB(ctx->opcode); + int rc =3D xC(ctx->opcode); + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - a =3D tcg_temp_new_i64(); - b =3D tcg_temp_new_i64(); - c =3D tcg_temp_new_i64(); - tmp =3D tcg_temp_new_i64(); - - get_cpu_vsrh(a, xA(ctx->opcode)); - get_cpu_vsrh(b, xB(ctx->opcode)); - get_cpu_vsrh(c, xC(ctx->opcode)); - - tcg_gen_and_i64(b, b, c); - tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(tmp, a, b); - set_cpu_vsrh(xT(ctx->opcode), tmp); - - get_cpu_vsrl(a, xA(ctx->opcode)); - get_cpu_vsrl(b, xB(ctx->opcode)); - get_cpu_vsrl(c, xC(ctx->opcode)); - - tcg_gen_and_i64(b, b, c); - tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(tmp, a, b); - set_cpu_vsrl(xT(ctx->opcode), tmp); - - tcg_temp_free_i64(a); - tcg_temp_free_i64(b); - tcg_temp_free_i64(c); - tcg_temp_free_i64(tmp); + tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra), + vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g); } =20 static void gen_xxspltw(DisasContext *ctx) --=20 2.17.2