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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34C0PCPFsQsKd58ay2ar3pj3ly5MXK9b89BvXCPHT7s=; b=Aeqk64PCALb/k1wdLQa1cKcjjvQkms/RE+QFd4vWPtpqZHUxmaMwDGB1XfMSAiQxG+ SYaWxzBb45hoV0ZQufpYVmT4qtXahP9+Aejnz+9EUkC2ojksuwHOOhKgsSBO8JJARSKS kVchQZp27sxpdqbYYQ3TXKe6sM3fIFgOUvEMs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34C0PCPFsQsKd58ay2ar3pj3ly5MXK9b89BvXCPHT7s=; b=sG6sa/ddNWvfvJuUlxkeY3fgPWId4lKRc56ILqdovqnMclsdM14rTlzQMDhJlzaIBa x3JZiVoNWDch6CZVm81g2qlsPv3r+jIsUVP7qgYSTo1y4azFrzTOsBwTG/VTFTcvJsVS VEG2Cxt3exIPWj2n2SNINlTfHNsvV4OczohDK/N46fDED7qbIExsrgGmnYsS7zdw1akX w5CdBs4ZKTuI3/JI/WojER7hjx/TTfede9fM5jB/+ZYRaheZUKFkf853hjO2wEjTjOAG FXveL3c2206+Y/3ZjGkMSXJByAEon6sccLMnQTXwF2lypoReIWga1tTUKvRSwEN5Dc/u VDFA== X-Gm-Message-State: AA+aEWYXLcgfRTbiOgGLi+JZc5/jR4V5NghjcWUmpochUMmiHDnwfjrK /yWKKOrJqZa4xJcUydiTDS5isE+Eoqc= X-Google-Smtp-Source: AFSGD/UeFjBE5zGTUOmDh4KL8arVzZSne4w8VMVSTwx4Fd8usgqh7ik+wwCobckSz1ifpFWEyDTdjQ== X-Received: by 2002:a62:de06:: with SMTP id h6mr16054864pfg.158.1545115155036; Mon, 17 Dec 2018 22:39:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:38 -0800 Message-Id: <20181218063911.2112-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 01/34] tcg: Add logical simplifications during gvec expand X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We handle many of these during integer expansion, and the rest of them during integer optimization. Signed-off-by: Richard Henderson Reviewed-by: David Gibson --- tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 61c25f5784..ec231b78fb 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1840,7 +1840,12 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, = uint32_t aofs, .opc =3D INDEX_op_and_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } =20 void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1853,7 +1858,12 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, u= int32_t aofs, .opc =3D INDEX_op_or_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } =20 void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1866,7 +1876,12 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, = uint32_t aofs, .opc =3D INDEX_op_xor_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } =20 void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1879,7 +1894,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs,= uint32_t aofs, .opc =3D INDEX_op_andc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } =20 void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -1892,7 +1912,12 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, = uint32_t aofs, .opc =3D INDEX_op_orc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } } =20 static const GVecGen2s gop_ands =3D { --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116284107139.49743119992945; Mon, 17 Dec 2018 22:58:04 -0800 (PST) Received: from localhost ([::1]:52123 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9KM-00081L-Oo for importer@patchew.org; Tue, 18 Dec 2018 01:58:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92y-0001iW-Ap for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92s-0002t9-Gh for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:04 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:42085) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92r-0001tb-Pe for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:57 -0500 Received: by mail-pg1-x52b.google.com with SMTP id d72so7337892pga.9 for ; Mon, 17 Dec 2018 22:39:17 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NBIM0mIrycdtqlXSzpKN+VgcBQ4YRzFxTXw+YZBnlKY=; b=HZ+OOz1JKGhs1iOFCAka0Rv7QLicbHM2RQGb5or8IH/0tWPuFxhByY3WQ5v27eu1dK Pl2iJscCLqraJeXqDTE/fdG2+4xTYdJ87hTtNSseeWU/TiuRy6ncCtnB+EFHX2+7OeNj pQhEzkGhwcccQfdM3jN+T1fOl8G+ubuGjxTO8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NBIM0mIrycdtqlXSzpKN+VgcBQ4YRzFxTXw+YZBnlKY=; b=NM9EMG8816W40nWDENbYv9XPvgtw1ixXxkNPScECTAyBWNYE3PwqXT1gHpinTDaoFr ivfe6shtyVqOxkobOtuqE/sROL0c/r7dlXoRtBgcnUIRCl7oga/ydiDvn2a6elrt+kFP e+6pMdbAGUJupLGqFEWMbeISBL7YdHaKINxbqEnW+htNPWhJroryM1fAfZrxud86EufU 0HX5b2cFn8Gx6ymNc+CKeKSBAsQKu5/t9CORXQCXbJebL/4+1aVX6ekPXNU6715Mby2Z itCKwt3A4GvilsbiHFJttYTzJexY7R6bdt2UAd9502WN7vpwBmbgGIkpNZIKhA6nzUuV efyw== X-Gm-Message-State: AA+aEWaBstuBDoD7zxy5hBu53VAZw28f6ys43aEeFbuPSb4PBS3wY3tu QliX1EUIlhSpIqhGe3vzA/kIjKnSME8= X-Google-Smtp-Source: AFSGD/WQzY1Hn8+MAe6h0sBCeqEHgX6JKjWvip4j1XIQ32W+ccOAujIsKSQoHgfjIOluZuskvniyzA== X-Received: by 2002:a63:4456:: with SMTP id t22mr15140191pgk.0.1545115156263; Mon, 17 Dec 2018 22:39:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:39 -0800 Message-Id: <20181218063911.2112-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since we're now handling a =3D=3D b generically, we no longer need to do it by hand within target/arm/. Signed-off-by: Richard Henderson Reviewed-by: David Gibson --- target/arm/translate-a64.c | 6 +----- target/arm/translate-sve.c | 6 +----- target/arm/translate.c | 12 +++--------- 3 files changed, 5 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..2d6f8c1b4f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10152,11 +10152,7 @@ static void disas_simd_3same_logic(DisasContext *s= , uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); return; case 2: /* ORR */ - if (rn =3D=3D rm) { /* MOV */ - gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); - } + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); return; case 3: /* ORN */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b15b615ceb..3a2eb51566 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz= *a) =20 static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) { - if (a->rn =3D=3D a->rm) { /* MOV */ - return do_mov_z(s, a->rd, a->rn); - } else { - return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); - } + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); } =20 static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c4675ffd8..33b1860148 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); break; - case 2: - if (rn =3D=3D rm) { - /* VMOV */ - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size= ); - } else { - /* VORR */ - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } + case 2: /* VORR */ + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); break; case 3: /* VORN */ tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115335285631.214335735861; Mon, 17 Dec 2018 22:42:15 -0800 (PST) Received: from localhost ([::1]:52027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ950-00037k-H2 for importer@patchew.org; Tue, 18 Dec 2018 01:42:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92p-0001ba-RJ for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92n-0002lf-MC for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:55 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35926) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92l-0001u6-5j for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:51 -0500 Received: by mail-pg1-x543.google.com with SMTP id n2so7349923pgm.3 for ; Mon, 17 Dec 2018 22:39:18 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zd6DkcIfQ90+2s7gpnUpm/YC3fVo3ib1Y0RDZl5yVWo=; b=At+jMiUkrbtLVsA0EdIn3YaV/LXuNMGd9GKJgFhVmfBj3//OGyFTRzaH5v8u55O2+6 i8elLHOB9lm/VHKxTnn/Wi5WqIVv1xP1kLjtvWQKJBJliyoCReFw+98OwtoxxkKca4aD F3L7XqMchPJ94a4e5f8eFy8dqevTHmpHV5BXY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zd6DkcIfQ90+2s7gpnUpm/YC3fVo3ib1Y0RDZl5yVWo=; b=tp684UXy0MffKNdptkEMU+h6LKKjxC2aI1qSt+H3N4seeAnWtmTluCoN6DJedDd7M9 N2QCS36aitnE6/PXa2AjbvxPBnwvsevQeQ8mdetatNnHlW9VPsZB1+imJzYJ7F9vJljh R1CQrDGpHwTta/2FbfQMsAwqRWDB/7CP3xnQZ858JPzkvsPkzo1diT8fHUUOVqEcfc6i PkBUSOiklDC05CoPoIZLWQVW8lg5jHka9uGijvXLSs09+7jmAg1+osQFua/M6rAU+eHp fO9ONPvBo6JHJhIstigjCs9tJu+1uHizX1RxHGdawFafUEMT8YCyHwjFPa1aKy3Tiohc HKGA== X-Gm-Message-State: AA+aEWbdjqZvjUQrOwkuabq1xRl1La1DJz2L5+o0dHdTESLjIPII2lmL nrlBBC6AAmoItvgJrBB53qHXmlXZHXo= X-Google-Smtp-Source: AFSGD/XXzf1t0AX+w7d6hh0N7sCGKHK+/8ucGMTCGbchSdPN2wgKAESPGlehc2a6HsORO8WQlJyGwA== X-Received: by 2002:a62:c28e:: with SMTP id w14mr15546522pfk.115.1545115157354; Mon, 17 Dec 2018 22:39:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:40 -0800 Message-Id: <20181218063911.2112-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 03/34] tcg: Add gvec expanders for nand, nor, eqv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: David Gibson --- accel/tcg/tcg-runtime.h | 3 +++ tcg/tcg-op-gvec.h | 6 +++++ tcg/tcg-op.h | 3 +++ accel/tcg/tcg-runtime-gvec.c | 33 +++++++++++++++++++++++ tcg/tcg-op-gvec.c | 51 ++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 21 +++++++++++++++ 6 files changed, 117 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 1bd39d136d..835ddfebb2 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -211,6 +211,9 @@ DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr,= ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_nand, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index ff43a29a0b..d65b9d9d4c 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -242,6 +242,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, u= int32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index db4e9188f4..1974bf1cae 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -961,6 +961,9 @@ void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec= a, TCGv_vec b); void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); =20 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 90340e56e0..d1802467d5 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -512,6 +512,39 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint3= 2_t desc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_nand)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D ~(*(vec64 *)(a + i) & *(vec64 *)(b + i)); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_nor)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D ~(*(vec64 *)(a + i) | *(vec64 *)(b + i)); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D ~(*(vec64 *)(a + i) ^ *(vec64 *)(b + i)); + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index ec231b78fb..81689d02f7 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1920,6 +1920,57 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, = uint32_t aofs, } } =20 +void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_nand_i64, + .fniv =3D tcg_gen_nand_vec, + .fno =3D gen_helper_gvec_nand, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } +} + +void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_nor_i64, + .fniv =3D tcg_gen_nor_vec, + .fno =3D gen_helper_gvec_nor, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } +} + +void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_eqv_i64, + .fniv =3D tcg_gen_eqv_vec, + .fno =3D gen_helper_gvec_eqv, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + }; + + if (aofs =3D=3D bofs) { + tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1); + } else { + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + } +} + static const GVecGen2s gop_ands =3D { .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cefba3d185..d77fdf7c1d 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -275,6 +275,27 @@ void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a, TCGv_vec b) } } =20 +void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + /* TODO: Add TCG_TARGET_HAS_nand_vec when adding a backend supports it= . */ + tcg_gen_and_vec(0, r, a, b); + tcg_gen_not_vec(0, r, r); +} + +void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + /* TODO: Add TCG_TARGET_HAS_nor_vec when adding a backend supports it.= */ + tcg_gen_or_vec(0, r, a, b); + tcg_gen_not_vec(0, r, r); +} + +void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + /* TODO: Add TCG_TARGET_HAS_eqv_vec when adding a backend supports it.= */ + tcg_gen_xor_vec(0, r, a, b); + tcg_gen_not_vec(0, r, r); +} + void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { if (TCG_TARGET_HAS_not_vec) { --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=13baR0fYl6duiBYqIpKDqOz4EjDaN2cM4w2ffhmehW8=; b=SXfoBG7iMZmG/vXwlDheXCUNNDVjlGTnaEmexZW4Fe0rol23MnXI1yFzF+i7ci3mKB Ww7DkOOL2VJgczdn+7Hguc7K0Wx75OCMZYuINjT2RbKbWTDcRkKF3dkh4OO9ifuNsflV jqvt6mknF6vi0aO201YTlVQPd7m9OkeUE9/70= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=13baR0fYl6duiBYqIpKDqOz4EjDaN2cM4w2ffhmehW8=; b=TeQaMVv4GL7zI2MAwIPhpdtZvmR6pvonpGVIcfQT0F2xjUyoEsMLKkUuLGynnUtN1h r8EZUQuRtSI85V7DsHRTM74Sk8d21NI7gZubbrA7gztuOBbkc2Ju89ly4HxUylBjzjhV l38l3TeX6SUXNJRTVtQddOKK1pwm6YTjXLzYp6DJ3iDAOzyCSktMUnrAKzJpMIrHzpKc GBy3kW2wbZvMhznbXK9YKt5YcFhQ/fNJEjeWtgzWEvM0xiXLGfBeGehgWPLBQ6g1ukI+ 9H44a9S9ChfZ/O9s1EYkQNix3FZACN8cVUfQbhsrTVrzeLC2saLYab86HBw7VLs37dHa cLGQ== X-Gm-Message-State: AA+aEWau7zxh4U5tRJ0bCV3zTBdg2mJPG8cKkUVR09h64eZEtJESYCTf cvczH6BcAjaM2aSi9qCNjK3uvihBNB8= X-Google-Smtp-Source: AFSGD/V+JENaX8LslaNNx4cZfSg21IOmmdmoIk01pNngLnNhPzPxjcMX6kcQusnVqxA/f2C1C7fuPQ== X-Received: by 2002:a63:de04:: with SMTP id f4mr14476267pgg.292.1545115158616; Mon, 17 Dec 2018 22:39:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:41 -0800 Message-Id: <20181218063911.2112-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 04/34] tcg: Add write_aofs to GVecGen4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows writing 2 output, 3 input operations. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index d65b9d9d4c..2cb447112e 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -181,6 +181,8 @@ typedef struct { uint8_t vece; /* Prefer i64 to v64. */ bool prefer_i64; + /* Write aofs as a 2nd dest operand. */ + bool write_aofs; } GVecGen4; =20 void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 81689d02f7..c10d3d7b26 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -665,7 +665,7 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs, =20 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, + uint32_t cofs, uint32_t oprsz, bool write_aofs, void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i3= 2)) { TCGv_i32 t0 =3D tcg_temp_new_i32(); @@ -680,6 +680,9 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, = uint32_t bofs, tcg_gen_ld_i32(t3, cpu_env, cofs + i); fni(t0, t1, t2, t3); tcg_gen_st_i32(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_i32(t1, cpu_env, aofs + i); + } } tcg_temp_free_i32(t3); tcg_temp_free_i32(t2); @@ -769,7 +772,7 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs, =20 /* Expand OPSZ bytes worth of three-operand operations using i64 elements.= */ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, + uint32_t cofs, uint32_t oprsz, bool write_aofs, void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i6= 4)) { TCGv_i64 t0 =3D tcg_temp_new_i64(); @@ -784,6 +787,9 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, = uint32_t bofs, tcg_gen_ld_i64(t3, cpu_env, cofs + i); fni(t0, t1, t2, t3); tcg_gen_st_i64(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_i64(t1, cpu_env, aofs + i); + } } tcg_temp_free_i64(t3); tcg_temp_free_i64(t2); @@ -880,7 +886,7 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, = uint32_t aofs, /* Expand OPSZ bytes worth of four-operand operations using host vectors. = */ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, - uint32_t tysz, TCGType type, + uint32_t tysz, TCGType type, bool write_aofs, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec)) { @@ -896,6 +902,9 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_gen_ld_vec(t3, cpu_env, cofs + i); fni(vece, t0, t1, t2, t3); tcg_gen_st_vec(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_vec(t1, cpu_env, aofs + i); + } } tcg_temp_free_vec(t3); tcg_temp_free_vec(t2); @@ -1187,7 +1196,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uin= t32_t bofs, uint32_t cofs, */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some, - 32, TCG_TYPE_V256, g->fniv); + 32, TCG_TYPE_V256, g->write_aofs, g->fniv); if (some =3D=3D oprsz) { break; } @@ -1200,18 +1209,20 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, u= int32_t bofs, uint32_t cofs, /* fallthru */ case TCG_TYPE_V128: expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, - 16, TCG_TYPE_V128, g->fniv); + 16, TCG_TYPE_V128, g->write_aofs, g->fniv); break; case TCG_TYPE_V64: expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, - 8, TCG_TYPE_V64, g->fniv); + 8, TCG_TYPE_V64, g->write_aofs, g->fniv); break; =20 case 0: if (g->fni8 && check_size_impl(oprsz, 8)) { - expand_4_i64(dofs, aofs, bofs, cofs, oprsz, g->fni8); + expand_4_i64(dofs, aofs, bofs, cofs, oprsz, + g->write_aofs, g->fni8); } else if (g->fni4 && check_size_impl(oprsz, 4)) { - expand_4_i32(dofs, aofs, bofs, cofs, oprsz, g->fni4); + expand_4_i32(dofs, aofs, bofs, cofs, oprsz, + g->write_aofs, g->fni4); } else { assert(g->fno !=3D NULL); tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/L7LdGSm5NNT7VX4GhYH4GxUJMBjROELDT1h85Zk74Y=; b=FRsEgCe7/k5jpzf5PnDaF1UTSOW7IcmJJhDedw9EGReIkhkJl/0twG2z0xiNX3D/TZ UWdUS7JUBL4xNrW0gAwbYKwm/bEnKmSvu2FXtnFLqdTxN1LVAAkUyhab91LAInnOX0Dg rErADFe9kw1f0RRSlx89BDDXGvVhPl3kn0XQ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/L7LdGSm5NNT7VX4GhYH4GxUJMBjROELDT1h85Zk74Y=; b=VlzgMjsFVd6zMS+KyUzsA3SS/MGxB0m3Ku7RJj5HtxRbtFaWBgLXn2zHHTNddzil4o Hbm8KupmLHqailhh4WavwgD4UFXEP49apCXWrgXYa57DCB1d6WX0RKoDEsMZwlQnGwO7 t+MiAHtvD68sk1RSkmMl2Tq3C5COt0gyS6bLCYyzKbJ3W4GLhkJ/rJO0WxKb1lwNwHCv 3RtEJFs33WiRp6Sn0srRtRIbiad4rQxb0AKDR0pSFkcTF8+ID5LXeFkTGLpI9KrElUTj +jNauho3RkMK9H4/1fe3rZRb4dBtrWLal90rqHXCJnyzxvLxaYcoLuV20qjoMbcNPqRr DhkQ== X-Gm-Message-State: AA+aEWblXrueQqhHyOPKvVk4LcgHOAp1FpGW/FerpADCl3SBecpUkUKP 5i1abAak4KJfr3SUD8qqZxamwPMaF1M= X-Google-Smtp-Source: AFSGD/VKVRtzgjQlVXvT2mFFVFmqExeJ8KLE80frwLlwe9mn5nP3NoegU4i1KaEcusACaO9f82Wrzw== X-Received: by 2002:a63:ea15:: with SMTP id c21mr13952893pgi.361.1545115159726; Mon, 17 Dec 2018 22:39:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:42 -0800 Message-Id: <20181218063911.2112-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 05/34] tcg: Add opcodes for vector saturated arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op.h | 4 ++ tcg/tcg-opc.h | 4 ++ tcg/tcg.h | 1 + tcg/tcg-op-gvec.c | 84 ++++++++++++++++++++++++++++++---------- tcg/tcg-op-vec.c | 34 ++++++++++++++-- tcg/tcg.c | 5 +++ 8 files changed, 110 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f966a4fcb3..98556bcf22 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -135,6 +135,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index f378d29568..44381062e6 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -185,6 +185,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 0 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 1974bf1cae..90b3193bf3 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -966,6 +966,10 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a, TCGv_vec b); void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index e3a43aabb6..94691e849b 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -221,6 +221,10 @@ DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) +DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) +DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) +DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) +DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) =20 DEF(and_vec, 1, 2, 0, IMPLVEC) DEF(or_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/tcg.h b/tcg/tcg.h index ade692fdf5..c90f65a387 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -183,6 +183,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index c10d3d7b26..0a33f51065 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1678,10 +1678,22 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dof= s, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_ssadd8, .vece =3D MO_8 }, - { .fno =3D gen_helper_gvec_ssadd16, .vece =3D MO_16 }, - { .fno =3D gen_helper_gvec_ssadd32, .vece =3D MO_32 }, - { .fno =3D gen_helper_gvec_ssadd64, .vece =3D MO_64 } + { .fniv =3D tcg_gen_ssadd_vec, + .fno =3D gen_helper_gvec_ssadd8, + .opc =3D INDEX_op_ssadd_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_ssadd_vec, + .fno =3D gen_helper_gvec_ssadd16, + .opc =3D INDEX_op_ssadd_vec, + .vece =3D MO_16 }, + { .fniv =3D tcg_gen_ssadd_vec, + .fno =3D gen_helper_gvec_ssadd32, + .opc =3D INDEX_op_ssadd_vec, + .vece =3D MO_32 }, + { .fniv =3D tcg_gen_ssadd_vec, + .fno =3D gen_helper_gvec_ssadd64, + .opc =3D INDEX_op_ssadd_vec, + .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); @@ -1691,16 +1703,28 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dof= s, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_sssub8, .vece =3D MO_8 }, - { .fno =3D gen_helper_gvec_sssub16, .vece =3D MO_16 }, - { .fno =3D gen_helper_gvec_sssub32, .vece =3D MO_32 }, - { .fno =3D gen_helper_gvec_sssub64, .vece =3D MO_64 } + { .fniv =3D tcg_gen_sssub_vec, + .fno =3D gen_helper_gvec_sssub8, + .opc =3D INDEX_op_sssub_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_sssub_vec, + .fno =3D gen_helper_gvec_sssub16, + .opc =3D INDEX_op_sssub_vec, + .vece =3D MO_16 }, + { .fniv =3D tcg_gen_sssub_vec, + .fno =3D gen_helper_gvec_sssub32, + .opc =3D INDEX_op_sssub_vec, + .vece =3D MO_32 }, + { .fniv =3D tcg_gen_sssub_vec, + .fno =3D gen_helper_gvec_sssub64, + .opc =3D INDEX_op_sssub_vec, + .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 -static void tcg_gen_vec_usadd32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { TCGv_i32 max =3D tcg_const_i32(-1); tcg_gen_add_i32(d, a, b); @@ -1708,7 +1732,7 @@ static void tcg_gen_vec_usadd32_i32(TCGv_i32 d, TCGv_= i32 a, TCGv_i32 b) tcg_temp_free_i32(max); } =20 -static void tcg_gen_vec_usadd32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { TCGv_i64 max =3D tcg_const_i64(-1); tcg_gen_add_i64(d, a, b); @@ -1720,20 +1744,30 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dof= s, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_usadd8, .vece =3D MO_8 }, - { .fno =3D gen_helper_gvec_usadd16, .vece =3D MO_16 }, - { .fni4 =3D tcg_gen_vec_usadd32_i32, + { .fniv =3D tcg_gen_usadd_vec, + .fno =3D gen_helper_gvec_usadd8, + .opc =3D INDEX_op_usadd_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_usadd_vec, + .fno =3D gen_helper_gvec_usadd16, + .opc =3D INDEX_op_usadd_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_usadd_i32, + .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd32, + .opc =3D INDEX_op_usadd_vec, .vece =3D MO_32 }, - { .fni8 =3D tcg_gen_vec_usadd32_i64, + { .fni8 =3D tcg_gen_usadd_i64, + .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd64, + .opc =3D INDEX_op_usadd_vec, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 -static void tcg_gen_vec_ussub32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { TCGv_i32 min =3D tcg_const_i32(0); tcg_gen_sub_i32(d, a, b); @@ -1741,7 +1775,7 @@ static void tcg_gen_vec_ussub32_i32(TCGv_i32 d, TCGv_= i32 a, TCGv_i32 b) tcg_temp_free_i32(min); } =20 -static void tcg_gen_vec_ussub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { TCGv_i64 min =3D tcg_const_i64(0); tcg_gen_sub_i64(d, a, b); @@ -1753,13 +1787,23 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dof= s, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { - { .fno =3D gen_helper_gvec_ussub8, .vece =3D MO_8 }, - { .fno =3D gen_helper_gvec_ussub16, .vece =3D MO_16 }, - { .fni4 =3D tcg_gen_vec_ussub32_i32, + { .fniv =3D tcg_gen_ussub_vec, + .fno =3D gen_helper_gvec_ussub8, + .opc =3D INDEX_op_ussub_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_ussub_vec, + .fno =3D gen_helper_gvec_ussub16, + .opc =3D INDEX_op_ussub_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_ussub_i32, + .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub32, + .opc =3D INDEX_op_ussub_vec, .vece =3D MO_32 }, - { .fni8 =3D tcg_gen_vec_ussub32_i64, + { .fni8 =3D tcg_gen_ussub_i64, + .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub64, + .opc =3D INDEX_op_ussub_vec, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index d77fdf7c1d..675aa09258 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -386,7 +386,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, } } =20 -void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGOpcode opc) { TCGTemp *rt =3D tcgv_vec_temp(r); TCGTemp *at =3D tcgv_vec_temp(a); @@ -399,11 +400,36 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) =20 tcg_debug_assert(at->base_type >=3D type); tcg_debug_assert(bt->base_type >=3D type); - can =3D tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece); + can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { - vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi); + vec_gen_3(opc, type, vece, ri, ai, bi); } else { tcg_debug_assert(can < 0); - tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi); + tcg_expand_vec_op(opc, type, vece, ri, ai, bi); } } + +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_mul_vec); +} + +void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_ssadd_vec); +} + +void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_usadd_vec); +} + +void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sssub_vec); +} + +void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_ussub_vec); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 963cb37892..f2cf60425b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1607,6 +1607,11 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return have_vec && TCG_TARGET_HAS_shv_vec; + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return have_vec && TCG_TARGET_HAS_sat_vec; =20 default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115712354108.67368762413946; Mon, 17 Dec 2018 22:48:32 -0800 (PST) Received: from localhost ([::1]:52066 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9B2-0008Gi-L5 for importer@patchew.org; Tue, 18 Dec 2018 01:48:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92t-0001fJ-Rp for qemu-devel@nongnu.org; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b6Irb6oSf56jzkl09+An3n/u5tlRfj1yzixgXmHIxxE=; b=E7Oy0q2Yzm5pQVlbO7R0eF2H97xpXz3TaxnOlJMsO2/6zf4qEk+g3hyXlswQbnqSVB faB9EhKS0mi7SFpMCToAKY/Idofc3PcfSsak6rnkkKcqg1/bPFXYIUCy7sILa7LFyTDJ nkYbXL3R7VXcfnomJfcl6ih3TE4TmBTChRA6c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b6Irb6oSf56jzkl09+An3n/u5tlRfj1yzixgXmHIxxE=; b=RtIsBW70x2dYnzyirMdK9WdYyovuPcdlL/7PeR7Dm68JpejHUGOSfVO/QscoDJI3I2 HDw3UM4j5EpJir5q7Ts3TBpcSYFv8kxYHtufp8/f9yghYXwsvHxe5HFgP0UHGv82DIU9 n41dBm26zBTeJO69ghmEwPd/9L43Dv5JgKxSsr9pNM3eqrGQvMH5A89vTVBhXi05YdK3 KrQTHfYU2yQwwUlSFhrzSFXQdYlXH5ujO8WeCA/SnnndTd1eRyax7SaVZl3GPOCn+m62 3vkmgnPIvx+LUcZvNq9Id6bASp2qvx9ESKEH26pqYrnmgtfEkF10jPF5aTjPv/aRt0XP cRvw== X-Gm-Message-State: AA+aEWaE8FvLZB7NGwyy3Xc6bixXBkkkyHRu20Xb/9IffXhJXUoJF76w 4wS3IFWePYEf0sg/O23FM/QZckVGgpg= X-Google-Smtp-Source: AFSGD/XKZaoNv6eQnY9m+TXN2NhyyaHn8Q+FTp+CI5Qha4hPN/bDuShluo3O99Tn4H5rHvDbFBlb6w== X-Received: by 2002:a65:49cd:: with SMTP id t13mr14937083pgs.376.1545115161073; Mon, 17 Dec 2018 22:39:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:43 -0800 Message-Id: <20181218063911.2112-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 06/34] tcg/i386: Implement vector saturating arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only MO_8 and MO_16 are implemented, since that's all the instruction set provides. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 44381062e6..f50234d97b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -185,7 +185,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c21c3272f2..3571483bae 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -377,6 +377,10 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_PADDW (0xfd | P_EXT | P_DATA16) #define OPC_PADDD (0xfe | P_EXT | P_DATA16) #define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PADDSB (0xec | P_EXT | P_DATA16) +#define OPC_PADDSW (0xed | P_EXT | P_DATA16) +#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) +#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) #define OPC_PAND (0xdb | P_EXT | P_DATA16) #define OPC_PANDN (0xdf | P_EXT | P_DATA16) #define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) @@ -408,6 +412,10 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) #define OPC_PSUBD (0xfa | P_EXT | P_DATA16) #define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) +#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) +#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) +#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) #define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) #define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) #define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) @@ -2591,9 +2599,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const add_insn[4] =3D { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ }; + static int const ssadd_insn[4] =3D { + OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 + }; + static int const usadd_insn[4] =3D { + OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 + }; static int const sub_insn[4] =3D { OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ }; + static int const sssub_insn[4] =3D { + OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 + }; + static int const ussub_insn[4] =3D { + OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 + }; static int const mul_insn[4] =3D { OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2 }; @@ -2631,9 +2651,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_add_vec: insn =3D add_insn[vece]; goto gen_simd; + case INDEX_op_ssadd_vec: + insn =3D ssadd_insn[vece]; + goto gen_simd; + case INDEX_op_usadd_vec: + insn =3D usadd_insn[vece]; + goto gen_simd; case INDEX_op_sub_vec: insn =3D sub_insn[vece]; goto gen_simd; + case INDEX_op_sssub_vec: + insn =3D sssub_insn[vece]; + goto gen_simd; + case INDEX_op_ussub_vec: + insn =3D ussub_insn[vece]; + goto gen_simd; case INDEX_op_mul_vec: insn =3D mul_insn[vece]; goto gen_simd; @@ -3007,6 +3039,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_or_vec: case INDEX_op_xor_vec: case INDEX_op_andc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3074,6 +3110,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } return 1; =20 + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return vece <=3D MO_16; + default: return 0; } --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vTZ65RErzu8a1C8Iyw6z0sxkXcGfUsAurzfsZ7mejUs=; b=GdBjBZy8sp99lWRLiCOOG+0mEi+qZmh0WrnZtoipIMNcFEKeumCHijysMVkwHk8gVl FyEP0cY4qDUf2vo2mIFTw9QTC2BROz6nogvasa9Tf7MIkfudnHj9feZLRgYf1Q88zFcU QAeNy5Yvop4BEA1RkX8M6NueEc1d+upf7FK8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vTZ65RErzu8a1C8Iyw6z0sxkXcGfUsAurzfsZ7mejUs=; b=Pv9qe+OfnMGowkuvnNIH21ks++tGA5kHHHHTa13KkuXkStXeYtc5pbvgsIa1hRnLG/ tFQWnKB/pYp05A2k5cBuYpfEfMSoCJwVr3p0RtQMns/jXdfw9swiIQvnI/ot+Fx7Z7xP 2QPDlT+eVAVKGR6r1S2TUrgmvSi5CKY5m/rKW451wL1uFtHsIVG+yGj76tg87PDQP/DK vP+SmmvvRBOvIrQNlJDs872ZKhgjsJLxid85tWt5R/aHpqOBGE8FzVcBEgrcOPpMhhLb aXgqhMSpwTMJSELizJ904EhniNIPBvTLURZPTFdjCY3of3aGpOCX81+2r6iqMUtHoPXe 2hJg== X-Gm-Message-State: AA+aEWaxk6/F11jPn+DEt/k+/NPgweCOjrk+PPcCMyHEX93bhHU/JdNf bdUSTB2bep3EugmAHTXnroA2tYU0SKc= X-Google-Smtp-Source: AFSGD/V9USsBuQUt8PX7rrRGwtckFqNw22LxnG4QRMXkP8QDGkv7hr5jMKnocm2+pKfSa6uvuU+ynQ== X-Received: by 2002:a17:902:690c:: with SMTP id j12mr15286432plk.206.1545115162372; Mon, 17 Dec 2018 22:39:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:44 -0800 Message-Id: <20181218063911.2112-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 20 ++++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op-gvec.h | 10 ++ tcg/tcg-op.h | 4 + tcg/tcg-opc.h | 4 + tcg/tcg.h | 1 + accel/tcg/tcg-runtime-gvec.c | 224 +++++++++++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 108 +++++++++++++++++ tcg/tcg-op-vec.c | 20 ++++ tcg/tcg.c | 5 + 11 files changed, 398 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 835ddfebb2..dfe325625c 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -200,6 +200,26 @@ DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void= , ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_smin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_smax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umin8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umin16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umin32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umin64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umax8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umax16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umax32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umax64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 98556bcf22..545a6eec75 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -136,6 +136,7 @@ typedef enum { #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index f50234d97b..efbd5a6fc9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -186,6 +186,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 +#define TCG_TARGET_HAS_minmax_vec 0 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 2cb447112e..4734eef7de 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -234,6 +234,16 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 +/* Min/max. */ +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 90b3193bf3..042c45e807 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -970,6 +970,10 @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_vec b); void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 94691e849b..691eddebdf 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -225,6 +225,10 @@ DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_= sat_vec)) DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) +DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) +DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) +DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) +DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) =20 DEF(and_vec, 1, 2, 0, IMPLVEC) DEF(or_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/tcg.h b/tcg/tcg.h index c90f65a387..b5bec3abf8 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -184,6 +184,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index d1802467d5..9358749741 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1028,3 +1028,227 @@ void HELPER(gvec_ussub64)(void *d, void *a, void *b= , uint32_t desc) } clear_high(d, oprsz, desc); } + +void HELPER(gvec_smin8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int8_t)) { + int8_t aa =3D *(int8_t *)(a + i); + int8_t bb =3D *(int8_t *)(b + i); + int8_t dd =3D aa < bb ? aa : bb; + *(int8_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smin16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + int16_t aa =3D *(int16_t *)(a + i); + int16_t bb =3D *(int16_t *)(b + i); + int16_t dd =3D aa < bb ? aa : bb; + *(int16_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smin32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { + int32_t aa =3D *(int32_t *)(a + i); + int32_t bb =3D *(int32_t *)(b + i); + int32_t dd =3D aa < bb ? aa : bb; + *(int32_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smin64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { + int64_t aa =3D *(int64_t *)(a + i); + int64_t bb =3D *(int64_t *)(b + i); + int64_t dd =3D aa < bb ? aa : bb; + *(int64_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smax8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int8_t)) { + int8_t aa =3D *(int8_t *)(a + i); + int8_t bb =3D *(int8_t *)(b + i); + int8_t dd =3D aa > bb ? aa : bb; + *(int8_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smax16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + int16_t aa =3D *(int16_t *)(a + i); + int16_t bb =3D *(int16_t *)(b + i); + int16_t dd =3D aa > bb ? aa : bb; + *(int16_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smax32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { + int32_t aa =3D *(int32_t *)(a + i); + int32_t bb =3D *(int32_t *)(b + i); + int32_t dd =3D aa > bb ? aa : bb; + *(int32_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_smax64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { + int64_t aa =3D *(int64_t *)(a + i); + int64_t bb =3D *(int64_t *)(b + i); + int64_t dd =3D aa > bb ? aa : bb; + *(int64_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umin8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t aa =3D *(uint8_t *)(a + i); + uint8_t bb =3D *(uint8_t *)(b + i); + uint8_t dd =3D aa < bb ? aa : bb; + *(uint8_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umin16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint16_t aa =3D *(uint16_t *)(a + i); + uint16_t bb =3D *(uint16_t *)(b + i); + uint16_t dd =3D aa < bb ? aa : bb; + *(uint16_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umin32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint32_t aa =3D *(uint32_t *)(a + i); + uint32_t bb =3D *(uint32_t *)(b + i); + uint32_t dd =3D aa < bb ? aa : bb; + *(uint32_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umin64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint64_t aa =3D *(uint64_t *)(a + i); + uint64_t bb =3D *(uint64_t *)(b + i); + uint64_t dd =3D aa < bb ? aa : bb; + *(uint64_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umax8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t aa =3D *(uint8_t *)(a + i); + uint8_t bb =3D *(uint8_t *)(b + i); + uint8_t dd =3D aa > bb ? aa : bb; + *(uint8_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umax16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint16_t aa =3D *(uint16_t *)(a + i); + uint16_t bb =3D *(uint16_t *)(b + i); + uint16_t dd =3D aa > bb ? aa : bb; + *(uint16_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umax32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint32_t aa =3D *(uint32_t *)(a + i); + uint32_t bb =3D *(uint32_t *)(b + i); + uint32_t dd =3D aa > bb ? aa : bb; + *(uint32_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint64_t aa =3D *(uint64_t *)(a + i); + uint64_t bb =3D *(uint64_t *)(b + i); + uint64_t dd =3D aa > bb ? aa : bb; + *(uint64_t *)(d + i) =3D dd; + } + clear_high(d, oprsz, desc); +} diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0a33f51065..3ee44fcb75 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1810,6 +1810,114 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dof= s, uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_smin_vec, + .fno =3D gen_helper_gvec_smin8, + .opc =3D INDEX_op_smin_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_smin_vec, + .fno =3D gen_helper_gvec_smin16, + .opc =3D INDEX_op_smin_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_smin_i32, + .fniv =3D tcg_gen_smin_vec, + .fno =3D gen_helper_gvec_smin32, + .opc =3D INDEX_op_smin_vec, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_smin_i64, + .fniv =3D tcg_gen_smin_vec, + .fno =3D gen_helper_gvec_smin64, + .opc =3D INDEX_op_smin_vec, + .vece =3D MO_64 } + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_umin_vec, + .fno =3D gen_helper_gvec_umin8, + .opc =3D INDEX_op_umin_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_umin_vec, + .fno =3D gen_helper_gvec_umin16, + .opc =3D INDEX_op_umin_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_umin_i32, + .fniv =3D tcg_gen_umin_vec, + .fno =3D gen_helper_gvec_umin32, + .opc =3D INDEX_op_umin_vec, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_umin_i64, + .fniv =3D tcg_gen_umin_vec, + .fno =3D gen_helper_gvec_umin64, + .opc =3D INDEX_op_umin_vec, + .vece =3D MO_64 } + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_smax_vec, + .fno =3D gen_helper_gvec_smax8, + .opc =3D INDEX_op_smax_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_smax_vec, + .fno =3D gen_helper_gvec_smax16, + .opc =3D INDEX_op_smax_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_smax_i32, + .fniv =3D tcg_gen_smax_vec, + .fno =3D gen_helper_gvec_smax32, + .opc =3D INDEX_op_smax_vec, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_smax_i64, + .fniv =3D tcg_gen_smax_vec, + .fno =3D gen_helper_gvec_smax64, + .opc =3D INDEX_op_smax_vec, + .vece =3D MO_64 } + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_umax_vec, + .fno =3D gen_helper_gvec_umax8, + .opc =3D INDEX_op_umax_vec, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_umax_vec, + .fno =3D gen_helper_gvec_umax16, + .opc =3D INDEX_op_umax_vec, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_umax_i32, + .fniv =3D tcg_gen_umax_vec, + .fno =3D gen_helper_gvec_umax32, + .opc =3D INDEX_op_umax_vec, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_umax_i64, + .fniv =3D tcg_gen_umax_vec, + .fno =3D gen_helper_gvec_umax64, + .opc =3D INDEX_op_umax_vec, + .vece =3D MO_64 } + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Perform a vector negation using normal negation and a mask. Compare gen_subv_mask above. */ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 675aa09258..36f35022ac 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -433,3 +433,23 @@ void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_ussub_vec); } + +void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_smin_vec); +} + +void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_umin_vec); +} + +void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_smax_vec); +} + +void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_umax_vec); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index f2cf60425b..2ee031fcf7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1612,6 +1612,11 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_sssub_vec: case INDEX_op_ussub_vec: return have_vec && TCG_TARGET_HAS_sat_vec; + case INDEX_op_smin_vec: + case INDEX_op_umin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umax_vec: + return have_vec && TCG_TARGET_HAS_minmax_vec; =20 default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115521324165.79449278907077; Mon, 17 Dec 2018 22:45:21 -0800 (PST) Received: from localhost ([::1]:52046 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ983-0005xW-VC for importer@patchew.org; Tue, 18 Dec 2018 01:45:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92j-0001VK-Qk for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92g-0002ZG-37 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:47 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92a-0001xM-5w for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:42 -0500 Received: by mail-pl1-x641.google.com with SMTP id a14so7350252plm.12 for ; Mon, 17 Dec 2018 22:39:24 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mNrweq0qvnl/lPO7L+11SNwKquBI6mLakgAe7C1QIBc=; b=QWr2GzYjP754Eeo0jkkEqU4R1zjuUXM2jLTlA4Z+QoCCVNsS62Mp68C2l74+C1bYXO sPEN1iVTZO/aB57c5mv7E7iwhZLby7Mh5sbcCjW6mRmCskYS6eUMLiU3BYsAjHTU9Mad jysySe5IT/uz0d36etdYWdYGoMtfDocScgNOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mNrweq0qvnl/lPO7L+11SNwKquBI6mLakgAe7C1QIBc=; b=NWf2qzNrLIn6cERImHzNa8LUMTbYSqbKHJlU7zzwwKJzMikAIGDP17cVLN2g0Zw9xS k4W4NhYGI0hwkLw6GXGqXYQcmqIt35VdDn7LEVKGn5PiMs4zKlq9Aj6aA/rD8UIFRfqD e+AXbDz0bu/VpakBd98MIIfAC6FY/jHKB4+RQ4kkUEEh/JRAhMkKqi3tlue2HS4XBc4X VcYJqU3jPtygU2PDaSEhZORKaBk7M4kiY3ZQsBz+PcH9Nam0YdwnM2G+Yania/RMOEyp BTMq5diHdRvvQ4ij+qNrk1IhkI6BA51g+jjcx4YOFM709C9q5b+4s3Ntq/fv+1JP+wCK LPZQ== X-Gm-Message-State: AA+aEWalAwH+P37dRvzOPi/F65B2DHA5JuxZxanVFjp93oDpyLVWa4bP KTv9rxBz6eixJDbiE0euAk9IpJsfsmw= X-Google-Smtp-Source: AFSGD/XA5vBg7267tFTp4UKe4nTOP0PX3xUqzEc/+IqWhVboXwkl3j1jf+5pT3SPooOWzdMDZXj+jw== X-Received: by 2002:a17:902:29a7:: with SMTP id h36mr15613911plb.244.1545115163654; Mon, 17 Dec 2018 22:39:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:45 -0800 Message-Id: <20181218063911.2112-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 08/34] tcg/i386: Implement vector minmax arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction set does not directly provide MO_64. We can still implement signed 64-bit with comparison and vpblendvb. Since the ISA has no unsigned comparison, it would take 4 insns to implement unsigned 64-bit, which is probably quicker as integers. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 64 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index efbd5a6fc9..7995fe3eab 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -186,7 +186,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3571483bae..c56753763a 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -392,6 +392,18 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) #define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) #define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) +#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) +#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) +#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) +#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) +#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) +#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) +#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) +#define OPC_PMINSW (0xea | P_EXT | P_DATA16) +#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) +#define OPC_PMINUB (0xda | P_EXT | P_DATA16) +#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) +#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) #define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) #define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) #define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) @@ -2638,6 +2650,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const packus_insn[4] =3D { OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 }; + static int const smin_insn[4] =3D { + OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2 + }; + static int const smax_insn[4] =3D { + OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2 + }; + static int const umin_insn[4] =3D { + OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2 + }; + static int const umax_insn[4] =3D { + OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2678,6 +2702,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_xor_vec: insn =3D OPC_PXOR; goto gen_simd; + case INDEX_op_smin_vec: + insn =3D smin_insn[vece]; + goto gen_simd; + case INDEX_op_umin_vec: + insn =3D umin_insn[vece]; + goto gen_simd; + case INDEX_op_smax_vec: + insn =3D smax_insn[vece]; + goto gen_simd; + case INDEX_op_umax_vec: + insn =3D umax_insn[vece]; + goto gen_simd; case INDEX_op_x86_punpckl_vec: insn =3D punpckl_insn[vece]; goto gen_simd; @@ -3043,6 +3079,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: case INDEX_op_ussub_vec: + case INDEX_op_smin_vec: + case INDEX_op_umin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umax_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3115,6 +3155,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_ussub_vec: return vece <=3D MO_16; + case INDEX_op_smin_vec: + case INDEX_op_smax_vec: + return vece <=3D MO_32 ? 1 : -1; + case INDEX_op_umin_vec: + case INDEX_op_umax_vec: + return vece <=3D MO_32; =20 default: return 0; @@ -3370,6 +3416,24 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, } break; =20 + case INDEX_op_smin_vec: + case INDEX_op_smax_vec: + tcg_debug_assert(vece =3D=3D MO_64); + a1 =3D va_arg(va, TCGArg); + a2 =3D va_arg(va, TCGArg); + t1 =3D tcg_temp_new_vec(type); + vec_gen_4(INDEX_op_cmp_vec, type, MO_64, + tcgv_vec_arg(t1), a1, a2, TCG_COND_GT); + if (opc =3D=3D INDEX_op_smin_vec) { + vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_64, + tcgv_vec_arg(v0), a2, a1, tcgv_vec_arg(t1)); + } else { + vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_64, + tcgv_vec_arg(v0), a1, a2, tcgv_vec_arg(t1)); + } + tcg_temp_free_vec(t1); + break; + default: break; } --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115348876536.2155950196301; Mon, 17 Dec 2018 22:42:28 -0800 (PST) Received: from localhost ([::1]:52029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ95H-0003MS-FD for importer@patchew.org; Tue, 18 Dec 2018 01:42:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92c-0001Tm-8I for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92X-0002ES-Tf for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:40 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:42365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92V-0001y7-Ph for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:37 -0500 Received: by mail-pf1-x442.google.com with SMTP id 64so7641146pfr.9 for ; Mon, 17 Dec 2018 22:39:26 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FerA1jdUPmyzDQdllgAlLCmDGQMUpOXaXKd/jiLP8aM=; b=a0FTROsScdVNojLTeAg6PkNpTYPVYwt3hiHhr3aUh2RS+yQuodOj+8mjiV2o0FhjRt qrW2JuR7crj9S0DW2rDJ8KNjg5bEpUY6x2c9xSg5924zYH3J2lefhOeghE/08Vn9QHh6 vF0livydGPAe9SdIvTchT6P6j1/YAwjxrxO4E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FerA1jdUPmyzDQdllgAlLCmDGQMUpOXaXKd/jiLP8aM=; b=O29rUjLccKR0NjuS5lAvD/wk8Pa5e8vngOedwcyQuqUGnyphFfMoTsLIii03hc0GUL ebclzk3IP2E4o+abK6vx9Ya29dWR8jebdRa90lWVmdSJ93NG2hMK2auCHqvbj/iBltNk /YzYenLT661B21nkf5/CX/u36rdk5cs8/JrSxnVQZcn5+qctFOgw9GCnSXD/ixWYOz1D pVmepI4HYHfQVz9qof1XdKuB4gg7ZQBZFSLjr0HanuJSXHu3xGJx/uOyvf9eri/eq7Uc yvDL1aPAhNV5/YcBGvPNChjxaoENJnvnHyz0onKPrhK1XPcWelnZWLK4k7azv35ucQjR HRVw== X-Gm-Message-State: AA+aEWbsGEX4JhIswty2/QvWJVdqR0N+nLvd7hQNxBn98BPfP4QpSumt OPq1xkV7pTSIDcbWptRlzIVAWIQcE+Y= X-Google-Smtp-Source: AFSGD/VK0J4ujqfmUeHV+AZrFAPXTA6u2hvUjMzqp+eZLoLmYBcc2FqKDd0TzU3W0udfNkqMkY6KNQ== X-Received: by 2002:a62:1484:: with SMTP id 126mr1174288pfu.257.1545115165174; Mon, 17 Dec 2018 22:39:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:46 -0800 Message-Id: <20181218063911.2112-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 09/34] target/arm: Use vector minmax expanders for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6f8c1b4f..bef21ada71 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10452,6 +10452,20 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) } =20 switch (opcode) { + case 0x0c: /* SMAX, UMAX */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); + } + return; + case 0x0d: /* SMIN, UMIN */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); + } + return; case 0x10: /* ADD, SUB */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); @@ -10613,27 +10627,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) genenvfn =3D fns[size][u]; break; } - case 0xc: /* SMAX, UMAX */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, - { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, - { tcg_gen_smax_i32, tcg_gen_umax_i32 }, - }; - genfn =3D fns[size][u]; - break; - } - - case 0xd: /* SMIN, UMIN */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, - { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, - { tcg_gen_smin_i32, tcg_gen_umin_i32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0xe: /* SABD, UABD */ case 0xf: /* SABA, UABA */ { --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116049451264.8737392565298; Mon, 17 Dec 2018 22:54:09 -0800 (PST) Received: from localhost ([::1]:52097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9GU-0004Xi-8v for importer@patchew.org; Tue, 18 Dec 2018 01:54:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92v-0001fa-Ts for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92q-0002qK-T9 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:01 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:42367) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92q-0001yb-EX for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:56 -0500 Received: by mail-pf1-x444.google.com with SMTP id 64so7641172pfr.9 for ; Mon, 17 Dec 2018 22:39:27 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kSo0oKSo1CsoY2QHLe3rTxnPQOT4r7h09gkl4JXYPGw=; b=VZVdRbIRFTzOUuKTyR7WE35uAwkuB2LxMLTPNmJvjBYEB8XOgKzgse77gw0q4SrXJi GG2QaSnVpE6RJ7A4xqBHdmeeVfK6wCPg4B1YR0fyOkUVvXAsoRSt1ZITnu9787R06FOz Dfoj3FtpaM/ut/1H7wLbRvG3AUT57Ds9wdrfA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kSo0oKSo1CsoY2QHLe3rTxnPQOT4r7h09gkl4JXYPGw=; b=BcwDAcGXfUloKDXCMf+7aMj9UGbQ2IMYx/Orv5Tgezlpt2ZMaE047cQ9Vou28l0xqW ngWrV7+hxJPsc6TYbJ/T2n6XMgIwButMIhvY4OkmZLfKvVVWLjb0YHVR6ofZMnZRw+co AQgqkFXLyJU4NAtXN4pMRBq5marg+QcVlHLCYJSYyU5X4lPC8GGe8Q0VlVWzf9bDbZX0 HLU1dlQ0/7QCXi+lXAL2gK1jFtdtGmlxSoTJTko27S0RKTeTIOxyCofmU5QYD3bpvOXa R60cyYVan77t0nU3ydtoCIlyx25vxNoHMS40cjz/2fmzKSRrkU9nc5MQWBVPmi8rL9sD HoLA== X-Gm-Message-State: AA+aEWaD24xePDucb0DTwPUW/O9Wscm/uycF6KnJaUvuLdIXFFVk4vDc fM/0A/9v+Pp8drvj6B9Dvp6u0e8hf9A= X-Google-Smtp-Source: AFSGD/VvlDDQ1naI7sMJFy3lYbcKj6gIJfW0cYcs4oZJtY2rR7RRvYCPeaojtZGEPGIhLoWn/2slkg== X-Received: by 2002:a62:d148:: with SMTP id t8mr16003007pfl.52.1545115166231; Mon, 17 Dec 2018 22:39:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:47 -0800 Message-Id: <20181218063911.2112-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 10/34] target/arm: Use vector minmax expanders for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 33b1860148..f3f172f384 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6368,6 +6368,25 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); return 0; + + case NEON_3R_VMAX: + if (u) { + tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; + case NEON_3R_VMIN: + if (u) { + tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; } =20 if (size =3D=3D 3) { @@ -6533,12 +6552,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_3R_VQRSHL: GEN_NEON_INTEGER_OP_ENV(qrshl); break; - case NEON_3R_VMAX: - GEN_NEON_INTEGER_OP(max); - break; - case NEON_3R_VMIN: - GEN_NEON_INTEGER_OP(min); - break; case NEON_3R_VABD: GEN_NEON_INTEGER_OP(abd); break; --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116765835847.3225731791501; Mon, 17 Dec 2018 23:06:05 -0800 (PST) Received: from localhost ([::1]:52186 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9S6-0006gS-4u for importer@patchew.org; Tue, 18 Dec 2018 02:06:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ931-0001nL-Tw for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92p-0002o3-By for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:07 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:34997) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92o-0001zY-NN for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:55 -0500 Received: by mail-pf1-x42e.google.com with SMTP id z9so7657866pfi.2 for ; Mon, 17 Dec 2018 22:39:29 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B6cQzLc8bFYMOTUWsaHT8UKWMCkKLCPcx9Rr7GUW2kU=; b=CkooyhQ4OtYxq0IEed36Yxl9H8YxF0XoAkLQ7US5/35g4DndlDxpY+qxmgmHgdaidd oVZGkMDygApzeK1fXjXb8efcwU9p8LCvHpxdbl05QpCqfoC8CROaE1BeC3lN6g31eB1v 9stshdMF9ogwpOXArFinzOzsQYZtZ7ytbYJJs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B6cQzLc8bFYMOTUWsaHT8UKWMCkKLCPcx9Rr7GUW2kU=; b=JuAaG3RHwWxgZHCpTcDo9oH5IaewiwVmaEkQzZ/f41FoGPTcSwRZjNqB/kIKmJlt02 50W5y04Yz0GMcEN+fvuBJlpoL6PbyDWOK8i0ajdKhPq1xXUeC0jTz/JCQtWVtJbv+eBR 3Zd9oncSH0rhe3vleXmvvSAnEEutUe64lljNG9VA71IlOlzJMC6cIpk7TdiuLwmF2Ft7 DczGJOarOOhFG5LaoKSEnXvmwhCX/ncR7w1uTfSYeXRbF1vefm0M/1un6f5loE3hitkt 7Mn24wpRpbr8FmYqamRbYPQBhevhN3CTx1bDPjMyTcvH5c6yxcwWC8G/oCL0KZ4F6fTz S8OQ== X-Gm-Message-State: AA+aEWbwxgWsdynWLYzg4RAw5Tz24oPQxBKBsJgOfuQouULIjFzbkTZf sA2VPBRXGOJdfOL7Hd/oN0cwI2uYnfk= X-Google-Smtp-Source: AFSGD/X227m8CRdIsc1xqn8ef3t97b6mfa04MSInhBwcsAJRJafEZZ5nEjU3fLMnMYibXwTgedJU7A== X-Received: by 2002:a62:d743:: with SMTP id v3mr994336pfl.34.1545115167847; Mon, 17 Dec 2018 22:39:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:48 -0800 Message-Id: <20181218063911.2112-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH 11/34] target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland These helpers allow us to move FP register values to/from the specified TCG= v_i64 argument in the VSR helpers to be introduced shortly. To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland Message-Id: <20181217122405.18732-2-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/translate.c | 10 + target/ppc/translate/fp-impl.inc.c | 490 ++++++++++++++++++++++------- 2 files changed, 390 insertions(+), 110 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 2b37910248..1d4bf624a3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6694,6 +6694,16 @@ static inline void gen_##name(DisasContext *ctx) = \ GEN_TM_PRIV_NOOP(treclaim); GEN_TM_PRIV_NOOP(trechkpt); =20 +static inline void get_fpr(TCGv_i64 dst, int regno) +{ + tcg_gen_mov_i64(dst, cpu_fpr[regno]); +} + +static inline void set_fpr(int regno, TCGv_i64 src) +{ + tcg_gen_mov_i64(cpu_fpr[regno], src); +} + #include "translate/fp-impl.inc.c" =20 #include "translate/vmx-impl.inc.c" diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-i= mpl.inc.c index 08770ba9f5..04b8733055 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -34,24 +34,38 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ + TCGv_i64 t0; = \ + TCGv_i64 t1; = \ + TCGv_i64 t2; = \ + TCGv_i64 t3; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i64(); = \ + t2 =3D tcg_temp_new_i64(); = \ + t3 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rA(ctx->opcode)], = \ - cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); = \ + get_fpr(t0, rA(ctx->opcode)); = \ + get_fpr(t1, rC(ctx->opcode)); = \ + get_fpr(t2, rB(ctx->opcode)); = \ + gen_helper_f##op(t3, cpu_env, t0, t1, t2); = \ if (isfloat) { = \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rD(ctx->opcode)]); = \ + get_fpr(t0, rD(ctx->opcode)); = \ + gen_helper_frsp(t3, cpu_env, t0); = \ } = \ + set_fpr(rD(ctx->opcode), t3); = \ if (set_fprf) { = \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); = \ + gen_compute_fprf_float64(t3); = \ } = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ + tcg_temp_free_i64(t0); = \ + tcg_temp_free_i64(t1); = \ + tcg_temp_free_i64(t2); = \ + tcg_temp_free_i64(t3); = \ } =20 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) = \ @@ -61,24 +75,34 @@ _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, t= ype); #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ + TCGv_i64 t0; = \ + TCGv_i64 t1; = \ + TCGv_i64 t2; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i64(); = \ + t2 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rA(ctx->opcode)], = \ - cpu_fpr[rB(ctx->opcode)]); = \ + get_fpr(t0, rA(ctx->opcode)); = \ + get_fpr(t1, rB(ctx->opcode)); = \ + gen_helper_f##op(t2, cpu_env, t0, t1); = \ if (isfloat) { = \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rD(ctx->opcode)]); = \ + get_fpr(t0, rD(ctx->opcode)); = \ + gen_helper_frsp(t2, cpu_env, t0); = \ } = \ + set_fpr(rD(ctx->opcode), t2); = \ if (set_fprf) { = \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); = \ + gen_compute_fprf_float64(t2); = \ } = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ + tcg_temp_free_i64(t0); = \ + tcg_temp_free_i64(t1); = \ + tcg_temp_free_i64(t2); = \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) = \ _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); = \ @@ -87,24 +111,35 @@ _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_= fprf, type); #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ + TCGv_i64 t0; = \ + TCGv_i64 t1; = \ + TCGv_i64 t2; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i64(); = \ + t2 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rA(ctx->opcode)], = \ - cpu_fpr[rC(ctx->opcode)]); = \ + get_fpr(t0, rA(ctx->opcode)); = \ + get_fpr(t1, rC(ctx->opcode)); = \ + gen_helper_f##op(t2, cpu_env, t0, t1); = \ + set_fpr(rD(ctx->opcode), t2); = \ if (isfloat) { = \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rD(ctx->opcode)]); = \ + get_fpr(t0, rD(ctx->opcode)); = \ + gen_helper_frsp(t2, cpu_env, t0); = \ + set_fpr(rD(ctx->opcode), t2); = \ } = \ if (set_fprf) { = \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); = \ + gen_compute_fprf_float64(t2); = \ } = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ + tcg_temp_free_i64(t0); = \ + tcg_temp_free_i64(t1); = \ + tcg_temp_free_i64(t2); = \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) = \ _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); = \ @@ -113,37 +148,51 @@ _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set= _fprf, type); #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ + TCGv_i64 t0; = \ + TCGv_i64 t1; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ - gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rB(ctx->opcode)]); = \ + get_fpr(t0, rB(ctx->opcode)); = \ + gen_helper_f##name(t1, cpu_env, t0); = \ + set_fpr(rD(ctx->opcode), t1); = \ if (set_fprf) { = \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); = \ + gen_compute_fprf_float64(t1); = \ } = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ + tcg_temp_free_i64(t0); = \ + tcg_temp_free_i64(t1); = \ } =20 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) = \ static void gen_f##name(DisasContext *ctx) = \ { = \ + TCGv_i64 t0; = \ + TCGv_i64 t1; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ + t1 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ - gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, = \ - cpu_fpr[rB(ctx->opcode)]); = \ + get_fpr(t0, rB(ctx->opcode)); = \ + gen_helper_f##name(t1, cpu_env, t0); = \ + set_fpr(rD(ctx->opcode), t1); = \ if (set_fprf) { = \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); = \ + gen_compute_fprf_float64(t1); = \ } = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ + tcg_temp_free_i64(t0); = \ + tcg_temp_free_i64(t1); = \ } =20 /* fadd - fadds */ @@ -165,19 +214,25 @@ GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE= ); /* frsqrtes */ static void gen_frsqrtes(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_frsqrte(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /* fsel */ @@ -189,34 +244,47 @@ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); /* fsqrt */ static void gen_fsqrt(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 static void gen_fsqrts(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /*** Floating-Point multiply-and-add = ***/ @@ -268,21 +336,32 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); =20 static void gen_ftdiv(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)]); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 static void gen_ftsqrt(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]= ); + t0 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } =20 =20 @@ -293,32 +372,46 @@ static void gen_ftsqrt(DisasContext *ctx) static void gen_fcmpo(DisasContext *ctx) { TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); crf =3D tcg_const_i32(crfD(ctx->opcode)); - gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], crf); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpo(cpu_env, t0, t1, crf); tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /* fcmpu */ static void gen_fcmpu(DisasContext *ctx) { TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); crf =3D tcg_const_i32(crfD(ctx->opcode)); - gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], crf); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpu(cpu_env, t0, t1, crf); tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /*** Floating-point move = ***/ @@ -326,100 +419,153 @@ static void gen_fcmpu(DisasContext *ctx) /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ static void gen_fabs(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - ~(1ULL << 63)); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_andi_i64(t1, t0, ~(1ULL << 63)); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /* fmr - fmr. */ /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ static void gen_fmr(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); + t0 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + set_fpr(rD(ctx->opcode), t0); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); } =20 /* fnabs */ /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ static void gen_fnabs(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - 1ULL << 63); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_ori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /* fneg */ /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ static void gen_fneg(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - 1ULL << 63); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_xori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 /* fcpsgn: PowerPC 2.05 specification */ /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ static void gen_fcpsgn(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], 0, 63); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 0, 63); + set_fpr(rD(ctx->opcode), t2); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } =20 static void gen_fmrgew(DisasContext *ctx) { TCGv_i64 b0; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } b0 =3D tcg_temp_new_i64(); - tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - b0, 0, 32); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_shri_i64(b0, t0, 32); + get_fpr(t0, rA(ctx->opcode)); + tcg_gen_deposit_i64(t1, t0, b0, 0, 32); + set_fpr(rD(ctx->opcode), t1); tcg_temp_free_i64(b0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 static void gen_fmrgow(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], - cpu_fpr[rA(ctx->opcode)], - 32, 32); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + get_fpr(t1, rA(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 32, 32); + set_fpr(rD(ctx->opcode), t2); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } =20 /*** Floating-Point status & ctrl register = ***/ @@ -458,15 +604,19 @@ static void gen_mcrfs(DisasContext *ctx) /* mffs */ static void gen_mffs(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + set_fpr(rD(ctx->opcode), t0); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); } =20 /* mtfsb0 */ @@ -522,6 +672,7 @@ static void gen_mtfsb1(DisasContext *ctx) static void gen_mtfsf(DisasContext *ctx) { TCGv_i32 t0; + TCGv_i64 t1; int flm, l, w; =20 if (unlikely(!ctx->fpu_enabled)) { @@ -541,7 +692,9 @@ static void gen_mtfsf(DisasContext *ctx) } else { t0 =3D tcg_const_i32(flm << (w * 8)); } - gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); + t1 =3D tcg_temp_new_i64(); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_store_fpscr(cpu_env, t1, t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -549,6 +702,7 @@ static void gen_mtfsf(DisasContext *ctx) } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t1); } =20 /* mtfsfi */ @@ -588,21 +742,26 @@ static void gen_mtfsfi(DisasContext *ctx) static void glue(gen_, name)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); = \ + gen_qemu_##ldop(ctx, t0, EA); = \ + set_fpr(rD(ctx->opcode), t0); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_LDUF(name, ldop, opc, type) = \ static void glue(gen_, name##u)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ @@ -613,20 +772,25 @@ static void glue(gen_, name##u)(DisasContext *ctx) } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); = \ + gen_qemu_##ldop(ctx, t0, EA); = \ + set_fpr(rD(ctx->opcode), t0); = \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_LDUXF(name, ldop, opc, type) = \ static void glue(gen_, name##ux)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ + t0 =3D tcg_temp_new_i64(); = \ if (unlikely(rA(ctx->opcode) =3D=3D 0)) { = \ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); = \ return; = \ @@ -634,24 +798,30 @@ static void glue(gen_, name##ux)(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); = \ + gen_qemu_##ldop(ctx, t0, EA); = \ + set_fpr(rD(ctx->opcode), t0); = \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_LDXF(name, ldop, opc2, opc3, type) = \ static void glue(gen_, name##x)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); = \ + gen_qemu_##ldop(ctx, t0, EA); = \ + set_fpr(rD(ctx->opcode), t0); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_LDFS(name, ldop, op, type) = \ @@ -677,6 +847,7 @@ GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); static void gen_lfdepx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; CHK_SV; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -684,16 +855,19 @@ static void gen_lfdepx(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, - DEF_MEMOP(MO_Q)); + tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q)); + set_fpr(rD(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* lfdp */ static void gen_lfdp(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -701,24 +875,31 @@ static void gen_lfdp(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0); + t0 =3D tcg_temp_new_i64(); /* We only need to swap high and low halves. gen_qemu_ld64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); } else { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* lfdpx */ static void gen_lfdpx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -726,18 +907,24 @@ static void gen_lfdpx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); + t0 =3D tcg_temp_new_i64(); /* We only need to swap high and low halves. gen_qemu_ld64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); } else { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* lfiwax */ @@ -745,6 +932,7 @@ static void gen_lfiwax(DisasContext *ctx) { TCGv EA; TCGv t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -752,47 +940,59 @@ static void gen_lfiwax(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); gen_qemu_ld32s(ctx, t0, EA); - tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); + tcg_gen_ext_tl_i64(t1, t0); + set_fpr(rD(ctx->opcode), t1); tcg_temp_free(EA); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } =20 /* lfiwzx */ static void gen_lfiwzx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld32u_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /*** Floating-point store = ***/ #define GEN_STF(name, stop, opc, type) = \ static void glue(gen_, name)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); = \ + get_fpr(t0, rS(ctx->opcode)); = \ + gen_qemu_##stop(ctx, t0, EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_STUF(name, stop, opc, type) = \ static void glue(gen_, name##u)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ @@ -803,16 +1003,20 @@ static void glue(gen_, name##u)(DisasContext *ctx) } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_imm_index(ctx, EA, 0); = \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); = \ + get_fpr(t0, rS(ctx->opcode)); = \ + gen_qemu_##stop(ctx, t0, EA); = \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_STUXF(name, stop, opc, type) = \ static void glue(gen_, name##ux)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ @@ -823,25 +1027,32 @@ static void glue(gen_, name##ux)(DisasContext *ctx) } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); = \ + get_fpr(t0, rS(ctx->opcode)); = \ + gen_qemu_##stop(ctx, t0, EA); = \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_STXF(name, stop, opc2, opc3, type) = \ static void glue(gen_, name##x)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 t0; = \ if (unlikely(!ctx->fpu_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_FPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_FLOAT); = \ EA =3D tcg_temp_new(); = \ + t0 =3D tcg_temp_new_i64(); = \ gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); = \ + get_fpr(t0, rS(ctx->opcode)); = \ + gen_qemu_##stop(ctx, t0, EA); = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(t0); = \ } =20 #define GEN_STFS(name, stop, op, type) = \ @@ -867,6 +1078,7 @@ GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); static void gen_stfdepx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; CHK_SV; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -874,60 +1086,76 @@ static void gen_stfdepx(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_st_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, - DEF_MEMOP(MO_Q)); + get_fpr(t0, rD(ctx->opcode)); + tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q)); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* stfdp */ static void gen_stfdp(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_addr_imm_index(ctx, EA, 0); /* We only need to swap high and low halves. gen_qemu_st64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); } else { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* stfdpx */ static void gen_stfdpx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); /* We only need to swap high and low halves. gen_qemu_st64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); } else { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 /* Optional: */ @@ -949,13 +1177,18 @@ static void gen_lfq(DisasContext *ctx) { int rd =3D rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } =20 /* lfqu */ @@ -964,17 +1197,22 @@ static void gen_lfqu(DisasContext *ctx) int ra =3D rA(ctx->opcode); int rd =3D rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); if (ra !=3D 0) tcg_gen_mov_tl(cpu_gpr[ra], t0); tcg_temp_free(t0); tcg_temp_free(t1); + tcg_temp_free_i64(t2); } =20 /* lfqux */ @@ -984,16 +1222,21 @@ static void gen_lfqux(DisasContext *ctx) int rd =3D rD(ctx->opcode); gen_set_access_type(ctx, ACCESS_FLOAT); TCGv t0, t1; + TCGv_i64 t2; + t2 =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); t1 =3D tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); tcg_temp_free(t1); if (ra !=3D 0) tcg_gen_mov_tl(cpu_gpr[ra], t0); tcg_temp_free(t0); + tcg_temp_free_i64(t2); } =20 /* lfqx */ @@ -1001,13 +1244,18 @@ static void gen_lfqx(DisasContext *ctx) { int rd =3D rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i64(); gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } =20 /* stfq */ @@ -1015,13 +1263,18 @@ static void gen_stfq(DisasContext *ctx) { int rd =3D rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } =20 /* stfqu */ @@ -1030,17 +1283,23 @@ static void gen_stfqu(DisasContext *ctx) int ra =3D rA(ctx->opcode); int rd =3D rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); + t2 =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); t1 =3D tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); tcg_temp_free(t1); - if (ra !=3D 0) + if (ra !=3D 0) { tcg_gen_mov_tl(cpu_gpr[ra], t0); + } tcg_temp_free(t0); + tcg_temp_free_i64(t2); } =20 /* stfqux */ @@ -1049,17 +1308,23 @@ static void gen_stfqux(DisasContext *ctx) int ra =3D rA(ctx->opcode); int rd =3D rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); + t2 =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); t1 =3D tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); tcg_temp_free(t1); - if (ra !=3D 0) + if (ra !=3D 0) { tcg_gen_mov_tl(cpu_gpr[ra], t0); + } tcg_temp_free(t0); + tcg_temp_free_i64(t2); } =20 /* stfqx */ @@ -1067,13 +1332,18 @@ static void gen_stfqx(DisasContext *ctx) { int rd =3D rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); + t1 =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } =20 #undef _GEN_FLOAT_ACB --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115793329246.83639291116526; Mon, 17 Dec 2018 22:49:53 -0800 (PST) Received: from localhost ([::1]:52069 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9CR-000194-VO for importer@patchew.org; Tue, 18 Dec 2018 01:49:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92s-0001eE-QC for qemu-devel@nongnu.org; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ySoOgGs97HnY91dx35E4Ze097XeFpL9Kzw7U4c5TgcU=; b=V+8/P8axABBYJrRvHQcf/rNR01QTKVSmPMjWzxicpizdaQxN3Q3cxxexZWBYPQGLe/ C/IvF6aFuZroAABBJ1aJ38v9YZWTb2otCTLNTI5FurMa6Z4Nix7Xg+LMIHvo/XAbVqdx X8gvl7m9trsjqZ1QwnvStei5pobpEoik9aVt0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ySoOgGs97HnY91dx35E4Ze097XeFpL9Kzw7U4c5TgcU=; b=N26YG22glH/JGx2Gzm8RekGO750vq0LoAaZVPDjXOd/PybhMUQBqycz+k6pmLS1Yib 5OpUBTqfy091Y1xOyiX6ezX+STWlwDS8WATrcdFSw4COyEGpPlTk85F/9sBtmHEVWf/c 0WvpWPoN/urYpvT5RTyKEPS8fEAkWaCo/tfEvEyPrxjLwe21bIyNarwy3hm2ECrEG4T+ 27b4BjSzCaA4huG72t01gsepn0lCAzDqsqXMM2ny4Ru1LHK415iiuNX/54k2nIiSlrGX Iqxkjkq4DSunVU13l4csU4aQCqD016LKF7pm14q4Wg6V5LlW2Rzk38EYKE+oMm5ntV3w loIw== X-Gm-Message-State: AA+aEWbAyCd5H47oC82JI4lVxPmRviXSQcdv/yLZEeWMrnwniYHzf9DB 65U53wJfnApspI/7bbCCI12IWXKfZTQ= X-Google-Smtp-Source: AFSGD/XwfrTMu4vgpwoIZbpCDXhFLPvgGtAVo1Sb9LYlTWS8hNnbSAWlyN1fe1N5pnS1eRDYieipSQ== X-Received: by 2002:a62:7f93:: with SMTP id a141mr222762pfd.96.1545115168878; Mon, 17 Dec 2018 22:39:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:49 -0800 Message-Id: <20181218063911.2112-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 12/34] target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland These helpers allow us to move AVR register values to/from the specified TC= Gv_i64 argument. To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extr= a TCG temporaries as required. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20181217122405.18732-3-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/translate.c | 10 +++ target/ppc/translate/vmx-impl.inc.c | 128 ++++++++++++++++++++++------ 2 files changed, 110 insertions(+), 28 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1d4bf624a3..fa3e8dc114 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6704,6 +6704,16 @@ static inline void set_fpr(int regno, TCGv_i64 src) tcg_gen_mov_i64(cpu_fpr[regno], src); } =20 +static inline void get_avr64(TCGv_i64 dst, int regno, bool high) +{ + tcg_gen_mov_i64(dst, (high ? cpu_avrh : cpu_avrl)[regno]); +} + +static inline void set_avr64(int regno, TCGv_i64 src, bool high) +{ + tcg_gen_mov_i64((high ? cpu_avrh : cpu_avrl)[regno], src); +} + #include "translate/fp-impl.inc.c" =20 #include "translate/vmx-impl.inc.c" diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 3cb6fc2926..30046c6e31 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -18,52 +18,66 @@ static inline TCGv_ptr gen_avr_ptr(int reg) static void glue(gen_, name)(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 avr; = \ if (unlikely(!ctx->altivec_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_VPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_INT); = \ + avr =3D tcg_temp_new_i64(); = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ tcg_gen_andi_tl(EA, EA, ~0xf); = \ /* We only need to swap high and low halves. gen_qemu_ld64_i64 does = \ necessary 64-bit byteswap already. */ = \ if (ctx->le_mode) { = \ - gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); = \ + gen_qemu_ld64_i64(ctx, avr, EA); = \ + set_avr64(rD(ctx->opcode), avr, false); = \ tcg_gen_addi_tl(EA, EA, 8); = \ - gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); = \ + gen_qemu_ld64_i64(ctx, avr, EA); = \ + set_avr64(rD(ctx->opcode), avr, true); = \ } else { = \ - gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); = \ + gen_qemu_ld64_i64(ctx, avr, EA); = \ + set_avr64(rD(ctx->opcode), avr, true); = \ tcg_gen_addi_tl(EA, EA, 8); = \ - gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); = \ + gen_qemu_ld64_i64(ctx, avr, EA); = \ + set_avr64(rD(ctx->opcode), avr, false); = \ } = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(avr); = \ } =20 #define GEN_VR_STX(name, opc2, opc3) = \ static void gen_st##name(DisasContext *ctx) = \ { = \ TCGv EA; = \ + TCGv_i64 avr; = \ if (unlikely(!ctx->altivec_enabled)) { = \ gen_exception(ctx, POWERPC_EXCP_VPU); = \ return; = \ } = \ gen_set_access_type(ctx, ACCESS_INT); = \ + avr =3D tcg_temp_new_i64(); = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ tcg_gen_andi_tl(EA, EA, ~0xf); = \ /* We only need to swap high and low halves. gen_qemu_st64_i64 does = \ necessary 64-bit byteswap already. */ = \ if (ctx->le_mode) { = \ - gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); = \ + get_avr64(avr, rD(ctx->opcode), false); = \ + gen_qemu_st64_i64(ctx, avr, EA); = \ tcg_gen_addi_tl(EA, EA, 8); = \ - gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); = \ + get_avr64(avr, rD(ctx->opcode), true); = \ + gen_qemu_st64_i64(ctx, avr, EA); = \ } else { = \ - gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); = \ + get_avr64(avr, rD(ctx->opcode), true); = \ + gen_qemu_st64_i64(ctx, avr, EA); = \ tcg_gen_addi_tl(EA, EA, 8); = \ - gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); = \ + get_avr64(avr, rD(ctx->opcode), false); = \ + gen_qemu_st64_i64(ctx, avr, EA); = \ } = \ tcg_temp_free(EA); = \ + tcg_temp_free_i64(avr); = \ } =20 #define GEN_VR_LVE(name, opc2, opc3, size) \ @@ -159,15 +173,20 @@ static void gen_lvsr(DisasContext *ctx) static void gen_mfvscr(DisasContext *ctx) { TCGv_i32 t; + TCGv_i64 avr; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); return; } - tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); + avr =3D tcg_temp_new_i64(); + tcg_gen_movi_i64(avr, 0); + set_avr64(rD(ctx->opcode), avr, true); t =3D tcg_temp_new_i32(); tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); - tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); + tcg_gen_extu_i32_i64(avr, t); + set_avr64(rD(ctx->opcode), avr, false); tcg_temp_free_i32(t); + tcg_temp_free_i64(avr); } =20 static void gen_mtvscr(DisasContext *ctx) @@ -188,6 +207,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ TCGv_i64 t0 =3D tcg_temp_new_i64(); \ TCGv_i64 t1 =3D tcg_temp_new_i64(); \ TCGv_i64 t2 =3D tcg_temp_new_i64(); \ + TCGv_i64 avr =3D tcg_temp_new_i64(); \ TCGv_i64 ten, z; \ \ if (unlikely(!ctx->altivec_enabled)) { \ @@ -199,26 +219,35 @@ static void glue(gen_, name)(DisasContext *ctx) = \ z =3D tcg_const_i64(0); \ \ if (add_cin) { \ - tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); \ - tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); \ - tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + get_avr64(avr, rB(ctx->opcode), false); \ + tcg_gen_andi_i64(t2, avr, 0xF); \ + tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ } else { \ - tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, \ - cpu_avrl[rA(ctx->opcode)], ten); \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(avr, t2, avr, ten); \ + set_avr64(rD(ctx->opcode), avr, false); \ } \ \ if (ret_carry) { \ - tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); \ - tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); \ - tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ + set_avr64(rD(ctx->opcode), z, true); \ } else { \ - tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); \ - tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mul_i64(t0, avr, ten); \ + tcg_gen_add_i64(avr, t0, t2); \ + set_avr64(rD(ctx->opcode), avr, true); \ } \ \ tcg_temp_free_i64(t0); \ tcg_temp_free_i64(t1); \ tcg_temp_free_i64(t2); \ + tcg_temp_free_i64(avr); \ tcg_temp_free_i64(ten); \ tcg_temp_free_i64(z); \ } \ @@ -232,12 +261,27 @@ GEN_VX_VMUL10(vmul10ecuq, 1, 1); #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) = \ { \ + TCGv_i64 t0 =3D tcg_temp_new_i64(); \ + TCGv_i64 t1 =3D tcg_temp_new_i64(); \ + TCGv_i64 avr =3D tcg_temp_new_i64(); \ + \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[= rB(ctx->opcode)]); \ - tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[= rB(ctx->opcode)]); \ + get_avr64(t0, rA(ctx->opcode), true); \ + get_avr64(t1, rB(ctx->opcode), true); \ + tcg_op(avr, t0, t1); \ + set_avr64(rD(ctx->opcode), avr, true); \ + \ + get_avr64(t0, rA(ctx->opcode), false); \ + get_avr64(t1, rB(ctx->opcode), false); \ + tcg_op(avr, t0, t1); \ + set_avr64(rD(ctx->opcode), avr, false); \ + \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(avr); \ } =20 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); @@ -406,6 +450,7 @@ GEN_VXFORM(vmrglw, 6, 6); static void gen_vmrgew(DisasContext *ctx) { TCGv_i64 tmp; + TCGv_i64 avr; int VT, VA, VB; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -415,15 +460,28 @@ static void gen_vmrgew(DisasContext *ctx) VA =3D rA(ctx->opcode); VB =3D rB(ctx->opcode); tmp =3D tcg_temp_new_i64(); - tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); - tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); - tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); - tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); + avr =3D tcg_temp_new_i64(); + + get_avr64(avr, VB, true); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, true); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, true); + + get_avr64(avr, VB, false); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, false); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, false); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(avr); } =20 static void gen_vmrgow(DisasContext *ctx) { + TCGv_i64 t0, t1; + TCGv_i64 avr; int VT, VA, VB; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -432,9 +490,23 @@ static void gen_vmrgow(DisasContext *ctx) VT =3D rD(ctx->opcode); VA =3D rA(ctx->opcode); VB =3D rB(ctx->opcode); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + avr =3D tcg_temp_new_i64(); =20 - tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); - tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); + get_avr64(t0, VB, true); + get_avr64(t1, VA, true); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, true); + + get_avr64(t0, VB, false); + get_avr64(t1, VA, false); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(avr); } =20 GEN_VXFORM(vmuloub, 4, 0); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8M1EhYm0cBzNrIHw+ulCbUtWA282WkxgR0CJDrYWKAk=; b=eEX8sBEPtiKjs2yuum7b4OUaPMiT0/jXE6cTFIHKFTVNH7Jy+ICll2TUnFC2al6QhR N2QEZcZmXEUwKXV2GSp1I7q+qIhfipgcpmrCJb7wMSxnofPeBmBaRFAxp6Iw1WKt1JMs 6M4LMmMLBL5qQyF58gReZ0cIgIONLiAlLmkWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8M1EhYm0cBzNrIHw+ulCbUtWA282WkxgR0CJDrYWKAk=; b=on9mMAiWJOjaCnAKBSd3eagLd+WG2FUOCWdTCmsza8LGNzZvmJ54JEAds4UodVw93Z zbNcl3cO84pQrWfhT7S9voKVxRNRdRUwTo8Zpr75NB5HOIV3y43spDEzS/LeB0X6jO3/ ElpFQ5rfNTIFeIygA6eSjbnOJ5jEOyq2T9DVhgk8DhWxKNJUlQFt52UW+LqciyZ618Qk nAG6y+OaLMXkWOtUYvvnO0IoEPGD5AqenuKICDARFncGCnyMs+FUbVtp+EvCNexQoM6S 9n/yobfnHYjCqW35auOaSKAY8yPjtHdqLtjueUOLmLPvf+MgKo4u0IxoeDJNQCK8pCMG RgOg== X-Gm-Message-State: AA+aEWYDzgufr6Sk5zkDQwYIcXuLOG2Dhq6qBbH2m8E2UOrsQEBpSKi3 u7XySeoVUkV7qe+5dXDHDORMhnWPBz4= X-Google-Smtp-Source: AFSGD/UEkkgU0HrG0grfpTnRIoawmopT6uSKrrZh5KvwR1605YPaARgAIDjLqfw0EoG46YUzumZmvA== X-Received: by 2002:a62:9657:: with SMTP id c84mr15987872pfe.77.1545115170224; Mon, 17 Dec 2018 22:39:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:50 -0800 Message-Id: <20181218063911.2112-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 13/34] target/ppc: introduce get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() helpers for VSR register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland These helpers allow us to move VSR register values to/from the specified TC= Gv_i64 argument. To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland Message-Id: <20181217122405.18732-4-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 782 ++++++++++++++++++++-------- 1 file changed, 561 insertions(+), 221 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 85ed135d44..e9a05d66f7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,20 +1,48 @@ /*** VSX extension = ***/ =20 -static inline TCGv_i64 cpu_vsrh(int n) +static inline void get_vsr(TCGv_i64 dst, int n) +{ + tcg_gen_mov_i64(dst, cpu_vsr[n]); +} + +static inline void set_vsr(int n, TCGv_i64 src) +{ + tcg_gen_mov_i64(cpu_vsr[n], src); +} + +static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { if (n < 32) { - return cpu_fpr[n]; + get_fpr(dst, n); } else { - return cpu_avrh[n-32]; + get_avr64(dst, n - 32, true); } } =20 -static inline TCGv_i64 cpu_vsrl(int n) +static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { if (n < 32) { - return cpu_vsr[n]; + get_vsr(dst, n); } else { - return cpu_avrl[n-32]; + get_avr64(dst, n - 32, false); + } +} + +static inline void set_cpu_vsrh(int n, TCGv_i64 src) +{ + if (n < 32) { + set_fpr(n, src); + } else { + set_avr64(n - 32, src, true); + } +} + +static inline void set_cpu_vsrl(int n, TCGv_i64 src) +{ + if (n < 32) { + set_vsr(n, src); + } else { + set_avr64(n - 32, src, false); } } =20 @@ -22,16 +50,20 @@ static inline TCGv_i64 cpu_vsrl(int n) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ + t0 =3D tcg_temp_new_i64(); \ gen_set_access_type(ctx, ACCESS_INT); \ EA =3D tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ + gen_qemu_##operation(ctx, t0, EA); \ + set_cpu_vsrh(xT(ctx->opcode), t0); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } =20 VSX_LOAD_SCALAR(lxsdx, ld64_i64) @@ -44,39 +76,54 @@ VSX_LOAD_SCALAR(lxsspx, ld32fs) static void gen_lxvd2x(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + t0 =3D tcg_temp_new_i64(); gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrl(xT(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 static void gen_lxvdsx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_gen_mov_i64(t1, t0); + set_cpu_vsrl(xT(ctx->opcode), t1); tcg_temp_free(EA); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } =20 static void gen_lxvw4x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrh(xtl, xT(ctx->opcode)); if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; @@ -104,6 +151,8 @@ static void gen_lxvw4x(DisasContext *ctx) tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } =20 static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, @@ -151,8 +200,10 @@ static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, static void gen_lxvh8x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrh(xtl, xT(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -169,13 +220,17 @@ static void gen_lxvh8x(DisasContext *ctx) gen_bswap16x8(xth, xtl, xth, xtl); } tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } =20 static void gen_lxvb16x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrh(xtl, xT(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -188,6 +243,8 @@ static void gen_lxvb16x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } =20 #define VSX_VECTOR_LOAD_STORE(name, op, indexed) \ @@ -195,15 +252,16 @@ static void gen_##name(DisasContext *ctx) = \ { \ int xt; \ TCGv EA; \ - TCGv_i64 xth, xtl; \ + TCGv_i64 xth =3D tcg_temp_new_i64(); \ + TCGv_i64 xtl =3D tcg_temp_new_i64(); \ \ if (indexed) { \ xt =3D xT(ctx->opcode); \ } else { \ xt =3D DQxT(ctx->opcode); \ } \ - xth =3D cpu_vsrh(xt); \ - xtl =3D cpu_vsrl(xt); \ + get_cpu_vsrh(xth, xt); \ + get_cpu_vsrl(xtl, xt); \ \ if (xt < 32) { \ if (unlikely(!ctx->vsx_enabled)) { \ @@ -225,14 +283,20 @@ static void gen_##name(DisasContext *ctx) = \ } \ if (ctx->le_mode) { \ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrl(xt, xtl); \ tcg_gen_addi_tl(EA, EA, 8); \ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrh(xt, xth); \ } else { \ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrh(xt, xth); \ tcg_gen_addi_tl(EA, EA, 8); \ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrl(xt, xtl); \ } \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ + tcg_temp_free_i64(xtl); \ } =20 VSX_VECTOR_LOAD_STORE(lxv, ld_i64, 0) @@ -276,7 +340,8 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvll) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ - TCGv_i64 xth =3D cpu_vsrh(rD(ctx->opcode) + 32); \ + TCGv_i64 xth =3D tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ @@ -286,8 +351,10 @@ static void gen_##name(DisasContext *ctx) = \ EA =3D tcg_temp_new(); \ gen_addr_imm_index(ctx, EA, 0x03); \ gen_qemu_##operation(ctx, xth, EA); \ + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ } =20 VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) @@ -297,15 +364,19 @@ VSX_LOAD_SCALAR_DS(lxssp, ld32fs) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ + t0 =3D tcg_temp_new_i64(); \ gen_set_access_type(ctx, ACCESS_INT); \ EA =3D tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ + gen_qemu_##operation(ctx, t0, EA); \ + set_cpu_vsrh(xS(ctx->opcode), t0); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } =20 VSX_STORE_SCALAR(stxsdx, st64_i64) @@ -318,6 +389,7 @@ VSX_STORE_SCALAR(stxsspx, st32fs) static void gen_stxvd2x(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0 =3D tcg_temp_new_i64(); if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; @@ -325,17 +397,23 @@ static void gen_stxvd2x(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_st64_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); + get_cpu_vsrh(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); + get_cpu_vsrl(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } =20 static void gen_stxvw4x(DisasContext *ctx) { - TCGv_i64 xsh =3D cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl =3D cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh =3D tcg_temp_new_i64(); + TCGv_i64 xsl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; @@ -362,13 +440,17 @@ static void gen_stxvw4x(DisasContext *ctx) tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } =20 static void gen_stxvh8x(DisasContext *ctx) { - TCGv_i64 xsh =3D cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl =3D cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh =3D tcg_temp_new_i64(); + TCGv_i64 xsl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -393,13 +475,17 @@ static void gen_stxvh8x(DisasContext *ctx) tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } =20 static void gen_stxvb16x(DisasContext *ctx) { - TCGv_i64 xsh =3D cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl =3D cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh =3D tcg_temp_new_i64(); + TCGv_i64 xsl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -412,13 +498,16 @@ static void gen_stxvb16x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } =20 #define VSX_STORE_SCALAR_DS(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ - TCGv_i64 xth =3D cpu_vsrh(rD(ctx->opcode) + 32); \ + TCGv_i64 xth =3D tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ @@ -430,62 +519,119 @@ static void gen_##name(DisasContext *ctx) = \ gen_qemu_##operation(ctx, xth, EA); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ } =20 VSX_LOAD_SCALAR_DS(stxsd, st64_i64) VSX_LOAD_SCALAR_DS(stxssp, st32fs) =20 -#define MV_VSRW(name, tcgop1, tcgop2, target, source) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - if (xS(ctx->opcode) < 32) { \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - TCGv_i64 tmp =3D tcg_temp_new_i64(); \ - tcg_gen_##tcgop1(tmp, source); \ - tcg_gen_##tcgop2(target, tmp); \ - tcg_temp_free_i64(tmp); \ +static void gen_mfvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 xsh =3D tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + tcg_gen_ext32u_i64(tmp, xsh); + tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp); + tcg_temp_free_i64(tmp); } =20 +static void gen_mtvsrwa(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 xsh =3D tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} =20 -MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ - cpu_vsrh(xS(ctx->opcode))) -MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ - cpu_gpr[rA(ctx->opcode)]) -MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ - cpu_gpr[rA(ctx->opcode)]) +static void gen_mtvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 xsh =3D tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32u_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} =20 #if defined(TARGET_PPC64) -#define MV_VSRD(name, target, source) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - if (xS(ctx->opcode) < 32) { \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - tcg_gen_mov_i64(target, source); \ +static void gen_mfvsrd(DisasContext *ctx) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + get_cpu_vsrh(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } =20 -MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) -MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) +static void gen_mtvsrd(DisasContext *ctx) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} =20 static void gen_mfvsrld(DisasContext *ctx) { + TCGv_i64 t0 =3D tcg_temp_new_i64(); if (xS(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -497,12 +643,14 @@ static void gen_mfvsrld(DisasContext *ctx) return; } } - - tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode))); + get_cpu_vsrl(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } =20 static void gen_mtvsrdd(DisasContext *ctx) { + TCGv_i64 t0 =3D tcg_temp_new_i64(); if (xT(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -516,16 +664,20 @@ static void gen_mtvsrdd(DisasContext *ctx) } =20 if (!rA(ctx->opcode)) { - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); + tcg_gen_movi_i64(t0, 0); } else { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)= ]); + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); } + set_cpu_vsrh(xT(ctx->opcode), t0); =20 - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]); + tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); + set_cpu_vsrl(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); } =20 static void gen_mtvsrws(DisasContext *ctx) { + TCGv_i64 t0 =3D tcg_temp_new_i64(); if (xT(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -538,55 +690,60 @@ static void gen_mtvsrws(DisasContext *ctx) } } =20 - tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)= ], + tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32, 32); - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode))); + set_cpu_vsrl(xT(ctx->opcode), t0); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); } =20 #endif =20 static void gen_xxpermdi(DisasContext *ctx) { + TCGv_i64 xh, xl; + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } =20 + xh =3D tcg_temp_new_i64(); + xl =3D tcg_temp_new_i64(); + if (unlikely((xT(ctx->opcode) =3D=3D xA(ctx->opcode)) || (xT(ctx->opcode) =3D=3D xB(ctx->opcode)))) { - TCGv_i64 xh, xl; - - xh =3D tcg_temp_new_i64(); - xl =3D tcg_temp_new_i64(); - if ((DM(ctx->opcode) & 2) =3D=3D 0) { - tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode))); + get_cpu_vsrh(xh, xA(ctx->opcode)); } else { - tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xh, xA(ctx->opcode)); } if ((DM(ctx->opcode) & 1) =3D=3D 0) { - tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(xl, xB(ctx->opcode)); } else { - tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode))); + get_cpu_vsrl(xl, xB(ctx->opcode)); } =20 - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl); - - tcg_temp_free_i64(xh); - tcg_temp_free_i64(xl); + set_cpu_vsrh(xT(ctx->opcode), xh); + set_cpu_vsrl(xT(ctx->opcode), xl); } else { if ((DM(ctx->opcode) & 2) =3D=3D 0) { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->op= code))); + get_cpu_vsrh(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); } else { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->op= code))); + get_cpu_vsrl(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); } if ((DM(ctx->opcode) & 1) =3D=3D 0) { - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->op= code))); + get_cpu_vsrh(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); } else { - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->op= code))); + get_cpu_vsrl(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); } } + tcg_temp_free_i64(xh); + tcg_temp_free_i64(xl); } =20 #define OP_ABS 1 @@ -606,7 +763,7 @@ static void glue(gen_, name)(DisasContext * ctx) = \ } \ xb =3D tcg_temp_new_i64(); \ sgm =3D tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ + get_cpu_vsrh(xb, xB(ctx->opcode)); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \ @@ -623,7 +780,7 @@ static void glue(gen_, name)(DisasContext * ctx) = \ } \ case OP_CPSGN: { \ TCGv_i64 xa =3D tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ + get_cpu_vsrh(xa, xA(ctx->opcode)); \ tcg_gen_and_i64(xa, xa, sgm); \ tcg_gen_andc_i64(xb, xb, sgm); \ tcg_gen_or_i64(xb, xb, xa); \ @@ -631,7 +788,7 @@ static void glue(gen_, name)(DisasContext * ctx) = \ break; \ } \ } \ - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ + set_cpu_vsrh(xT(ctx->opcode), xb); \ tcg_temp_free_i64(xb); \ tcg_temp_free_i64(sgm); \ } @@ -647,7 +804,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ int xa; \ int xt =3D rD(ctx->opcode) + 32; \ int xb =3D rB(ctx->opcode) + 32; \ - TCGv_i64 xah, xbh, xbl, sgm; \ + TCGv_i64 xah, xbh, xbl, sgm, tmp; \ \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ @@ -656,8 +813,9 @@ static void glue(gen_, name)(DisasContext *ctx) = \ xbh =3D tcg_temp_new_i64(); \ xbl =3D tcg_temp_new_i64(); \ sgm =3D tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xbh, cpu_vsrh(xb)); \ - tcg_gen_mov_i64(xbl, cpu_vsrl(xb)); \ + tmp =3D tcg_temp_new_i64(); \ + get_cpu_vsrh(xbh, xb); \ + get_cpu_vsrl(xbl, xb); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: \ @@ -672,17 +830,19 @@ static void glue(gen_, name)(DisasContext *ctx) = \ case OP_CPSGN: \ xah =3D tcg_temp_new_i64(); \ xa =3D rA(ctx->opcode) + 32; \ - tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \ + get_cpu_vsrh(tmp, xa); \ + tcg_gen_and_i64(xah, tmp, sgm); \ tcg_gen_andc_i64(xbh, xbh, sgm); \ tcg_gen_or_i64(xbh, xbh, xah); \ tcg_temp_free_i64(xah); \ break; \ } \ - tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \ - tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \ + set_cpu_vsrh(xt, xbh); \ + set_cpu_vsrl(xt, xbl); \ tcg_temp_free_i64(xbl); \ tcg_temp_free_i64(xbh); \ tcg_temp_free_i64(sgm); \ + tcg_temp_free_i64(tmp); \ } =20 VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP) @@ -701,8 +861,8 @@ static void glue(gen_, name)(DisasContext * ctx) = \ xbh =3D tcg_temp_new_i64(); \ xbl =3D tcg_temp_new_i64(); \ sgm =3D tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ - tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ + set_cpu_vsrh(xB(ctx->opcode), xbh); \ + set_cpu_vsrl(xB(ctx->opcode), xbl); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \ @@ -723,8 +883,8 @@ static void glue(gen_, name)(DisasContext * ctx) = \ case OP_CPSGN: { \ TCGv_i64 xah =3D tcg_temp_new_i64(); \ TCGv_i64 xal =3D tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ + get_cpu_vsrh(xah, xA(ctx->opcode)); \ + get_cpu_vsrl(xal, xA(ctx->opcode)); \ tcg_gen_and_i64(xah, xah, sgm); \ tcg_gen_and_i64(xal, xal, sgm); \ tcg_gen_andc_i64(xbh, xbh, sgm); \ @@ -736,8 +896,8 @@ static void glue(gen_, name)(DisasContext * ctx) = \ break; \ } \ } \ - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ + set_cpu_vsrh(xT(ctx->opcode), xbh); \ + set_cpu_vsrl(xT(ctx->opcode), xbl); \ tcg_temp_free_i64(xbh); \ tcg_temp_free_i64(xbl); \ tcg_temp_free_i64(sgm); \ @@ -768,12 +928,17 @@ static void gen_##name(DisasContext * ctx) = \ #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext * ctx) \ { \ + TCGv_i64 t0 =3D tcg_temp_new_i64(); \ + TCGv_i64 t1 =3D tcg_temp_new_i64(); \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ - cpu_vsrh(xB(ctx->opcode))); \ + get_cpu_vsrh(t0, xB(ctx->opcode)); \ + gen_helper_##name(t1, cpu_env, t0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ } =20 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) @@ -949,10 +1114,13 @@ GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) =20 static void gen_xxbrd(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -960,28 +1128,49 @@ static void gen_xxbrd(DisasContext *ctx) } tcg_gen_bswap64_i64(xth, xbh); tcg_gen_bswap64_i64(xtl, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xxbrh(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } gen_bswap16x8(xth, xtl, xbh, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xxbrq(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + TCGv_i64 t0 =3D tcg_temp_new_i64(); =20 if (unlikely(!ctx->vsx_enabled)) { @@ -990,35 +1179,65 @@ static void gen_xxbrq(DisasContext *ctx) } tcg_gen_bswap64_i64(t0, xbl); tcg_gen_bswap64_i64(xtl, xbh); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_gen_mov_i64(xth, t0); + set_cpu_vsrl(xT(ctx->opcode), xth); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xxbrw(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } gen_bswap32x4(xth, xtl, xbh, xbl); + set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 #define VSX_LOGICAL(name, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ - cpu_vsrh(xB(ctx->opcode))); \ - tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ - cpu_vsrl(xB(ctx->opcode))); \ + t0 =3D tcg_temp_new_i64(); \ + t1 =3D tcg_temp_new_i64(); \ + t2 =3D tcg_temp_new_i64(); \ + get_cpu_vsrh(t0, xA(ctx->opcode)); \ + get_cpu_vsrh(t1, xB(ctx->opcode)); \ + tcg_op(t2, t0, t1); \ + set_cpu_vsrh(xT(ctx->opcode), t2); \ + get_cpu_vsrl(t0, xA(ctx->opcode)); \ + get_cpu_vsrl(t1, xB(ctx->opcode)); \ + tcg_op(t2, t0, t1); \ + set_cpu_vsrl(xT(ctx->opcode), t2); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ } =20 VSX_LOGICAL(xxland, tcg_gen_and_i64) @@ -1033,7 +1252,7 @@ VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) #define VSX_XXMRG(name, high) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ - TCGv_i64 a0, a1, b0, b1; \ + TCGv_i64 a0, a1, b0, b1, tmp; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ @@ -1042,27 +1261,29 @@ static void glue(gen_, name)(DisasContext * ctx) = \ a1 =3D tcg_temp_new_i64(); \ b0 =3D tcg_temp_new_i64(); \ b1 =3D tcg_temp_new_i64(); \ + tmp =3D tcg_temp_new_i64(); \ if (high) { \ - tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ - tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ + get_cpu_vsrh(a0, xA(ctx->opcode)); \ + get_cpu_vsrh(a1, xA(ctx->opcode)); \ + get_cpu_vsrh(b0, xB(ctx->opcode)); \ + get_cpu_vsrh(b1, xB(ctx->opcode)); \ } else { \ - tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ - tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ - tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ - tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ + get_cpu_vsrl(a0, xA(ctx->opcode)); \ + get_cpu_vsrl(a1, xA(ctx->opcode)); \ + get_cpu_vsrl(b0, xB(ctx->opcode)); \ + get_cpu_vsrl(b1, xB(ctx->opcode)); \ } \ tcg_gen_shri_i64(a0, a0, 32); \ tcg_gen_shri_i64(b0, b0, 32); \ - tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ - b0, a0, 32, 32); \ - tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ - b1, a1, 32, 32); \ + tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \ + set_cpu_vsrh(xT(ctx->opcode), tmp); \ + tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \ + set_cpu_vsrl(xT(ctx->opcode), tmp); \ tcg_temp_free_i64(a0); \ tcg_temp_free_i64(a1); \ tcg_temp_free_i64(b0); \ tcg_temp_free_i64(b1); \ + tcg_temp_free_i64(tmp); \ } =20 VSX_XXMRG(xxmrghw, 1) @@ -1070,7 +1291,7 @@ VSX_XXMRG(xxmrglw, 0) =20 static void gen_xxsel(DisasContext * ctx) { - TCGv_i64 a, b, c; + TCGv_i64 a, b, c, tmp; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; @@ -1078,34 +1299,43 @@ static void gen_xxsel(DisasContext * ctx) a =3D tcg_temp_new_i64(); b =3D tcg_temp_new_i64(); c =3D tcg_temp_new_i64(); + tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); - tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); - tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); + get_cpu_vsrh(a, xA(ctx->opcode)); + get_cpu_vsrh(b, xB(ctx->opcode)); + get_cpu_vsrh(c, xC(ctx->opcode)); =20 tcg_gen_and_i64(b, b, c); tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); + tcg_gen_or_i64(tmp, a, b); + set_cpu_vsrh(xT(ctx->opcode), tmp); =20 - tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); - tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); - tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); + get_cpu_vsrl(a, xA(ctx->opcode)); + get_cpu_vsrl(b, xB(ctx->opcode)); + get_cpu_vsrl(c, xC(ctx->opcode)); =20 tcg_gen_and_i64(b, b, c); tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); + tcg_gen_or_i64(tmp, a, b); + set_cpu_vsrl(xT(ctx->opcode), tmp); =20 tcg_temp_free_i64(a); tcg_temp_free_i64(b); tcg_temp_free_i64(c); + tcg_temp_free_i64(tmp); } =20 static void gen_xxspltw(DisasContext *ctx) { TCGv_i64 b, b2; - TCGv_i64 vsr =3D (UIM(ctx->opcode) & 2) ? - cpu_vsrl(xB(ctx->opcode)) : - cpu_vsrh(xB(ctx->opcode)); + TCGv_i64 vsr; + + vsr =3D tcg_temp_new_i64(); + if (UIM(ctx->opcode) & 2) { + get_cpu_vsrl(vsr, xB(ctx->opcode)); + } else { + get_cpu_vsrh(vsr, xB(ctx->opcode)); + } =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -1122,9 +1352,11 @@ static void gen_xxspltw(DisasContext *ctx) } =20 tcg_gen_shli_i64(b2, b, 32); - tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + tcg_gen_or_i64(vsr, b, b2); + set_cpu_vsrh(xT(ctx->opcode), vsr); + set_cpu_vsrl(xT(ctx->opcode), vsr); =20 + tcg_temp_free_i64(vsr); tcg_temp_free_i64(b); tcg_temp_free_i64(b2); } @@ -1134,6 +1366,7 @@ static void gen_xxspltw(DisasContext *ctx) static void gen_xxspltib(DisasContext *ctx) { unsigned char uim8 =3D IMM8(ctx->opcode); + TCGv_i64 vsr =3D tcg_temp_new_i64(); if (xS(ctx->opcode) < 32) { if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -1145,8 +1378,10 @@ static void gen_xxspltib(DisasContext *ctx) return; } } - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), pattern(uim8)); - tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), pattern(uim8)); + tcg_gen_movi_i64(vsr, pattern(uim8)); + set_cpu_vsrh(xT(ctx->opcode), vsr); + set_cpu_vsrl(xT(ctx->opcode), vsr); + tcg_temp_free_i64(vsr); } =20 static void gen_xxsldwi(DisasContext *ctx) @@ -1161,40 +1396,40 @@ static void gen_xxsldwi(DisasContext *ctx) =20 switch (SHW(ctx->opcode)) { case 0: { - tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); - tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrh(xth, xA(ctx->opcode)); + get_cpu_vsrl(xtl, xA(ctx->opcode)); break; } case 1: { TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); + get_cpu_vsrh(xth, xA(ctx->opcode)); tcg_gen_shli_i64(xth, xth, 32); - tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(t0, xA(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xtl, xA(ctx->opcode)); tcg_gen_shli_i64(xtl, xtl, 32); - tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); tcg_temp_free_i64(t0); break; } case 2: { - tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); - tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrl(xth, xA(ctx->opcode)); + get_cpu_vsrh(xtl, xB(ctx->opcode)); break; } case 3: { TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xth, xA(ctx->opcode)); tcg_gen_shli_i64(xth, xth, 32); - tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(xtl, xB(ctx->opcode)); tcg_gen_shli_i64(xtl, xtl, 32); - tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); + get_cpu_vsrl(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); tcg_temp_free_i64(t0); @@ -1202,8 +1437,8 @@ static void gen_xxsldwi(DisasContext *ctx) } } =20 - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); =20 tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -1214,6 +1449,7 @@ static void gen_##name(DisasContext *ctx) = \ { \ TCGv xt, xb; \ TCGv_i32 t0 =3D tcg_temp_new_i32(); \ + TCGv_i64 t1 =3D tcg_temp_new_i64(); \ uint8_t uimm =3D UIMM4(ctx->opcode); \ \ if (unlikely(!ctx->vsx_enabled)) { \ @@ -1226,8 +1462,9 @@ static void gen_##name(DisasContext *ctx) = \ * uimm > 12 handle as per hardware in helper \ */ \ if (uimm > 15) { \ - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \ - tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \ + tcg_gen_movi_i64(t1, 0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + set_cpu_vsrl(xT(ctx->opcode), t1); \ return; \ } \ tcg_gen_movi_i32(t0, uimm); \ @@ -1235,6 +1472,7 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free(xb); \ tcg_temp_free(xt); \ tcg_temp_free_i32(t0); \ + tcg_temp_free_i64(t1); \ } =20 VSX_EXTRACT_INSERT(xxextractuw) @@ -1244,30 +1482,41 @@ VSX_EXTRACT_INSERT(xxinsertw) static void gen_xsxexpdp(DisasContext *ctx) { TCGv rt =3D cpu_gpr[rD(ctx->opcode)]; + TCGv_i64 t0 =3D tcg_temp_new_i64(); if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11); + get_cpu_vsrh(t0, xB(ctx->opcode)); + tcg_gen_extract_i64(rt, t0, 52, 11); + tcg_temp_free_i64(t0); } =20 static void gen_xsxexpqp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl =3D cpu_vsrl(rD(ctx->opcode) + 32); - TCGv_i64 xbh =3D cpu_vsrh(rB(ctx->opcode) + 32); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } tcg_gen_extract_i64(xth, xbh, 48, 15); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); tcg_gen_movi_i64(xtl, 0); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } =20 static void gen_xsiexpdp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); + TCGv_i64 xth; TCGv ra =3D cpu_gpr[rA(ctx->opcode)]; TCGv rb =3D cpu_gpr[rB(ctx->opcode)]; TCGv_i64 t0; @@ -1277,21 +1526,30 @@ static void gen_xsiexpdp(DisasContext *ctx) return; } t0 =3D tcg_temp_new_i64(); + xth =3D tcg_temp_new_i64(); tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF); tcg_gen_andi_i64(t0, rb, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); /* dword[1] is undefined */ tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); } =20 static void gen_xsiexpqp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl =3D cpu_vsrl(rD(ctx->opcode) + 32); - TCGv_i64 xah =3D cpu_vsrh(rA(ctx->opcode) + 32); - TCGv_i64 xal =3D cpu_vsrl(rA(ctx->opcode) + 32); - TCGv_i64 xbh =3D cpu_vsrh(rB(ctx->opcode) + 32); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xah =3D tcg_temp_new_i64(); + TCGv_i64 xal =3D tcg_temp_new_i64(); + get_cpu_vsrh(xah, rA(ctx->opcode) + 32); + get_cpu_vsrl(xal, rA(ctx->opcode) + 32); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + TCGv_i64 t0; =20 if (unlikely(!ctx->vsx_enabled)) { @@ -1303,14 +1561,22 @@ static void gen_xsiexpqp(DisasContext *ctx) tcg_gen_andi_i64(t0, xbh, 0x7FFF); tcg_gen_shli_i64(t0, t0, 48); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); tcg_gen_mov_i64(xtl, xal); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); } =20 static void gen_xsxsigdp(DisasContext *ctx) { TCGv rt =3D cpu_gpr[rD(ctx->opcode)]; - TCGv_i64 t0, zr, nan, exp; + TCGv_i64 t0, t1, zr, nan, exp; =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -1318,17 +1584,21 @@ static void gen_xsxsigdp(DisasContext *ctx) } exp =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); zr =3D tcg_const_i64(0); nan =3D tcg_const_i64(2047); =20 - tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11); + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_extract_i64(exp, t1, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF); + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_andi_i64(rt, t1, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(rt, rt, t0); =20 tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); @@ -1337,8 +1607,13 @@ static void gen_xsxsigdp(DisasContext *ctx) static void gen_xsxsigqp(DisasContext *ctx) { TCGv_i64 t0, zr, nan, exp; - TCGv_i64 xth =3D cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl =3D cpu_vsrl(rD(ctx->opcode) + 32); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + get_cpu_vsrl(xbl, rB(ctx->opcode) + 32); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -1349,29 +1624,41 @@ static void gen_xsxsigqp(DisasContext *ctx) zr =3D tcg_const_i64(0); nan =3D tcg_const_i64(32767); =20 - tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15); + tcg_gen_extract_i64(exp, xbh, 48, 15); tcg_gen_movi_i64(t0, 0x0001000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_andi_i64(xth, cpu_vsrh(rB(ctx->opcode) + 32), 0x0000FFFFFFFFFF= FF); + tcg_gen_andi_i64(xth, xbh, 0x0000FFFFFFFFFFFF); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrl(rB(ctx->opcode) + 32)); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); + tcg_gen_mov_i64(xtl, xbl); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); =20 tcg_temp_free_i64(t0); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } #endif =20 static void gen_xviexpsp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xah =3D cpu_vsrh(xA(ctx->opcode)); - TCGv_i64 xal =3D cpu_vsrl(xA(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xah =3D tcg_temp_new_i64(); + TCGv_i64 xal =3D tcg_temp_new_i64(); + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + TCGv_i64 t0; =20 if (unlikely(!ctx->vsx_enabled)) { @@ -1383,21 +1670,36 @@ static void gen_xviexpsp(DisasContext *ctx) tcg_gen_andi_i64(t0, xbh, 0xFF000000FF); tcg_gen_shli_i64(t0, t0, 23); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF); tcg_gen_andi_i64(t0, xbl, 0xFF000000FF); tcg_gen_shli_i64(t0, t0, 23); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xviexpdp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xah =3D cpu_vsrh(xA(ctx->opcode)); - TCGv_i64 xal =3D cpu_vsrl(xA(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xah =3D tcg_temp_new_i64(); + TCGv_i64 xal =3D tcg_temp_new_i64(); + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + TCGv_i64 t0; =20 if (unlikely(!ctx->vsx_enabled)) { @@ -1409,19 +1711,31 @@ static void gen_xviexpdp(DisasContext *ctx) tcg_gen_andi_i64(t0, xbh, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_andi_i64(xtl, xal, 0x800FFFFFFFFFFFFF); tcg_gen_andi_i64(t0, xbl, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xvxexpsp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -1429,33 +1743,53 @@ static void gen_xvxexpsp(DisasContext *ctx) } tcg_gen_shri_i64(xth, xbh, 23); tcg_gen_andi_i64(xth, xth, 0xFF000000FF); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_shri_i64(xtl, xbl, 23); tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 static void gen_xvxexpdp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } tcg_gen_extract_i64(xth, xbh, 52, 11); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_extract_i64(xtl, xbl, 52, 11); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) =20 static void gen_xvxsigdp(DisasContext *ctx) { - TCGv_i64 xth =3D cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl =3D cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh =3D cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl =3D cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth =3D tcg_temp_new_i64(); + TCGv_i64 xtl =3D tcg_temp_new_i64(); + + TCGv_i64 xbh =3D tcg_temp_new_i64(); + TCGv_i64 xbl =3D tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); =20 TCGv_i64 t0, zr, nan, exp; =20 @@ -1474,6 +1808,7 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); =20 tcg_gen_extract_i64(exp, xbl, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); @@ -1481,11 +1816,16 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_andi_i64(xtl, xbl, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); =20 tcg_temp_free_i64(t0); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } =20 #undef GEN_XX2FORM --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NU3R4FxI/x9lyPAEtypuA7Q9inpm7VB8r05LGRTMWNo=; b=XACLYAdNu62Uqa+Lleee1xo63ruywpwwqPSE12DtkbLFcWyrHwrsXcFL911ZNcsdhK kVBSROoGetIRG5LWSpbMdzlXFjDeLCKWEQ2CVyAzTBBgYEvA21RbthdxJY/RwX+1X6FR cCriGRn8/JJTrSN6VyRYZNeYP2KB873ihNEvc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NU3R4FxI/x9lyPAEtypuA7Q9inpm7VB8r05LGRTMWNo=; b=nqa2hLXSD2LJY6IhnBXXo97mV5uf8wbOJ3SIoOrgBIUWW8aMZHR3Ay/LJrpZrAGveq CO0XzQaRssdCCeTVPp4x/CpInUHY+b2WQ5GHQOd3RUtCWcX4Vymg1y8JzDIEdXaa78HX XW8Yfi7Vmf9K9uSHuGvXTLkGr/5ai41vmbAm0aROYryqNDuiiuTcSPDy8AgK8S6nq0vI ItUBjJI0v37p1ljCmYUrZe0HQrtUOzHkEpbxFu36xKGn4mO6cT8Z5PQ9GTKgUnofGuK9 1uITb8JmR47SGF9hxh6f/QR6LMbgCCsiBfi7EhV1LY4ZnzsnfekLYC3WcTOKfGo6tTwm d2uQ== X-Gm-Message-State: AA+aEWa8sdOGj2zBFbtpNHXOiX2/tUtD4fgu0Ekrzlwe0nSLRf8jufyq zCktsb6YxLHXLGNDlDsYgrmocrOjVEY= X-Google-Smtp-Source: AFSGD/UGImgGhtPgcZDp+M0fWjDSVXuEH4yCB7pFDqvcGm/4YQMTr2T0C1+F2U5XfkjGLajzg3GuAw== X-Received: by 2002:a62:a510:: with SMTP id v16mr15484837pfm.18.1545115172094; Mon, 17 Dec 2018 22:39:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:51 -0800 Message-Id: <20181218063911.2112-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Instead of accessing the FPR, VMX and VSX registers through static arrays of TCGv_i64 globals, remove them and change the helpers to load/store data dir= ectly within cpu_env. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20181217122405.18732-6-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/translate.c | 59 ++++++++--------------------- target/ppc/translate/vsx-impl.inc.c | 4 +- 2 files changed, 18 insertions(+), 45 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa3e8dc114..5923c688cd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -55,15 +55,9 @@ /* global register indexes */ static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ - + 10*4 + 22*5 /* FPR */ - + 2*(10*6 + 22*7) /* AVRh, AVRl */ - + 10*5 + 22*6 /* VSR */ + 8*5 /* CRF */]; static TCGv cpu_gpr[32]; static TCGv cpu_gprh[32]; -static TCGv_i64 cpu_fpr[32]; -static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; -static TCGv_i64 cpu_vsr[32]; static TCGv_i32 cpu_crf[8]; static TCGv cpu_nip; static TCGv cpu_msr; @@ -108,39 +102,6 @@ void ppc_translate_init(void) offsetof(CPUPPCState, gprh[i]), p= ); p +=3D (i < 10) ? 4 : 5; cpu_reg_names_size -=3D (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "fp%d", i); - cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, fpr[i]),= p); - p +=3D (i < 10) ? 4 : 5; - cpu_reg_names_size -=3D (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "avr%dH", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrh[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[0]), p); -#else - cpu_avrh[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[1]), p); -#endif - p +=3D (i < 10) ? 6 : 7; - cpu_reg_names_size -=3D (i < 10) ? 6 : 7; - - snprintf(p, cpu_reg_names_size, "avr%dL", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrl[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[1]), p); -#else - cpu_avrl[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].= u64[0]), p); -#endif - p +=3D (i < 10) ? 6 : 7; - cpu_reg_names_size -=3D (i < 10) ? 6 : 7; - snprintf(p, cpu_reg_names_size, "vsr%d", i); - cpu_vsr[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, vsr[i]),= p); - p +=3D (i < 10) ? 5 : 6; - cpu_reg_names_size -=3D (i < 10) ? 5 : 6; } =20 cpu_nip =3D tcg_global_mem_new(cpu_env, @@ -6696,22 +6657,34 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_mov_i64(dst, cpu_fpr[regno]); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, fpr[regno])); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_mov_i64(cpu_fpr[regno], src); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, fpr[regno])); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { - tcg_gen_mov_i64(dst, (high ? cpu_avrh : cpu_avrl)[regno]); +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 1 : 0)])); +#endif } =20 static inline void set_avr64(int regno, TCGv_i64 src, bool high) { - tcg_gen_mov_i64((high ? cpu_avrh : cpu_avrl)[regno], src); +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + avr[regno].u64[(high ? 1 : 0)])); +#endif } =20 #include "translate/fp-impl.inc.c" diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index e9a05d66f7..20e1fd9324 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -2,12 +2,12 @@ =20 static inline void get_vsr(TCGv_i64 dst, int n) { - tcg_gen_mov_i64(dst, cpu_vsr[n]); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n])); } =20 static inline void set_vsr(int n, TCGv_i64 src) { - tcg_gen_mov_i64(cpu_vsr[n], src); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n])); } =20 static inline void get_cpu_vsrh(TCGv_i64 dst, int n) --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115568609434.3777694543106; Mon, 17 Dec 2018 22:46:08 -0800 (PST) Received: from localhost ([::1]:52053 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ98p-0006cJ-7L for importer@patchew.org; Tue, 18 Dec 2018 01:46:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92r-0001dQ-SH for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92o-0002mm-FZ for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:57 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43637) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92o-00029k-1g for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:54 -0500 Received: by mail-pg1-x541.google.com with SMTP id v28so7335556pgk.10 for ; Mon, 17 Dec 2018 22:39:35 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M3tYypoE1zPYV9p9+Wx3H8RN+xM9ADSh8Bbr/uR2N8s=; b=cJ+TTbAxYrzBUVReZzsmn/Iqh6tt3pXulZca9lcEv72X1kCYZ/STTEmTTFPanpcRJW hinIeqezpHurkRMQ3sIuTbVXG++qRBUlfvvtLmsfeaC7KiYZswIVffJpUICvsOQrXfgl L+5N8L1Mi2bT0FtM2tGC+uR+UAHbSwsCUBFrA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M3tYypoE1zPYV9p9+Wx3H8RN+xM9ADSh8Bbr/uR2N8s=; b=NMIcPVakhlhL0w5/u0VyzidDz9C143hwBt35xvUGFzKWOOd5xjRvqLgb3iYUSC+LZR hPod9eEHKhBe4DQdafMqVtppvD40GUzp/tWDiyqt02umyjT9RvVY/USafelFETrbbKyX MCNd5IMvbVVbquLAq7IB3tDCOJb9CxqhXNIzZL/VNhy46S3hMiPlY1O2GDUdTYWr+cpc B8CfloWMAGdskO3632eEiSKFy7+GycWAHWyAh6UK/chTEJ7yGzkEBChpt3yBV97eDCjA jaSdMc4IML9zxt2KSXU47zPdpGE+jiSY82a2JwNKOwdLi1RO4MAgKRUfqOh3gT3KSmrP KsrQ== X-Gm-Message-State: AA+aEWaqEnxaXqk1PUDfDI8UTO4+Pj0+kElVANtzCiLJdwE+vVDvqZgJ z1pszVDfU7SsUfh+wj0KlKY6nnXPDfU= X-Google-Smtp-Source: AFSGD/VSyzyks31YD4DHWtYPLYJjDT2xLGXmxm6KFNu4hAm2WYqXNIpvnR7VUrwqWRiZH9Qx4+ZFEw== X-Received: by 2002:a63:c451:: with SMTP id m17mr12724276pgg.27.1545115174213; Mon, 17 Dec 2018 22:39:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:52 -0800 Message-Id: <20181218063911.2112-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 15/34] target/ppc: merge ppc_vsr_t and ppc_avr_t union types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Since the VSX registers are actually a superset of the VMX registers then t= hey can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and cha= nge ppc_avr_t to be a simple typedef alias. Note that due to a difference in the naming of the float32 member between ppc_avr_t and ppc_vsr_t, references to the ppc_avr_t f member must be repla= ced with f32 instead. Signed-off-by: Mark Cave-Ayland Message-Id: <20181217122405.18732-7-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/cpu.h | 17 +++++++------ target/ppc/internal.h | 11 -------- target/ppc/int_helper.c | 56 +++++++++++++++++++++-------------------- 3 files changed, 39 insertions(+), 45 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ab68abe8a2..5445d4c3c1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -230,7 +230,6 @@ typedef struct opc_handler_t opc_handler_t; /* Types used to describe some PowerPC registers etc. */ typedef struct DisasContext DisasContext; typedef struct ppc_spr_t ppc_spr_t; -typedef union ppc_avr_t ppc_avr_t; typedef union ppc_tlb_t ppc_tlb_t; typedef struct ppc_hash_pte64 ppc_hash_pte64_t; =20 @@ -254,22 +253,26 @@ struct ppc_spr_t { #endif }; =20 -/* Altivec registers (128 bits) */ -union ppc_avr_t { - float32 f[4]; +/* VSX/Altivec registers (128 bits) */ +typedef union _ppc_vsr_t { uint8_t u8[16]; uint16_t u16[8]; uint32_t u32[4]; + uint64_t u64[2]; int8_t s8[16]; int16_t s16[8]; int32_t s32[4]; - uint64_t u64[2]; int64_t s64[2]; + float32 f32[4]; + float64 f64[2]; + float128 f128; #ifdef CONFIG_INT128 __uint128_t u128; #endif - Int128 s128; -}; + Int128 s128; +} ppc_vsr_t; + +typedef ppc_vsr_t ppc_avr_t; =20 #if !defined(CONFIG_USER_ONLY) /* Software TLB cache */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a9bcadff42..b4b1f7b3db 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -204,17 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8); EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); =20 -typedef union _ppc_vsr_t { - uint8_t u8[16]; - uint16_t u16[8]; - uint32_t u32[4]; - uint64_t u64[2]; - float32 f32[4]; - float64 f64[2]; - float128 f128; - Int128 s128; -} ppc_vsr_t; - #if defined(HOST_WORDS_BIGENDIAN) #define VsrB(i) u8[i] #define VsrH(i) u16[i] diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index fcac90a4a9..9d715be25c 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -548,8 +548,8 @@ VARITH_DO(muluwm, *, u32) { \ int i; \ \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] =3D func(a->f[i], b->f[i], &env->vec_status); \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] =3D func(a->f32[i], b->f32[i], &env->vec_status); \ } \ } VARITHFP(addfp, float32_add) @@ -563,9 +563,9 @@ VARITHFP(maxfp, float32_max) ppc_avr_t *b, ppc_avr_t *c) \ { \ int i; \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] =3D float32_muladd(a->f[i], c->f[i], b->f[i], \ - type, &env->vec_status); \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] =3D float32_muladd(a->f32[i], c->f32[i], b->f32[i], \ + type, &env->vec_status); \ } \ } VARITHFPFMA(maddfp, 0); @@ -670,9 +670,9 @@ VABSDU(w, u32) { \ int i; \ \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ float32 t =3D cvt(b->element[i], &env->vec_status); \ - r->f[i] =3D float32_scalbn(t, -uim, &env->vec_status); \ + r->f32[i] =3D float32_scalbn(t, -uim, &env->vec_status); \ } \ } VCF(ux, uint32_to_float32, u32) @@ -782,9 +782,9 @@ VCMPNE(w, u32, uint32_t, 0) uint32_t none =3D 0; \ int i; \ \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ uint32_t result; \ - int rel =3D float32_compare_quiet(a->f[i], b->f[i], \ + int rel =3D float32_compare_quiet(a->f32[i], b->f32[i], \ &env->vec_status); \ if (rel =3D=3D float_relation_unordered) { = \ result =3D 0; \ @@ -816,14 +816,16 @@ static inline void vcmpbfp_internal(CPUPPCState *env,= ppc_avr_t *r, int i; int all_in =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { - int le_rel =3D float32_compare_quiet(a->f[i], b->f[i], &env->vec_s= tatus); + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { + int le_rel =3D float32_compare_quiet(a->f32[i], b->f32[i], + &env->vec_status); if (le_rel =3D=3D float_relation_unordered) { r->u32[i] =3D 0xc0000000; all_in =3D 1; } else { - float32 bneg =3D float32_chs(b->f[i]); - int ge_rel =3D float32_compare_quiet(a->f[i], bneg, &env->vec_= status); + float32 bneg =3D float32_chs(b->f32[i]); + int ge_rel =3D float32_compare_quiet(a->f32[i], bneg, + &env->vec_status); int le =3D le_rel !=3D float_relation_greater; int ge =3D ge_rel !=3D float_relation_less; =20 @@ -856,11 +858,11 @@ void helper_vcmpbfp_dot(CPUPPCState *env, ppc_avr_t *= r, ppc_avr_t *a, float_status s =3D env->vec_status; \ \ set_float_rounding_mode(float_round_to_zero, &s); \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ - if (float32_is_any_nan(b->f[i])) { \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ + if (float32_is_any_nan(b->f32[i])) { \ r->element[i] =3D 0; \ } else { \ - float64 t =3D float32_to_float64(b->f[i], &s); \ + float64 t =3D float32_to_float64(b->f32[i], &s); \ int64_t j; \ \ t =3D float64_scalbn(t, uim, &s); \ @@ -1661,8 +1663,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc= _avr_t *b) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] =3D float32_div(float32_one, b->f[i], &env->vec_status); + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] =3D float32_div(float32_one, b->f32[i], &env->vec_status= ); } } =20 @@ -1674,8 +1676,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc= _avr_t *b) float_status s =3D env->vec_status; \ \ set_float_rounding_mode(rounding, &s); \ - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] =3D float32_round_to_int (b->f[i], &s); \ + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] =3D float32_round_to_int (b->f32[i], &s); \ } \ } VRFI(n, float_round_nearest_even) @@ -1705,10 +1707,10 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *= r, ppc_avr_t *b) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { - float32 t =3D float32_sqrt(b->f[i], &env->vec_status); + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { + float32 t =3D float32_sqrt(b->f32[i], &env->vec_status); =20 - r->f[i] =3D float32_div(float32_one, t, &env->vec_status); + r->f32[i] =3D float32_div(float32_one, t, &env->vec_status); } } =20 @@ -1751,8 +1753,8 @@ void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *b) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] =3D float32_exp2(b->f[i], &env->vec_status); + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] =3D float32_exp2(b->f32[i], &env->vec_status); } } =20 @@ -1760,8 +1762,8 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, p= pc_avr_t *b) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] =3D float32_log2(b->f[i], &env->vec_status); + for (i =3D 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] =3D float32_log2(b->f32[i], &env->vec_status); } } =20 --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116106451958.8406097965097; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G5CU8MZicozTJp4S8ayy9PViVDnI2UEt5v3xLxv1Hrc=; b=Dp7A+f7UL6O7JcQxEkLSycjkUBI3c1BQ/gFh8XisjjD1NkF8xmTugaawhi54BRWVWU lHUiIqm33Tov4I8lWKeX5uR4os11v7WS9VchUO9gaBr9dd/D3oTxZ770P+a5WD/5WMH5 mf+dN19njYOsTWoFO9gVC/wr6tdl0F8VNhF+8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G5CU8MZicozTJp4S8ayy9PViVDnI2UEt5v3xLxv1Hrc=; b=rAP6XEh9eBWNzagS/HXspid268w7TzaAnSJDfIsuBSPd5qiBLsiCi/zMRay9zpM/8I PUS7TU7QRSQM9ZcCkXItbI6gF5nwE7fp4FJH7YYSnxiguuhnwBP4EFAqIo2QqY/oigFP jjKlCgIAvbgkDi6jRPRgj+XYAjO6jw/cC6rPmnvFhEavY0wm0ynGgpv+WKAJqTTWVb7Y G6K484cm1GwzQRdaqE8PfnzsbbC7p8bFARrNynugAwGyJGS8nN+CzdGu0cWvKWT3eZWZ Pdg+r09ZY7pCA56SaAgKT9OUdeb8I13P01gsy4SJd+ME/cUT3wCCOyUtE0idK5Vc4/vg k9Rg== X-Gm-Message-State: AA+aEWbg5s8kYLSq7QJxAQ++d6nFOuADzbCzPziBbZ7stzBt/qN4zCzG t9u9KdxaQiXPpkTaqS28b+TFxL8MYQU= X-Google-Smtp-Source: AFSGD/WBVVUcR6/Pv9pqJYSelwvT3FQnzS+SYvlEzFdkVQj05BTpqXDgxAkXfKOB27UeKCBzF/OgMw== X-Received: by 2002:a65:520a:: with SMTP id o10mr1909557pgp.276.1545115175402; Mon, 17 Dec 2018 22:39:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:53 -0800 Message-Id: <20181218063911.2112-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vect= or operations, recreate the same layout using an aligned version of the existi= ng vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. T= his also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland Message-Id: <20181217122405.18732-8-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/cpu.h | 9 ++-- target/ppc/internal.h | 18 ++------ linux-user/ppc/signal.c | 24 +++++----- target/ppc/arch_dump.c | 12 ++--- target/ppc/gdbstub.c | 8 ++-- target/ppc/machine.c | 72 +++++++++++++++++++++++++++-- target/ppc/monitor.c | 4 +- target/ppc/translate.c | 14 +++--- target/ppc/translate/dfp-impl.inc.c | 2 +- target/ppc/translate/vmx-impl.inc.c | 7 ++- target/ppc/translate/vsx-impl.inc.c | 4 +- target/ppc/translate_init.inc.c | 24 +++++----- 12 files changed, 126 insertions(+), 72 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5445d4c3c1..c8f449081d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1016,8 +1016,6 @@ struct CPUPPCState { =20 /* Floating point execution context */ float_status fp_status; - /* floating point registers */ - float64 fpr[32]; /* floating point status and control register */ target_ulong fpscr; =20 @@ -1067,11 +1065,10 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Altivec registers */ - ppc_avr_t avr[32]; + /* Vector status and control register */ uint32_t vscr; - /* VSX registers */ - uint64_t vsr[32]; + /* VSX registers (including FP and AVR) */ + ppc_vsr_t vsr[64] QEMU_ALIGNED(16); /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index b4b1f7b3db..b77d564a65 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -218,24 +218,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1,= 6, 6); =20 static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - if (n < 32) { - vsr->VsrD(0) =3D env->fpr[n]; - vsr->VsrD(1) =3D env->vsr[n]; - } else { - vsr->u64[0] =3D env->avr[n - 32].u64[0]; - vsr->u64[1] =3D env->avr[n - 32].u64[1]; - } + vsr->VsrD(0) =3D env->vsr[n].u64[0]; + vsr->VsrD(1) =3D env->vsr[n].u64[1]; } =20 static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - if (n < 32) { - env->fpr[n] =3D vsr->VsrD(0); - env->vsr[n] =3D vsr->VsrD(1); - } else { - env->avr[n - 32].u64[0] =3D vsr->u64[0]; - env->avr[n - 32].u64[1] =3D vsr->u64[1]; - } + env->vsr[n].u64[0] =3D vsr->VsrD(0); + env->vsr[n].u64[1] =3D vsr->VsrD(1); } =20 void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 2ae120a2bc..a053dd5b84 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -258,8 +258,8 @@ static void save_user_regs(CPUPPCState *env, struct tar= get_mcontext *frame) /* Save Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { uint32_t *vrsave; - for (i =3D 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr =3D &env->avr[i]; + for (i =3D 0; i < 32; i++) { + ppc_avr_t *avr =3D &env->vsr[32 + i]; ppc_avr_t *vreg =3D (ppc_avr_t *)&frame->mc_vregs.altivec[i]; =20 __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); @@ -281,15 +281,15 @@ static void save_user_regs(CPUPPCState *env, struct t= arget_mcontext *frame) /* Save VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs =3D (uint64_t *)&frame->mc_vregs.altivec[34]; - for (i =3D 0; i < ARRAY_SIZE(env->vsr); i++) { - __put_user(env->vsr[i], &vsregs[i]); + for (i =3D 0; i < 32; i++) { + __put_user(env->vsr[i].u64[1], &vsregs[i]); } } =20 /* Save floating point registers. */ if (env->insns_flags & PPC_FLOAT) { - for (i =3D 0; i < ARRAY_SIZE(env->fpr); i++) { - __put_user(env->fpr[i], &frame->mc_fregs[i]); + for (i =3D 0; i < 32; i++) { + __put_user(env->vsr[i].u64[0], &frame->mc_fregs[i]); } __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); } @@ -373,8 +373,8 @@ static void restore_user_regs(CPUPPCState *env, #else v_regs =3D (ppc_avr_t *)frame->mc_vregs.altivec; #endif - for (i =3D 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr =3D &env->avr[i]; + for (i =3D 0; i < 32; i++) { + ppc_avr_t *avr =3D &env->vsr[32 + i]; ppc_avr_t *vreg =3D &v_regs[i]; =20 __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); @@ -393,16 +393,16 @@ static void restore_user_regs(CPUPPCState *env, /* Restore VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs =3D (uint64_t *)&frame->mc_vregs.altivec[34]; - for (i =3D 0; i < ARRAY_SIZE(env->vsr); i++) { - __get_user(env->vsr[i], &vsregs[i]); + for (i =3D 0; i < 32; i++) { + __get_user(env->vsr[i].u64[1], &vsregs[i]); } } =20 /* Restore floating point registers. */ if (env->insns_flags & PPC_FLOAT) { uint64_t fpscr; - for (i =3D 0; i < ARRAY_SIZE(env->fpr); i++) { - __get_user(env->fpr[i], &frame->mc_fregs[i]); + for (i =3D 0; i < 32; i++) { + __get_user(env->vsr[i].u64[0], &frame->mc_fregs[i]); } __get_user(fpscr, &frame->mc_fregs[32]); env->fpscr =3D (uint32_t) fpscr; diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index cc1460e4e3..c272d0d3d4 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -140,7 +140,7 @@ static void ppc_write_elf_fpregset(NoteFuncArg *arg, Po= werPCCPU *cpu) memset(fpregset, 0, sizeof(*fpregset)); =20 for (i =3D 0; i < 32; i++) { - fpregset->fpr[i] =3D cpu_to_dump64(s, cpu->env.fpr[i]); + fpregset->fpr[i] =3D cpu_to_dump64(s, cpu->env.vsr[i].u64[0]); } fpregset->fpscr =3D cpu_to_dump_reg(s, cpu->env.fpscr); } @@ -166,11 +166,11 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg,= PowerPCCPU *cpu) #endif =20 if (needs_byteswap) { - vmxregset->avr[i].u64[0] =3D bswap64(cpu->env.avr[i].u64[1]); - vmxregset->avr[i].u64[1] =3D bswap64(cpu->env.avr[i].u64[0]); + vmxregset->avr[i].u64[0] =3D bswap64(cpu->env.vsr[32 + i].u64[= 1]); + vmxregset->avr[i].u64[1] =3D bswap64(cpu->env.vsr[32 + i].u64[= 0]); } else { - vmxregset->avr[i].u64[0] =3D cpu->env.avr[i].u64[0]; - vmxregset->avr[i].u64[1] =3D cpu->env.avr[i].u64[1]; + vmxregset->avr[i].u64[0] =3D cpu->env.vsr[32 + i].u64[0]; + vmxregset->avr[i].u64[1] =3D cpu->env.vsr[32 + i].u64[1]; } } vmxregset->vscr.u32[3] =3D cpu_to_dump32(s, cpu->env.vscr); @@ -188,7 +188,7 @@ static void ppc_write_elf_vsxregset(NoteFuncArg *arg, P= owerPCCPU *cpu) memset(vsxregset, 0, sizeof(*vsxregset)); =20 for (i =3D 0; i < 32; i++) { - vsxregset->vsr[i] =3D cpu_to_dump64(s, cpu->env.vsr[i]); + vsxregset->vsr[i] =3D cpu_to_dump64(s, cpu->env.vsr[i].u64[1]); } } =20 diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index b6f6693583..8c9dc284c4 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -126,7 +126,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *me= m_buf, int n) gdb_get_regl(mem_buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, env->fpr[n-32]); + stfq_p(mem_buf, env->vsr[n - 32].u64[0]); } else { switch (n) { case 64: @@ -178,7 +178,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8= _t *mem_buf, int n) gdb_get_reg64(mem_buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, env->fpr[n-32]); + stfq_p(mem_buf, env->vsr[n - 32].u64[0]); } else if (n < 96) { /* Altivec */ stq_p(mem_buf, n - 64); @@ -234,7 +234,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) env->gpr[n] =3D ldtul_p(mem_buf); } else if (n < 64) { /* fprs */ - env->fpr[n-32] =3D ldfq_p(mem_buf); + env->vsr[n - 32].u64[0] =3D ldfq_p(mem_buf); } else { switch (n) { case 64: @@ -284,7 +284,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint= 8_t *mem_buf, int n) env->gpr[n] =3D ldq_p(mem_buf); } else if (n < 64) { /* fprs */ - env->fpr[n-32] =3D ldfq_p(mem_buf); + env->vsr[n - 32].u64[0] =3D ldfq_p(mem_buf); } else { switch (n) { case 64 + 32: diff --git a/target/ppc/machine.c b/target/ppc/machine.c index e7b3725273..451cf376b4 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -45,7 +45,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) uint64_t l; } u; u.l =3D qemu_get_be64(f); - env->fpr[i] =3D u.d; + env->vsr[i].u64[0] =3D u.d; } qemu_get_be32s(f, &fpscr); env->fpscr =3D fpscr; @@ -138,11 +138,73 @@ static const VMStateInfo vmstate_info_avr =3D { }; =20 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ - VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) + VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) =20 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) =20 +static int get_fpr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + ppc_vsr_t *v =3D pv; + + v->u64[0] =3D qemu_get_be64(f); + + return 0; +} + +static int put_fpr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + ppc_vsr_t *v =3D pv; + + qemu_put_be64(f, v->u64[0]); + return 0; +} + +static const VMStateInfo vmstate_info_fpr =3D { + .name =3D "fpr", + .get =3D get_fpr, + .put =3D put_fpr, +}; + +#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) + +#define VMSTATE_FPR_ARRAY(_f, _s, _n) \ + VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) + +static int get_vsr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + ppc_vsr_t *v =3D pv; + + v->u64[1] =3D qemu_get_be64(f); + + return 0; +} + +static int put_vsr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + ppc_vsr_t *v =3D pv; + + qemu_put_be64(f, v->u64[1]); + return 0; +} + +static const VMStateInfo vmstate_info_vsr =3D { + .name =3D "vsr", + .get =3D get_vsr, + .put =3D put_vsr, +}; + +#define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) + +#define VMSTATE_VSR_ARRAY(_f, _s, _n) \ + VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) + static bool cpu_pre_2_8_migration(void *opaque, int version_id) { PowerPCCPU *cpu =3D opaque; @@ -354,7 +416,7 @@ static const VMStateDescription vmstate_fpu =3D { .minimum_version_id =3D 1, .needed =3D fpu_needed, .fields =3D (VMStateField[]) { - VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), + VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_UINTTL(env.fpscr, PowerPCCPU), VMSTATE_END_OF_LIST() }, @@ -373,7 +435,7 @@ static const VMStateDescription vmstate_altivec =3D { .minimum_version_id =3D 1, .needed =3D altivec_needed, .fields =3D (VMStateField[]) { - VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), + VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_UINT32(env.vscr, PowerPCCPU), VMSTATE_END_OF_LIST() }, @@ -392,7 +454,7 @@ static const VMStateDescription vmstate_vsx =3D { .minimum_version_id =3D 1, .needed =3D vsx_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), + VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_END_OF_LIST() }, }; diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c index 14915119fc..1db9396b2e 100644 --- a/target/ppc/monitor.c +++ b/target/ppc/monitor.c @@ -123,8 +123,8 @@ int target_get_monitor_def(CPUState *cs, const char *na= me, uint64_t *pval) =20 /* Floating point registers */ if ((qemu_tolower(name[0]) =3D=3D 'f') && - ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->fpr), ®num)) { - *pval =3D env->fpr[regnum]; + ppc_cpu_get_reg_num(name + 1, 32, ®num)) { + *pval =3D env->vsr[regnum].u64[0]; return 0; } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5923c688cd..8e89aec14d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6657,22 +6657,22 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, fpr[regno])); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, fpr[regno])); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { #ifdef HOST_WORDS_BIGENDIAN tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - avr[regno].u64[(high ? 0 : 1)])); + vsr[32 + regno].u64[(high ? 0 : = 1)])); #else tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - avr[regno].u64[(high ? 1 : 0)])); + vsr[32 + regno].u64[(high ? 1 : = 0)])); #endif } =20 @@ -6680,10 +6680,10 @@ static inline void set_avr64(int regno, TCGv_i64 sr= c, bool high) { #ifdef HOST_WORDS_BIGENDIAN tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - avr[regno].u64[(high ? 0 : 1)])); + vsr[32 + regno].u64[(high ? 0 : = 1)])); #else tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - avr[regno].u64[(high ? 1 : 0)])); + vsr[32 + regno].u64[(high ? 1 : = 0)])); #endif } =20 @@ -7434,7 +7434,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, if ((i & (RFPL - 1)) =3D=3D 0) { cpu_fprintf(f, "FPR%02d", i); } - cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); + cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->vsr[i].u64[= 0])); if ((i & (RFPL - 1)) =3D=3D (RFPL - 1)) { cpu_fprintf(f, "\n"); } diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp= -impl.inc.c index 634ef73b8a..6c556dc2e1 100644 --- a/target/ppc/translate/dfp-impl.inc.c +++ b/target/ppc/translate/dfp-impl.inc.c @@ -3,7 +3,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg])); + tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); return r; } =20 diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 30046c6e31..75d2b2280f 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -10,10 +10,15 @@ static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); + tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0= ])); return r; } =20 +static inline long avr64_offset(int reg, bool high) +{ + return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]); +} + #define GEN_VR_LDX(name, opc2, opc3) = \ static void glue(gen_, name)(DisasContext *ctx) = \ { = \ diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 20e1fd9324..1608ad48b1 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -2,12 +2,12 @@ =20 static inline void get_vsr(TCGv_i64 dst, int n) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n])); + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); } =20 static inline void set_vsr(int n, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n])); + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); } =20 static inline void get_cpu_vsrh(TCGv_i64 dst, int n) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 168d0cec28..b83097141c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9486,7 +9486,7 @@ static bool avr_need_swap(CPUPPCState *env) static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { - stfq_p(mem_buf, env->fpr[n]); + stfq_p(mem_buf, env->vsr[n].u64[0]); ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } @@ -9502,7 +9502,7 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_= t *mem_buf, int n) { if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); - env->fpr[n] =3D ldfq_p(mem_buf); + env->vsr[n].u64[0] =3D ldfq_p(mem_buf); return 8; } if (n =3D=3D 32) { @@ -9517,11 +9517,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_= t *mem_buf, int n) { if (n < 32) { if (!avr_need_swap(env)) { - stq_p(mem_buf, env->avr[n].u64[0]); - stq_p(mem_buf+8, env->avr[n].u64[1]); + stq_p(mem_buf, env->vsr[32 + n].u64[0]); + stq_p(mem_buf + 8, env->vsr[32 + n].u64[1]); } else { - stq_p(mem_buf, env->avr[n].u64[1]); - stq_p(mem_buf+8, env->avr[n].u64[0]); + stq_p(mem_buf, env->vsr[32 + n].u64[1]); + stq_p(mem_buf + 8, env->vsr[32 + n].u64[0]); } ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); @@ -9546,11 +9546,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_= t *mem_buf, int n) ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); if (!avr_need_swap(env)) { - env->avr[n].u64[0] =3D ldq_p(mem_buf); - env->avr[n].u64[1] =3D ldq_p(mem_buf+8); + env->vsr[32 + n].u64[0] =3D ldq_p(mem_buf); + env->vsr[32 + n].u64[1] =3D ldq_p(mem_buf + 8); } else { - env->avr[n].u64[1] =3D ldq_p(mem_buf); - env->avr[n].u64[0] =3D ldq_p(mem_buf+8); + env->vsr[32 + n].u64[1] =3D ldq_p(mem_buf); + env->vsr[32 + n].u64[0] =3D ldq_p(mem_buf + 8); } return 16; } @@ -9623,7 +9623,7 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t = *mem_buf, int n) static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { - stq_p(mem_buf, env->vsr[n]); + stq_p(mem_buf, env->vsr[n].u64[1]); ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } @@ -9634,7 +9634,7 @@ static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t = *mem_buf, int n) { if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); - env->vsr[n] =3D ldq_p(mem_buf); + env->vsr[n].u64[1] =3D ldq_p(mem_buf); return 8; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 17/34] target/ppc: convert VMX logical instructions to use vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20181217122405.18732-9-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/translate.c | 1 + target/ppc/translate/vmx-impl.inc.c | 63 ++++++++++++++++------------- 2 files changed, 37 insertions(+), 27 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8e89aec14d..1b61bfa093 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -24,6 +24,7 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" =20 diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 75d2b2280f..c13828a09d 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -262,41 +262,50 @@ GEN_VX_VMUL10(vmul10euq, 1, 0); GEN_VX_VMUL10(vmul10cuq, 0, 1); GEN_VX_VMUL10(vmul10ecuq, 1, 1); =20 -/* Logical operations */ -#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) = \ +#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv_i64 t0 =3D tcg_temp_new_i64(); \ - TCGv_i64 t1 =3D tcg_temp_new_i64(); \ - TCGv_i64 avr =3D tcg_temp_new_i64(); \ - \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - get_avr64(t0, rA(ctx->opcode), true); \ - get_avr64(t1, rB(ctx->opcode), true); \ - tcg_op(avr, t0, t1); \ - set_avr64(rD(ctx->opcode), avr, true); \ \ - get_avr64(t0, rA(ctx->opcode), false); \ - get_avr64(t1, rB(ctx->opcode), false); \ - tcg_op(avr, t0, t1); \ - set_avr64(rD(ctx->opcode), avr, false); \ - \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(avr); \ + tcg_op(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rA(ctx->opcode), true), \ + avr64_offset(rB(ctx->opcode), true), \ + 16, 16); \ } =20 -GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); -GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); -GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); -GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); -GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); -GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); -GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); -GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); +#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + tcg_op(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rA(ctx->opcode), true), \ + avr64_offset(rB(ctx->opcode), true), \ + 16, 16); \ + \ + tcg_gen_gvec_not(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rD(ctx->opcode), true), \ + 16, 16); \ +} + +/* Logical operations */ +GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); +GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); +GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); +GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); +GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20); +GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26); +GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22); +GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); =20 #define GEN_VXFORM(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) = \ --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154511638758020.987720853256178; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DfEDAOBAUOVsP11aCnwKVwokisF0su/yccCWcjyBBKI=; b=Px/c15PIrd0d24Su/5y6db5UoaFfY1ZCGoIgD5D6wQdXgg700JbVIe88mSsrMT9f17 fLlBexL4zPNYcdfhoKZLXJESOaSvJN2F7vavHsBGAKskh9MLEadHLhRhSZhNAd91a075 Hx1Cu3m3oqTVe7eC5Jg1Z+qCvKMA28QnFs3Ao= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DfEDAOBAUOVsP11aCnwKVwokisF0su/yccCWcjyBBKI=; b=T9LOVOAT8Na/jp+ueMsX9ssiRxbLE0lnya2lxYzclCNPtGJn0QpwCyhlD4joCAqaT6 byAVQ5CpyEByLTXyHp393sbSHkCsztraDdL9yadUAf/Nix1CkmrhlKsDUtzmwp8i4WBw ZV3kRs5Qb8mUci3F039nQgOfGYkGsCDZOdeI3htH+XC/1rRDL9gakpnQ0MWOjLruIXI/ yXGzxiKCIOsGF4f6vIiO5+B74xyoJeKKr4yUALSlhLkzXqQy7BQL1/GNnMlxbxjgjR6r E+rt8KkMZJkY800M+v2IYZSMCGSazTamZeFhwMfbXiipewn5KMsW+ZiaTH05iT3ddcZh GDLw== X-Gm-Message-State: AA+aEWYUwkx+A4a5XxKNDcAw0OMwtSYwZLAyqx2ChpnBZNVuBtISB58b hUcs3Sy2iUn8CzoN7GrTtAdF2CY/W0I= X-Google-Smtp-Source: AFSGD/WSufZTixa2iraHohwCujpA9b/YeQbVvJpdKb1tiQqlfYZsezDX8YEhpJoy0Z1i27BOVoVyxQ== X-Received: by 2002:a65:6645:: with SMTP id z5mr14880357pgv.351.1545115178247; Mon, 17 Dec 2018 22:39:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:55 -0800 Message-Id: <20181218063911.2112-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 18/34] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over to use vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20181217122405.18732-10-mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson --- target/ppc/helper.h | 8 -------- target/ppc/int_helper.c | 7 ------- target/ppc/translate/vmx-impl.inc.c | 16 ++++++++-------- 3 files changed, 8 insertions(+), 23 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index c7de04e068..553ff500c8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,14 +108,6 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i6= 4) #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr =20 -DEF_HELPER_3(vaddubm, void, avr, avr, avr) -DEF_HELPER_3(vadduhm, void, avr, avr, avr) -DEF_HELPER_3(vadduwm, void, avr, avr, avr) -DEF_HELPER_3(vaddudm, void, avr, avr, avr) -DEF_HELPER_3(vsububm, void, avr, avr, avr) -DEF_HELPER_3(vsubuhm, void, avr, avr, avr) -DEF_HELPER_3(vsubuwm, void, avr, avr, avr) -DEF_HELPER_3(vsubudm, void, avr, avr, avr) DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) DEF_HELPER_3(vavguw, void, avr, avr, avr) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 9d715be25c..4547453ef1 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -531,13 +531,6 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b) r->element[i] =3D a->element[i] op b->element[i]; \ } \ } -#define VARITH(suffix, element) \ - VARITH_DO(add##suffix, +, element) \ - VARITH_DO(sub##suffix, -, element) -VARITH(ubm, u8) -VARITH(uhm, u16) -VARITH(uwm, u32) -VARITH(udm, u64) VARITH_DO(muluwm, *, u32) #undef VARITH_DO #undef VARITH diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index c13828a09d..e353d3f174 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -411,18 +411,18 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_temp_free_ptr(rb); \ } =20 -GEN_VXFORM(vaddubm, 0, 0); +GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM(vadduhm, 0, 1); +GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ vmul10ecuq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vadduwm, 0, 2); -GEN_VXFORM(vaddudm, 0, 3); -GEN_VXFORM(vsububm, 0, 16); -GEN_VXFORM(vsubuhm, 0, 17); -GEN_VXFORM(vsubuwm, 0, 18); -GEN_VXFORM(vsubudm, 0, 19); +GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); +GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); +GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); +GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); +GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); +GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); GEN_VXFORM(vmaxub, 1, 0); GEN_VXFORM(vmaxuh, 1, 1); GEN_VXFORM(vmaxuw, 1, 2); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116644957208.6420561583625; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MkmjLnCmuY4EjGai5glHUVjL1YN82v4g8w9+k1ILEeA=; b=VB5zsPZF2SXip/gBTORjMwKxXaNwR4Z8xI0Q/1PeZXnYEg5/l7ceAYrUuwl3c4L97k oT8nWGtR/XwJCmqlkjPGtYR1pd5yC5udOxdcyiv+EKDeBOy17a1mGvLTyEvKHXnlrCw5 4SxJB4r3Hp6jf34UP+WWTxBlOBYm6fQz8PeCY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MkmjLnCmuY4EjGai5glHUVjL1YN82v4g8w9+k1ILEeA=; b=U4hDhIadY8BRLR3DEdCHx9S/Q/UHCneZSNuKEMbqKb0hMd+LSJvddaYUeJwVCowFRe owuEVz7GVInxzig4Im6SNxJfZYw2BqiM08wmkYXcBQ8yvx6qOhTt/nnzoYOCEA0AQdn9 QEaVdlMauCo5Ntjq1SW/Q0OM3UHW1/dU42SbnWw8376IvXmgrHRtMhqH6m2bHRnZ5asQ l+LFh9EBnH/HM6ThdGDHpAI4ODUr+7pn9/0GsiCBmENEVjZAvWz7UkAZVb2i0CbeJz+n xxEUk3vfNaNeDuh2ovqDQEzAm4pjRgNq8TuA91JQVcEPv8AmNFDs5O9Y8hGDWnXn82RI W7lQ== X-Gm-Message-State: AA+aEWbGpKrFIlsx3SV/U8/zFfD08ZcclqXbJecrvMzqMRWzkYEn6Z9o 8aEBi1w49WhZi53gRcYqSk8zKufeQqQ= X-Google-Smtp-Source: AFSGD/VGSoStGFL+WeRxeZvC/37dxvuBqW7d35tZeeMDpr8briCNAo+NNeEStvp8r4WO25oVxusa7Q== X-Received: by 2002:a63:f515:: with SMTP id w21mr14684241pgh.220.1545115179453; Mon, 17 Dec 2018 22:39:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:56 -0800 Message-Id: <20181218063911.2112-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/helper.h | 3 --- target/ppc/int_helper.c | 15 ------------ target/ppc/translate/vmx-impl.inc.c | 36 +++++++---------------------- 3 files changed, 8 insertions(+), 46 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 553ff500c8..2aa60e5d36 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -246,9 +246,6 @@ DEF_HELPER_3(vrld, void, avr, avr, avr) DEF_HELPER_3(vsl, void, avr, avr, avr) DEF_HELPER_3(vsr, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) -DEF_HELPER_2(vspltisb, void, avr, i32) -DEF_HELPER_2(vspltish, void, avr, i32) -DEF_HELPER_2(vspltisw, void, avr, i32) DEF_HELPER_3(vspltb, void, avr, avr, i32) DEF_HELPER_3(vsplth, void, avr, avr, i32) DEF_HELPER_3(vspltw, void, avr, avr, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 4547453ef1..e44c0d90ee 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -2066,21 +2066,6 @@ VNEG(vnegw, s32) VNEG(vnegd, s64) #undef VNEG =20 -#define VSPLTI(suffix, element, splat_type) \ - void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat) \ - { \ - splat_type x =3D (int8_t)(splat << 3) >> 3; \ - int i; \ - \ - for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - r->element[i] =3D x; \ - } \ - } -VSPLTI(b, s8, int8_t) -VSPLTI(h, s16, int16_t) -VSPLTI(w, s32, int32_t) -#undef VSPLTI - #define VSR(suffix, element, mask) \ void helper_vsr##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ { \ diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index e353d3f174..be638cdb1a 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -720,25 +720,21 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) =20 -#define GEN_VXFORM_SIMM(name, opc2, opc3) \ +#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv_ptr rd; \ - TCGv_i32 simm; \ + int simm; \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - simm =3D tcg_const_i32(SIMM5(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name (rd, simm); \ - tcg_temp_free_i32(simm); \ - tcg_temp_free_ptr(rd); \ + simm =3D SIMM5(ctx->opcode); \ + tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \ } =20 -GEN_VXFORM_SIMM(vspltisb, 6, 12); -GEN_VXFORM_SIMM(vspltish, 6, 13); -GEN_VXFORM_SIMM(vspltisw, 6, 14); +GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12); +GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13); +GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14); =20 #define GEN_VXFORM_NOA(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) = \ @@ -818,22 +814,6 @@ GEN_VXFORM_NOA(vprtybw, 1, 24); GEN_VXFORM_NOA(vprtybd, 1, 24); GEN_VXFORM_NOA(vprtybq, 1, 24); =20 -#define GEN_VXFORM_SIMM(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) = \ - { \ - TCGv_ptr rd; \ - TCGv_i32 simm; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - simm =3D tcg_const_i32(SIMM5(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name (rd, simm); \ - tcg_temp_free_i32(simm); \ - tcg_temp_free_ptr(rd); \ - } - #define GEN_VXFORM_UIMM(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) = \ { \ @@ -1255,7 +1235,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, #undef GEN_VXRFORM_DUAL #undef GEN_VXRFORM1 #undef GEN_VXRFORM -#undef GEN_VXFORM_SIMM +#undef GEN_VXFORM_DUPI #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545117223248619.7948824756709; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SXcmeu5bjYHVse3xR5bVWi80NcPVDPvpXGM2YXZ3FDs=; b=YKWUVpu96ThH9ylAIhYSD7RTZOoEgfXhTgWIjvWE5XG0Sb5AEc64jcEwhMQUrRm1Ij Xrb8UNxDZROAMkJ9cq6/1vI3AhHUElQek9DoCCdyGqeCJ8zI5h+EHsCvgs2d2nRKc3Q+ w6jcim/oMLRnDiG3douaVy3ko7klyhyPb80KY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SXcmeu5bjYHVse3xR5bVWi80NcPVDPvpXGM2YXZ3FDs=; b=Z7I0yzS8GG1r3UAX0E0wKDw5FY/dS096dZZBXwgjkTn3ST4KxMoYxuj+uz6smeKWFb U9ikHQ43PxrEwOPTN+YKhy+r5yJ30zrggoGlqTvq21bg7RhqrSqBaeFGoMxTaDKHhE8k IjEXfEO2bu7hq+oDgSg/rv7/l7/7sLCQiuaeF+cRMd/XhdU3gMr6hCoWMeflG6+IdmRU Li5G9t6Ka4FvkjzcIaR76+esMnueyaarlSR8/KoX/3oykUGf/BWVEOc2+XaCY/cYeNF2 kuuAN8tC0YRrOgvRfOyuLvQEPMs51grOLJU9v8SwztsbA8RCocencWyCMtCJDP0nwsbG 0zsw== X-Gm-Message-State: AA+aEWZNFJsKebyIzhkuaj015u1qdkqbh+L1G/3IjewTqBRibnz6YIxH QdyFg6QSiewwHVzSuvFpwnUrrlwOD7k= X-Google-Smtp-Source: AFSGD/XHx/W4IjqLscmXiFQcpfVnRj+p3g4398tBjI3bpsl/bzPN+2b9UjoS1ERzd4sJ71j776X9pA== X-Received: by 2002:a63:a41:: with SMTP id z1mr1848708pgk.117.1545115180667; Mon, 17 Dec 2018 22:39:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:57 -0800 Message-Id: <20181218063911.2112-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/helper.h | 3 -- target/ppc/int_helper.c | 24 --------------- target/ppc/translate/vmx-impl.inc.c | 45 +++++++++++++++++------------ 3 files changed, 26 insertions(+), 46 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 2aa60e5d36..069daa9883 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -246,9 +246,6 @@ DEF_HELPER_3(vrld, void, avr, avr, avr) DEF_HELPER_3(vsl, void, avr, avr, avr) DEF_HELPER_3(vsr, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) -DEF_HELPER_3(vspltb, void, avr, avr, i32) -DEF_HELPER_3(vsplth, void, avr, avr, i32) -DEF_HELPER_3(vspltw, void, avr, avr, i32) DEF_HELPER_3(vextractub, void, avr, avr, i32) DEF_HELPER_3(vextractuh, void, avr, avr, i32) DEF_HELPER_3(vextractuw, void, avr, avr, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index e44c0d90ee..3bf0fdb6c5 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1918,30 +1918,6 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) #endif } =20 -/* Experimental testing shows that hardware masks the immediate. */ -#define _SPLAT_MASKED(element) (splat & (ARRAY_SIZE(r->element) - 1)) -#if defined(HOST_WORDS_BIGENDIAN) -#define SPLAT_ELEMENT(element) _SPLAT_MASKED(element) -#else -#define SPLAT_ELEMENT(element) \ - (ARRAY_SIZE(r->element) - 1 - _SPLAT_MASKED(element)) -#endif -#define VSPLT(suffix, element) \ - void helper_vsplt##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \ - { \ - uint32_t s =3D b->element[SPLAT_ELEMENT(element)]; \ - int i; \ - \ - for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - r->element[i] =3D s; \ - } \ - } -VSPLT(b, u8) -VSPLT(h, u16) -VSPLT(w, u32) -#undef VSPLT -#undef SPLAT_ELEMENT -#undef _SPLAT_MASKED #if defined(HOST_WORDS_BIGENDIAN) #define VINSERT(suffix, element) = \ void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index= ) \ diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index be638cdb1a..529ae0e5f5 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -814,24 +814,31 @@ GEN_VXFORM_NOA(vprtybw, 1, 24); GEN_VXFORM_NOA(vprtybd, 1, 24); GEN_VXFORM_NOA(vprtybq, 1, 24); =20 -#define GEN_VXFORM_UIMM(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) = \ - { \ - TCGv_ptr rb, rd; \ - TCGv_i32 uimm; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - uimm =3D tcg_const_i32(UIMM5(ctx->opcode)); \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name (rd, rb, uimm); \ - tcg_temp_free_i32(uimm); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ +static void gen_vsplt(DisasContext *ctx, int vece) +{ + int uimm, dofs, bofs; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; } =20 + uimm =3D UIMM5(ctx->opcode); + bofs =3D avr64_offset(rB(ctx->opcode), true); + dofs =3D avr64_offset(rD(ctx->opcode), true); + + /* Experimental testing shows that hardware masks the immediate. */ + bofs +=3D (uimm << vece) & 15; +#ifndef HOST_WORDS_BIGENDIAN + bofs ^=3D 15; +#endif + + tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16); +} + +#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); } + #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ @@ -873,9 +880,9 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_temp_free_ptr(rd); \ } =20 -GEN_VXFORM_UIMM(vspltb, 6, 8); -GEN_VXFORM_UIMM(vsplth, 6, 9); -GEN_VXFORM_UIMM(vspltw, 6, 10); +GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8); +GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9); +GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10); GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15); GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14); GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116127375597.1337141514435; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Blx++t/+8e3x4h5xs8nsjg1AqfkSW8Uuocvlldz1kUI=; b=cLtTlB0CvAUUS72krce0w4NNUya1lAPXlJLtoW792F2B61JyTqN6+XPtt4xYL1TzcC OETD2sgJkfOWEPCcbqV5938zccEnUfkDtA8PfqFh6E7jAOsjrDvMWkG4nZKn1CSDDuoq eh08q7ngsed59V5J38oqcUpc/zAlFqJSkwhXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Blx++t/+8e3x4h5xs8nsjg1AqfkSW8Uuocvlldz1kUI=; b=c8ysZh1ef8pxsd/rPcCpAFKnmo9XyfgPjcsymspzhnJUcZUkDX0YUoBL4Ko/FR3CC5 AR9Sm1HYsGbV7Szp3Jk1yxHOl6lUAlFR8RApJdKf4k7czTR0JCSU0N3A6CumRA1sG2nz xVP5tQK62d+5OKCzsWgM85PYRyLLMwoGJMGKsRNerhsQLb5xYMtAFVJgtZtwhCHcCqwq rXFYvLXT7kL1NYPriZojmGNc9ubmrO1qqCcx062U4y15eF4MHWIiN6+hVRAtPwW9bbx1 FDqzyL6FwdbAxEYeZAv9oQof8jcQeDb7hj+VpOOWgOSooIw9X7f3SK1r9CDb/sgZL/TZ tRug== X-Gm-Message-State: AA+aEWbf+6BF8dbjF9Z5opViXJ+eaH0sYij+E+sk7F110k0zOip3Vffv B6pqem1NqdUY6O97AUQzsz2eIn22pQI= X-Google-Smtp-Source: AFSGD/VJZQ8rCtlvB56vKGsUdtWGann8hoq2RYvQ25YdrLaubRUMGYOl/y8q38K7c8mO+jBeTZg2Ew== X-Received: by 2002:a63:f412:: with SMTP id g18mr11647641pgi.262.1545115181944; Mon, 17 Dec 2018 22:39:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:58 -0800 Message-Id: <20181218063911.2112-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vmx-impl.inc.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 529ae0e5f5..329131d30b 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -277,34 +277,14 @@ static void glue(gen_, name)(DisasContext *ctx) = \ 16, 16); \ } =20 -#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - tcg_op(vece, \ - avr64_offset(rD(ctx->opcode), true), \ - avr64_offset(rA(ctx->opcode), true), \ - avr64_offset(rB(ctx->opcode), true), \ - 16, 16); \ - \ - tcg_gen_gvec_not(vece, \ - avr64_offset(rD(ctx->opcode), true), \ - avr64_offset(rD(ctx->opcode), true), \ - 16, 16); \ -} - /* Logical operations */ GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); -GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20); -GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26); -GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22); +GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20); +GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26); +GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22); GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); =20 #define GEN_VXFORM(name, opc2, opc3) \ --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154511633220179.34099270667548; Mon, 17 Dec 2018 22:58:52 -0800 (PST) Received: from localhost ([::1]:52127 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9L8-0000MG-Oi for importer@patchew.org; Tue, 18 Dec 2018 01:58:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92y-0001iH-59 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92s-0002tH-G7 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:04 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:34060) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92r-0002Ta-Rg for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:58 -0500 Received: by mail-pg1-x52b.google.com with SMTP id j10so6136811pga.1 for ; Mon, 17 Dec 2018 22:39:44 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/mPaOY+aA1IJmM7Rfj1xBIO/Pp254zxtD1fh9vhH2PQ=; b=Pv3MZmXU+gqUEI5LSc4x45XTYcvhmXnFxL9zVKVUEg1iJsDoO1XMW/nBgqNu+jp0ok pJeHtommkLHL4eOKZ9DmKRUX57D3y1ezBqPUm/ZEuK7H+TjQguWdsUPQDB15jwakG2sC Hlmz/IrSYWKM+DshlMafgvnsoyPrFQFxrWWVc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/mPaOY+aA1IJmM7Rfj1xBIO/Pp254zxtD1fh9vhH2PQ=; b=Bibj5fuKb22nvGK17i1TxE7h3sxrfQ+lrrPueq5ciImt073hRHk5yYhjtIzRC/I6A9 duIDrTCEZRcE1DhaR2YUcT//s6pcsRZs6rwdFlGU9rhtJzo1L6uJ1u0eAEVjQM6+wxDX D15sd5eddTP5tbcxCbcNxQK3FroKf6uCN2AXGhqd4KOS5Hx8mXnlHw+9hHxWSOVXrYpn UNHhbm+si69oevvRqYudIJsCNsIDGQGVKUs92GaRwoOhwxMmeQI10II4r4Sf2ts63FQK bTJwi+1GnRFZaJBTt7erWN4Qvt1InIwMIDtDbBUEV5wk23NlEly/Cso0wyrF2dS30Swr 3CVw== X-Gm-Message-State: AA+aEWZgGMJxvoss8n/qr+91oLHwP/bpB9jVj/glYquKdFlF2upzzi9y 7w1p3NMKnlKudw7L+WjDdFDRtBi0L30= X-Google-Smtp-Source: AFSGD/Usdn9oCg9movRdof39qHFBGt84r6RiGrB3a4UVlDDEdIiMPpQmkQHt6nvselhWftxs5pUAAA== X-Received: by 2002:a65:5a4c:: with SMTP id z12mr14674029pgs.188.1545115183377; Mon, 17 Dec 2018 22:39:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:59 -0800 Message-Id: <20181218063911.2112-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 43 ++++++++++++----------------- 1 file changed, 17 insertions(+), 26 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 1608ad48b1..8ab1290026 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -10,6 +10,11 @@ static inline void set_vsr(int n, TCGv_i64 src) tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); } =20 +static inline int vsr_full_offset(int n) +{ + return offsetof(CPUPPCState, vsr[n].u64[0]); +} + static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { if (n < 32) { @@ -1214,40 +1219,26 @@ static void gen_xxbrw(DisasContext *ctx) tcg_temp_free_i64(xbl); } =20 -#define VSX_LOGICAL(name, tcg_op) \ +#define VSX_LOGICAL(name, vece, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - t0 =3D tcg_temp_new_i64(); \ - t1 =3D tcg_temp_new_i64(); \ - t2 =3D tcg_temp_new_i64(); \ - get_cpu_vsrh(t0, xA(ctx->opcode)); \ - get_cpu_vsrh(t1, xB(ctx->opcode)); \ - tcg_op(t2, t0, t1); \ - set_cpu_vsrh(xT(ctx->opcode), t2); \ - get_cpu_vsrl(t0, xA(ctx->opcode)); \ - get_cpu_vsrl(t1, xB(ctx->opcode)); \ - tcg_op(t2, t0, t1); \ - set_cpu_vsrl(xT(ctx->opcode), t2); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ + tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \ + vsr_full_offset(xA(ctx->opcode)), \ + vsr_full_offset(xB(ctx->opcode)), 16, 16); \ } =20 -VSX_LOGICAL(xxland, tcg_gen_and_i64) -VSX_LOGICAL(xxlandc, tcg_gen_andc_i64) -VSX_LOGICAL(xxlor, tcg_gen_or_i64) -VSX_LOGICAL(xxlxor, tcg_gen_xor_i64) -VSX_LOGICAL(xxlnor, tcg_gen_nor_i64) -VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64) -VSX_LOGICAL(xxlnand, tcg_gen_nand_i64) -VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) +VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and) +VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc) +VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or) +VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor) +VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor) +VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv) +VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand) +VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc) =20 #define VSX_XXMRG(name, high) \ static void glue(gen_, name)(DisasContext * ctx) \ --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115906293257.7638520200077; Mon, 17 Dec 2018 22:51:46 -0800 (PST) Received: from localhost ([::1]:52084 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9EH-0002hP-0E for importer@patchew.org; Tue, 18 Dec 2018 01:51:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ934-0001sB-IX for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92u-0002x3-PI for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:10 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42873) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0002Wx-FA for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:00 -0500 Received: by mail-pg1-x543.google.com with SMTP id d72so7338497pga.9 for ; Mon, 17 Dec 2018 22:39:45 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wJ6refrKK9bsJzJvMv7G5+VyDes8vGvaBDUrOMaWwh8=; b=Ncri+3iATwPiPEoXh5EsZpb/Z56fXV6M2wL1NiqWLwsulSE2sYXXM5wwAzyxittF7S ulBv4AlKB27HzPQjJPAk/u8w1M9iHJENA1KLj4TDPuHhJJBic75HClSnjowrD5h70OMB 4fBfmiB/kgDurUh5Bs2XjikipJTP15BOqj5BI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wJ6refrKK9bsJzJvMv7G5+VyDes8vGvaBDUrOMaWwh8=; b=o1RmFYCBDfoNeZHpZqsSOXJNGT7V1Lr9xG1HKSar84Q9n2UFKMZxe5rtGDs6Kb5AB7 +I7zVqMfnD84I0+UnYBrV0ddRyva18q3c8gnd2w1qQgNsmRcEx0dHUWMXjFr/sELJ0iR E/TA3DS40x+/61Xrn8zUdVBs+Gy321x16DtQJb5rBTQ+0WVYw6Fs/Ng997zZNYqrxKl1 +ZWbJq0GRzwgaCjX4kW+t5NbIYELZ+s0/dodYyTcww9yLt8UYnlgrCYl/bHiaDohMgbZ oOdQ9C2xiMvjEaWOXLCD/4tr4sXXP4ShXIUqVQLhAmuGCy3GO6Jq+xIPJsq5Mv/M8w48 WrYQ== X-Gm-Message-State: AA+aEWbO9+cGOu/+O1J8P/KvUUh8Tzn74aWlIdyG2dGY2IfM2iRMfkDY g/zSwySZmGCfBBpyB17C7aKJ63KQW8w= X-Google-Smtp-Source: AFSGD/Wz32isHIOXoE8OmtI9UWmkkUcYGFjo5VTs0xDJr7a4/uKktHo9nOvYrXjDZCPrvVALHcTEsg== X-Received: by 2002:a63:8149:: with SMTP id t70mr15078577pgd.172.1545115184452; Mon, 17 Dec 2018 22:39:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:00 -0800 Message-Id: <20181218063911.2112-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 8ab1290026..d88d6bbd74 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1356,9 +1356,10 @@ static void gen_xxspltw(DisasContext *ctx) =20 static void gen_xxspltib(DisasContext *ctx) { - unsigned char uim8 =3D IMM8(ctx->opcode); - TCGv_i64 vsr =3D tcg_temp_new_i64(); - if (xS(ctx->opcode) < 32) { + uint8_t uim8 =3D IMM8(ctx->opcode); + int rt =3D xT(ctx->opcode); + + if (rt < 32) { if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); return; @@ -1369,10 +1370,7 @@ static void gen_xxspltib(DisasContext *ctx) return; } } - tcg_gen_movi_i64(vsr, pattern(uim8)); - set_cpu_vsrh(xT(ctx->opcode), vsr); - set_cpu_vsrl(xT(ctx->opcode), vsr); - tcg_temp_free_i64(vsr); + tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8); } =20 static void gen_xxsldwi(DisasContext *ctx) --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545117078378504.0813250114088; Mon, 17 Dec 2018 23:11:18 -0800 (PST) Received: from localhost ([::1]:52217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9X6-000216-Ny for importer@patchew.org; Tue, 18 Dec 2018 02:11:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ934-0001s8-IK for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92v-0002xp-Bm for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:10 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0002a2-VS for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:01 -0500 Received: by mail-pg1-x543.google.com with SMTP id n2so7350519pgm.3 for ; Mon, 17 Dec 2018 22:39:46 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G/n0AtjzKeXwi2DOVDVEH8AoSvsXLdyE81u7l7jdtpE=; b=Rkv6RHSBDhKp459NEvsMaKECfjPUg/3B+5kOnsKeh+BihrAYM9np05xImHR1r1rqx9 w7cn2pZqCeLqBiS6spONNXDiXpz6KC06LtGkH0wBzScgGe+4WsLalJD9fn6DFGhIF4EB WzS04crtdOY6qVrAks/6PmY2eo8fKWV+UH4Jc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G/n0AtjzKeXwi2DOVDVEH8AoSvsXLdyE81u7l7jdtpE=; b=Rm5qhz3K7dgZJuYK7F2xDvFqy5WjQdeSszMIvma+Gp8lqVgP4b+7bshtE/4wHcwJGD NiYYQFvFI9MVkOpy5owgHIF4pJOkyWGBEzsKL59dsYjGyOP3JbQaOAPmW4FWeOSCIsvX jtsWjrp8HYLliA41OgJuVmYWUTXYg6eggem4Mw/YvuGoRtxKO7ziPSRwWkzdwv4O7NKl zu84xW/yDvnBzLe9CfvTNshjyGWK50/28QQ0LvNjDyWh88Jz8qb4FTZGJ3Uj7Z8juypA zB0H3qZxw7HuiUh7y0jqplT3eYzOmi3nXl1dM9jqj0EoPU5qV0MjOSPVpdPEVW07Hi69 pxOw== X-Gm-Message-State: AA+aEWa2wOSGprbmbHTVzNyNlzMR7RuaO9yLbQOu8J79X1GxCcisyGpS ZQKHPbjYYjRoF+hjz3/Cv1zJjVupEgE= X-Google-Smtp-Source: AFSGD/XqQ+9welMvSblbSGO8Dkh52z+redRRs0XUkCZFN9zaAcIsmA0MC8U0QiCkf+5t14xvdNzHIw== X-Received: by 2002:a65:520a:: with SMTP id o10mr1909877pgp.276.1545115185643; Mon, 17 Dec 2018 22:39:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:01 -0800 Message-Id: <20181218063911.2112-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 24/34] target/ppc: convert xxspltw to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 36 +++++++++-------------------- 1 file changed, 11 insertions(+), 25 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index d88d6bbd74..a040038ed4 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1318,38 +1318,24 @@ static void gen_xxsel(DisasContext * ctx) =20 static void gen_xxspltw(DisasContext *ctx) { - TCGv_i64 b, b2; - TCGv_i64 vsr; - - vsr =3D tcg_temp_new_i64(); - if (UIM(ctx->opcode) & 2) { - get_cpu_vsrl(vsr, xB(ctx->opcode)); - } else { - get_cpu_vsrh(vsr, xB(ctx->opcode)); - } + int rt =3D xT(ctx->opcode); + int rb =3D xB(ctx->opcode); + int uim =3D UIM(ctx->opcode); + int tofs, bofs; =20 if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } =20 - b =3D tcg_temp_new_i64(); - b2 =3D tcg_temp_new_i64(); + tofs =3D vsr_full_offset(rt); + bofs =3D vsr_full_offset(rb); + bofs +=3D uim << MO_32; +#ifndef HOST_WORDS_BIG_ENDIAN + bofs ^=3D 8 | 4; +#endif =20 - if (UIM(ctx->opcode) & 1) { - tcg_gen_ext32u_i64(b, vsr); - } else { - tcg_gen_shri_i64(b, vsr, 32); - } - - tcg_gen_shli_i64(b2, b, 32); - tcg_gen_or_i64(vsr, b, b2); - set_cpu_vsrh(xT(ctx->opcode), vsr); - set_cpu_vsrl(xT(ctx->opcode), vsr); - - tcg_temp_free_i64(vsr); - tcg_temp_free_i64(b); - tcg_temp_free_i64(b2); + tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16); } =20 #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff)) --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115480170552.8792757683112; Mon, 17 Dec 2018 22:44:40 -0800 (PST) Received: from localhost ([::1]:52042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ97O-0005OC-QX for importer@patchew.org; Tue, 18 Dec 2018 01:44:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ930-0001m5-VU for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92t-0002vG-SF for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:06 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42874) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92t-0002fD-I8 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:59 -0500 Received: by mail-pg1-x543.google.com with SMTP id d72so7338573pga.9 for ; Mon, 17 Dec 2018 22:39:49 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e9sbYZtWNeSqAkktYrwPzYVucFa+O20EgxyH5iSp3Ug=; b=igL+oZVf0MHYg40/KlUAOjV2R5/6vxtWK+jKDmWEFf7hltLnsyE9HTy7h/bVNjRHmL OYlY4D+1TCVDck4MAm+IGAGQ3eWEXyMkJioAJ+3fVwKaWtoMGlUa5LvIOFnM4uutLIGX JWnyN+LWsBhoPj9YEVjSpsudyRw5N3xDZ4Vcg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e9sbYZtWNeSqAkktYrwPzYVucFa+O20EgxyH5iSp3Ug=; b=AfxZKg4vzESg/2TBNomlryjR39GSFYWT4+zn9dWjoQ6bGZ24+uta+Av26izxsQ9DSu cErSvbgFWJcxSABE4ZHJWx5KLkO4ybbSQCLUB6W4xz7tvHkX3KsbsVa4qT+OxrRpMmHa wd+UTij/JsUOjJe70C5NLbksHPIDtuX3zWorx6I6jcJAw+4hqM3MBZGLGARVxNeRL+jq Blw7ZUvO4T8RjY807AEX5zaCliV4JDpd0NUkQ/3CXLrrpmjHwqY9BtGu84GZSw7Sc7BK 6KLwm0xbOO5It8SYsrO9+RnnoVcrNp21OiPXvshx3EMMto36s41HnlMQrZYevo/frALH gvsw== X-Gm-Message-State: AA+aEWYIj3fzweKigdG4MXdhN10fqCqgxThefRuNg1CTWqVKcRKxelQE 11Jxd9ud0OeyLnc+I2DZfJq5g3RZA0U= X-Google-Smtp-Source: AFSGD/VWcWqZs8I2tJyGbil9hAZzR32E6ThXe1uIYwpjmX6CnGolhlpayAdcNBw/pg7+O4fF5HqI6Q== X-Received: by 2002:a63:6150:: with SMTP id v77mr14467051pgb.266.1545115186890; Mon, 17 Dec 2018 22:39:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:02 -0800 Message-Id: <20181218063911.2112-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 25/34] target/ppc: convert xxsel to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 55 ++++++++++++++--------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index a040038ed4..dc32471cd7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1280,40 +1280,39 @@ static void glue(gen_, name)(DisasContext * ctx) = \ VSX_XXMRG(xxmrghw, 1) VSX_XXMRG(xxmrglw, 0) =20 +static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) +{ + tcg_gen_and_i64(b, b, c); + tcg_gen_andc_i64(a, a, c); + tcg_gen_or_i64(t, a, b); +} + +static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a, + TCGv_vec b, TCGv_vec c) +{ + tcg_gen_and_vec(vece, b, b, c); + tcg_gen_andc_vec(vece, a, a, c); + tcg_gen_or_vec(vece, t, a, b); +} + static void gen_xxsel(DisasContext * ctx) { - TCGv_i64 a, b, c, tmp; + static const GVecGen4 g =3D { + .fni8 =3D xxsel_i64, + .fniv =3D xxsel_vec, + .vece =3D MO_64, + }; + int rt =3D xT(ctx->opcode); + int ra =3D xA(ctx->opcode); + int rb =3D xB(ctx->opcode); + int rc =3D xC(ctx->opcode); + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - a =3D tcg_temp_new_i64(); - b =3D tcg_temp_new_i64(); - c =3D tcg_temp_new_i64(); - tmp =3D tcg_temp_new_i64(); - - get_cpu_vsrh(a, xA(ctx->opcode)); - get_cpu_vsrh(b, xB(ctx->opcode)); - get_cpu_vsrh(c, xC(ctx->opcode)); - - tcg_gen_and_i64(b, b, c); - tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(tmp, a, b); - set_cpu_vsrh(xT(ctx->opcode), tmp); - - get_cpu_vsrl(a, xA(ctx->opcode)); - get_cpu_vsrl(b, xB(ctx->opcode)); - get_cpu_vsrl(c, xC(ctx->opcode)); - - tcg_gen_and_i64(b, b, c); - tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(tmp, a, b); - set_cpu_vsrl(xT(ctx->opcode), tmp); - - tcg_temp_free_i64(a); - tcg_temp_free_i64(b); - tcg_temp_free_i64(c); - tcg_temp_free_i64(tmp); + tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra), + vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g); } =20 static void gen_xxspltw(DisasContext *ctx) --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115895218459.17685493552983; Mon, 17 Dec 2018 22:51:35 -0800 (PST) Received: from localhost ([::1]:52083 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9E5-0002YJ-Rh for importer@patchew.org; Tue, 18 Dec 2018 01:51:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92t-0001fH-RS for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92q-0002py-Pm for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:59 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:36692) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92q-0002iw-Cp for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:56 -0500 Received: by mail-pf1-x434.google.com with SMTP id b85so7655504pfc.3 for ; Mon, 17 Dec 2018 22:39:50 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=070cEypBjZxfxUYkH8IwPesDYg9dOtX7CjVcZ/KHhDs=; b=Dw0oIX2xkkyBJCt1iOLm90FiVz8gBPiJofFMlIWgB7Drh364Nf9PYQ5N51u90qVOmY UO4jzOlKjCGdSHcm0S98+iR16xVTc0DOfW9ygb7H1KqTtWFFjjbGXJd62RRM7VgJQeXQ hn9Wgqm6CcfpseVGhJOzLsZbO9fpomYf1Q5gY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=070cEypBjZxfxUYkH8IwPesDYg9dOtX7CjVcZ/KHhDs=; b=DKB5AkOm/jUi+9KQ3ENtYyKK+MuFwDg179sP9m+Ex+2uoUKJ+DmefURDW3AAjEglUj mCaAWz85esgu6r/fdfk049R6xlLCDSBYrd/ZO6eIRWw+JEDWqB1xcZyEPpQs8Vc19MZ0 1vDfOD2mcwA4u6lzjrfUqU5eSJ8tXLAyr8wjO8o7z0c+21uWRrPizb+uh+MhTyh6Zigg /xnv24wsDQhLGHk7zgzA+S2yH0DPGQRQvk/sURoT7a2gzvClZiBUYs2/cKVGqOguu2uQ VHINlxaY5y0io6rbEkHDLqv4CVtGbEJRC+5tivVSYmzyiuCLEt6S0lKOI/0qIN3FseNx 7+4A== X-Gm-Message-State: AA+aEWZHtlacFsujeATNab9xNlPPKY9+/X/mHtFKSmSUO4ROVwIEqJyz vCgG5rX4H3U8e5iuyLh+2ysqhb8ku9U= X-Google-Smtp-Source: AFSGD/WnK9NYLxncAWXAYIyzT+MbddoZPNrE03BE8GrwIKmQJ+DLd1YiVYoKstBX3OU1i+JaoJ/HAw== X-Received: by 2002:aa7:83c6:: with SMTP id j6mr15523958pfn.91.1545115189005; Mon, 17 Dec 2018 22:39:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:03 -0800 Message-Id: <20181218063911.2112-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH 26/34] target/ppc: Pass integer to helper_mtvscr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can re-use this helper elsewhere if we're not passing in an entire vector register. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/helper.h | 2 +- target/ppc/int_helper.c | 10 +++------- target/ppc/translate/vmx-impl.inc.c | 17 +++++++++++++---- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 069daa9883..b3ffe28103 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -294,7 +294,7 @@ DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr) -DEF_HELPER_2(mtvscr, void, env, avr) +DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_3(lvebx, void, env, avr, tl) DEF_HELPER_3(lvehx, void, env, avr, tl) DEF_HELPER_3(lvewx, void, env, avr, tl) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 3bf0fdb6c5..0443f33cd2 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -469,14 +469,10 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh) } } =20 -void helper_mtvscr(CPUPPCState *env, ppc_avr_t *r) +void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { -#if defined(HOST_WORDS_BIGENDIAN) - env->vscr =3D r->u32[3]; -#else - env->vscr =3D r->u32[0]; -#endif - set_flush_to_zero(vscr_nj, &env->vec_status); + env->vscr =3D vscr; + set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } =20 void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 329131d30b..ab6da3aa55 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -196,14 +196,23 @@ static void gen_mfvscr(DisasContext *ctx) =20 static void gen_mtvscr(DisasContext *ctx) { - TCGv_ptr p; + TCGv_i32 val; + int bofs; + if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); return; } - p =3D gen_avr_ptr(rB(ctx->opcode)); - gen_helper_mtvscr(cpu_env, p); - tcg_temp_free_ptr(p); + + val =3D tcg_temp_new_i32(); + bofs =3D avr64_offset(rB(ctx->opcode), true); +#ifdef HOST_WORDS_BIGENDIAN + bofs +=3D 3 * 4; +#endif + + tcg_gen_ld_i32(val, cpu_env, bofs); + gen_helper_mtvscr(cpu_env, val); + tcg_temp_free_i32(val); } =20 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116789814272.00109692940487; Mon, 17 Dec 2018 23:06:29 -0800 (PST) Received: from localhost ([::1]:52187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9SW-00071Z-Gf for importer@patchew.org; Tue, 18 Dec 2018 02:06:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ931-0001mk-Ev for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92u-0002wE-DO for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:07 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:37998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0002jg-2B for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:00 -0500 Received: by mail-pf1-x434.google.com with SMTP id q1so7651546pfi.5 for ; Mon, 17 Dec 2018 22:39:51 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YW7kNEnh0p74b8tmNGS0tI6jmUKC29mBQcE1tHBFKh8=; b=TucXQbdma+auyfCjcQSjbQVeKjgdf/Up2OVuuSFsXTwkgmmoK+Y5q/2/LyDB1r+SCv AaSve5KC4HFiaidppN3guQYyupZcfDRUavRnJYCoXtrG86XyVwh/PE3m+AicU5IhtTEn mCsx7O1N+cgtu5S4RJWJ1s8Hrp8dcrZsHBWyA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YW7kNEnh0p74b8tmNGS0tI6jmUKC29mBQcE1tHBFKh8=; b=ndQ1A5AjyXsIfvMpcxU2B1w8uIdhYLmymKakkcYLq/LQkRiu69GFPihp7MPWK3Xx87 2w+eo53hVe0vTPAULBMLb/IxCB9oi9pWJ3ayc96+ebNObDf0lPW4B2jSP0VVkYnMlI8B eOeuHbvKcEpcOSrAJDU6HdfU7eMheJyBT4eT6cFK57/osAWbdIyzxo3HXW+LEs7XEokh VmTkFS3nOXGOdYOEM5XthQqJlATGoUy2nPpLEHRRFqy+gMm2kXnywhE1IB+BjHQ0ylzx KfY38qJ0QHl5DwCGc1/WkGUaulXSvjbGgV4c0ZMsk8XXXSrYQuf5UVEM+cyhuD9mOXuf HY2Q== X-Gm-Message-State: AA+aEWYt7w/eD2Iptti2dEPi2Fblkcmx3GPWWksMtmsK+p9bTlV0+En7 0UcqHQwuDS9dWkAzfr3RSQVP0fbpTg8= X-Google-Smtp-Source: AFSGD/VnV4QE3olM1VtZg+C+7RtlveUZxMB5Y3iYiK7/HFSjxxpHXe5rPQhMmJm6rtayckVj7g7s/A== X-Received: by 2002:a62:c28e:: with SMTP id w14mr15547502pfk.115.1545115190167; Mon, 17 Dec 2018 22:39:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:04 -0800 Message-Id: <20181218063911.2112-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not setting flush_to_zero from gdb_set_avr_reg was a bug. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate_init.inc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index b83097141c..292b1df700 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -601,10 +601,9 @@ static void spr_write_excp_vector(DisasContext *ctx, i= nt sprn, int gprn) =20 static inline void vscr_init(CPUPPCState *env, uint32_t val) { - env->vscr =3D val; /* Altivec always uses round-to-nearest */ set_float_rounding_mode(float_round_nearest_even, &env->vec_status); - set_flush_to_zero(vscr_nj, &env->vec_status); + helper_mtvscr(env, val); } =20 #ifdef CONFIG_USER_ONLY @@ -9556,7 +9555,7 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t = *mem_buf, int n) } if (n =3D=3D 32) { ppc_maybe_bswap_register(env, mem_buf, 4); - env->vscr =3D ldl_p(mem_buf); + helper_mtvscr(env, ldl_p(mem_buf)); return 4; } if (n =3D=3D 33) { --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154511574751576.51692329028435; Mon, 17 Dec 2018 22:49:07 -0800 (PST) Received: from localhost ([::1]:52068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9Bi-0000Xv-3Z for importer@patchew.org; Tue, 18 Dec 2018 01:49:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92r-0001dS-TW for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92q-0002oo-0Z for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:57 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33330) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92p-0002kn-Bx for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:55 -0500 Received: by mail-pg1-x544.google.com with SMTP id z11so7360434pgu.0 for ; Mon, 17 Dec 2018 22:39:52 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=95bC4PshL9/gRRw60p20ZTjAk8iqlop3uJI1xroQkSE=; b=RfR6iWKAkpLSIVrdHhN89korvb7sKI3MWwXR7ik7geGrvgHf9Qmds9Tggnga3Xqewx P0IxQ4isieJ4FXymk4mmpdIcZenjKN1gBSc96EAVUE1u/jW+ITmeNV9EIdwFA0fQroa8 e+SL7qBJpGaxYSDTSXEwlnTTcxqVJQzMf+n00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=95bC4PshL9/gRRw60p20ZTjAk8iqlop3uJI1xroQkSE=; b=Qs7VDQLqZE9dhTyGUfpImJyEnrWCCc+DhnMK6hHNAl6dgapab9YxukUqfiXVSoLsEe kc51AM14eQCXDJX7mJBfko5ojQTMNXIH25thexspT+c7ainigqV+9QVp+B/qO+Eg2FBJ cS/wu8Ceba1fpxJDQoDa6i82avpU3uxpD2ftFcKl7sJnWBokHSTIYEjU7DSAk7vmKVfv 7nINYcMlklpXDmWPv4TYqQi1GfoLdjBp0ObJfTqg10FFX40cqiFTNx7ghbWHOqhiFJjn gkllFAq3kibznqFIeKGuwsVkpMtoLaqq5iHS60SyC6WM3Nell172iwqs+g4B8MJTnVeU 21SA== X-Gm-Message-State: AA+aEWYRQLbgT0i6cCNSdNf3BWoRkq8ijQ3/dErSMlGdYyZ/QcrIMR02 5U7fIEJBZB1zDuX1MBIgeHZWnqkew4A= X-Google-Smtp-Source: AFSGD/WybdO9qCZRva08japjU/M78L+r1W2bZgvoz+MjQAMDArGxfcM6UAyRat9WtHACkfY5UVOuTg== X-Received: by 2002:a63:165e:: with SMTP id 30mr14784493pgw.103.1545115191297; Mon, 17 Dec 2018 22:39:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:05 -0800 Message-Id: <20181218063911.2112-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 28/34] target/ppc: Remove vscr_nj and vscr_sat X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These macros are no longer used. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c8f449081d..a2fe6058b1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -700,8 +700,6 @@ enum { /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */ #define VSCR_SAT 0 /* Vector saturation */ -#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) -#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) =20 /*************************************************************************= ****/ /* BookE e500 MMU registers */ --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154511690165639.272085143235245; Mon, 17 Dec 2018 23:08:21 -0800 (PST) Received: from localhost ([::1]:52202 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9UF-0008D8-BL for importer@patchew.org; Tue, 18 Dec 2018 02:08:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ933-0001p4-1P for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92u-0002w5-CE for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:08 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:33328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0002lO-1I for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:00 -0500 Received: by mail-pg1-x541.google.com with SMTP id z11so7360465pgu.0 for ; Mon, 17 Dec 2018 22:39:53 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZrBpnbx7YF++UHHSdYwnXTWh9J6az0qW7yMUWdUpg/c=; b=Nn+z94fH2k/lI4tWiobU8W6slxfS2Pkp1d1Duit1E7FZcmUvm0VVuBHkILZhaLyUOL ncydktHBg403IG95dUkRLhlX1UOek4oTiexhUzSD5GMC5Xg5obSXaNm6lHPPQ3DhYXaj nbWe9vDA+WOHeNzQmGT+FvOS4KE6swB6IfOws= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZrBpnbx7YF++UHHSdYwnXTWh9J6az0qW7yMUWdUpg/c=; b=Y8ETfq0RaD+1MJInIkyTECKJ+O7jreYO7pIHqTrVvBwhGMJ0ktLzupUx9ZRgqkYjPB YtELKWGV3IMqwD0+k3I4w/EhE8zExp8p06l2tTUkBmQeTQp2cvIzVrVU5Sq0+Tq3TPK9 +cZYSKMZsm5cB02d2UeqDw+rp85yrgUXY8S3ZEIlWm1lE5onJF5McUvx65YjDXqz1R+9 zfL+mpcBOKbuIBJTk4V3GFABNcc2wqnSRz3nDH8l7rOk6Ik6hpVbZFFm/Agi1SPMvUI/ qySnZ+POfHRPRuuH3w3SnQEFbcXaEFSiCO+yrHYg8RsYsn01YCVhuFcDV8uArhiE22Ct mcCg== X-Gm-Message-State: AA+aEWYc9aY2o8W3TxvqzHNcYL9r+A8ezoytPaMVYNoqFQhwbKjUh2RS ZxMZBNyzxIVE/9hGBqZqkWtxuqmPUf8= X-Google-Smtp-Source: AFSGD/VH0Jvg4XddBJPFArWSSRRWS4zNf2ihcTFoOeA0hLLu0BQEJNnJgTS1w4NsteyhiuqVoLDaTA== X-Received: by 2002:a63:de04:: with SMTP id f4mr14477247pgg.292.1545115192550; Mon, 17 Dec 2018 22:39:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:06 -0800 Message-Id: <20181218063911.2112-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is required before changing the representation of the register. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/arch_dump.c | 3 ++- target/ppc/int_helper.c | 5 +++++ target/ppc/translate/vmx-impl.inc.c | 2 +- target/ppc/translate_init.inc.c | 2 +- 5 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index b3ffe28103..7dbb08b9dd 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -295,6 +295,7 @@ DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env) DEF_HELPER_3(lvebx, void, env, avr, tl) DEF_HELPER_3(lvehx, void, env, avr, tl) DEF_HELPER_3(lvewx, void, env, avr, tl) diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index c272d0d3d4..f753798789 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -17,6 +17,7 @@ #include "elf.h" #include "sysemu/dump.h" #include "sysemu/kvm.h" +#include "exec/helper-proto.h" =20 #ifdef TARGET_PPC64 #define ELFCLASS ELFCLASS64 @@ -173,7 +174,7 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg, P= owerPCCPU *cpu) vmxregset->avr[i].u64[1] =3D cpu->env.vsr[32 + i].u64[1]; } } - vmxregset->vscr.u32[3] =3D cpu_to_dump32(s, cpu->env.vscr); + vmxregset->vscr.u32[3] =3D cpu_to_dump32(s, helper_mfvscr(&cpu->env)); } =20 static void ppc_write_elf_vsxregset(NoteFuncArg *arg, PowerPCCPU *cpu) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 0443f33cd2..75201bbba6 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -475,6 +475,11 @@ void helper_mtvscr(CPUPPCState *env, uint32_t vscr) set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } =20 +uint32_t helper_mfvscr(CPUPPCState *env) +{ + return env->vscr; +} + void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index ab6da3aa55..1c0c461241 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -187,7 +187,7 @@ static void gen_mfvscr(DisasContext *ctx) tcg_gen_movi_i64(avr, 0); set_avr64(rD(ctx->opcode), avr, true); t =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); + gen_helper_mfvscr(t, cpu_env); tcg_gen_extu_i32_i64(avr, t); set_avr64(rD(ctx->opcode), avr, false); tcg_temp_free_i32(t); diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 292b1df700..353285c6bd 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9527,7 +9527,7 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t = *mem_buf, int n) return 16; } if (n =3D=3D 32) { - stl_p(mem_buf, env->vscr); + stl_p(mem_buf, helper_mfvscr(env)); ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116460223804.7367805786996; Mon, 17 Dec 2018 23:01:00 -0800 (PST) Received: from localhost ([::1]:52147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9NC-0002QO-MS for importer@patchew.org; Tue, 18 Dec 2018 02:00:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92z-0001kN-Rc for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92t-0002ug-J8 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:05 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:35047) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92s-0002nX-SC for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:59 -0500 Received: by mail-pg1-x544.google.com with SMTP id s198so7352692pgs.2 for ; Mon, 17 Dec 2018 22:39:55 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1s64UqmeR6s+cjzurqiz1uvvH8UBU0oqlpEZmmz7mWg=; b=QXBnmbX5HEVsdDCYEfy4JpIzF7RIiuSe8bOXObmdDGwWudrmPF3lebMEYv4sMao8X0 d0Obuflu6zi/OCC0dcYX0TVOipPq38kLBc01Gd3btEUBrdn7AtAYc+JOg6daaihMZ++2 9A3TKpv+zh7eyVVhii31fp5AUtyL51BU020BQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1s64UqmeR6s+cjzurqiz1uvvH8UBU0oqlpEZmmz7mWg=; b=CGf2tddfm+sSr30ZGQVDejiQkni8gRQFI8FvBhNZLhYt0qmNK9THN7Pg4AHg/h1Sk/ U8YWA82Gv4Fh7xEwn2R2CjUglqidzjgJZnqVeTXu9az64ORWwE3OAfLp+1A98VSn0amd ysSFxI5K3WtKEcMDhje7ZQdMIICYh/CVzyVJGu8oNb5Ho6ZvmPJl0K50FAgEm4q06A94 iDBApxeMPddvIk1L9aojAVoxfLcxedBxaf+AOY7QUrJFqVp0zjZnt1YwyJs4xg69RxIZ 6rDZ9zwjelJSNQDCT6MbbILGEWLuvIZ/K+RID1lvegXyzC+9vZ18WOMZcEifLsGNTJPf 6MDA== X-Gm-Message-State: AA+aEWb7cTXO66Ojs4TBRV060SVVhVh+HTheOLTrzPlzvO59iybizuW+ UOYxtN3D5v2FQW/kwaIo8uycaHSO+eg= X-Google-Smtp-Source: AFSGD/VqRCpesRh7otEW8lgbVfPlT53ApyIEEMmU940ZbejN4Qhhc9wGqZLasyCg7DBjEMC8zhaEpA== X-Received: by 2002:a62:f5da:: with SMTP id b87mr15800396pfm.253.1545115194189; Mon, 17 Dec 2018 22:39:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:07 -0800 Message-Id: <20181218063911.2112-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is required before changing the representation of the register. Signed-off-by: Richard Henderson --- target/ppc/machine.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 451cf376b4..3c27a89166 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -10,6 +10,7 @@ #include "migration/cpu.h" #include "qapi/error.h" #include "kvm_ppc.h" +#include "exec/helper-proto.h" =20 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { @@ -17,7 +18,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) CPUPPCState *env =3D &cpu->env; unsigned int i, j; target_ulong sdr1; - uint32_t fpscr; + uint32_t fpscr, vscr; #if defined(TARGET_PPC64) int32_t slb_nr; #endif @@ -84,7 +85,8 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) if (!cpu->vhyp) { ppc_store_sdr1(env, sdr1); } - qemu_get_be32s(f, &env->vscr); + qemu_get_be32s(f, &vscr); + helper_mtvscr(env, vscr); qemu_get_be64s(f, &env->spe_acc); qemu_get_be32s(f, &env->spe_fscr); qemu_get_betls(f, &env->msr_mask); @@ -429,6 +431,28 @@ static bool altivec_needed(void *opaque) return (cpu->env.insns_flags & PPC_ALTIVEC); } =20 +static int get_vscr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + PowerPCCPU *cpu =3D opaque; + helper_mtvscr(&cpu->env, qemu_get_be32(f)); + return 0; +} + +static int put_vscr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + PowerPCCPU *cpu =3D opaque; + qemu_put_be32(f, helper_mfvscr(&cpu->env)); + return 0; +} + +static const VMStateInfo vmstate_vscr =3D { + .name =3D "cpu/altivec/vscr", + .get =3D get_vscr, + .put =3D put_vscr, +}; + static const VMStateDescription vmstate_altivec =3D { .name =3D "cpu/altivec", .version_id =3D 1, @@ -436,7 +460,21 @@ static const VMStateDescription vmstate_altivec =3D { .needed =3D altivec_needed, .fields =3D (VMStateField[]) { VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), - VMSTATE_UINT32(env.vscr, PowerPCCPU), + /* + * Save the architecture value of the vscr, not the internally + * expanded version. Since this architecture value does not + * exist in memory to be stored, this requires a but of hoop + * jumping. We want OFFSET=3D0 so that we effectively pass CPU + * to the helper functions. + */ + { + .name =3D "vscr", + .version_id =3D 0, + .size =3D sizeof(uint32_t), + .info =3D &vmstate_vscr, + .flags =3D VMS_SINGLE, + .offset =3D 0 + }, VMSTATE_END_OF_LIST() }, }; --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116232473377.33445629515563; Mon, 17 Dec 2018 22:57:12 -0800 (PST) Received: from localhost ([::1]:52120 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9JX-0007DO-3q for importer@patchew.org; Tue, 18 Dec 2018 01:57:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92v-0001fg-Tq for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92r-0002rw-R0 for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:01 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:38630) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92r-0002p7-AI for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:57 -0500 Received: by mail-pg1-x541.google.com with SMTP id g189so7344540pgc.5 for ; Mon, 17 Dec 2018 22:39:56 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ME/4+nurOdE1yQJ1DxhO1wjJsToD86j8nY3sLe3Yfc=; b=fmvwm6LJW0EoGqPsMBZSW+2nx17WTQGMBfIk+1qTlXlAKhOEeMz6bB6IswiCPcqweH BHg5mWgQBd2B8hhwYnPaHYq39aRDHik8jtBnYRCxVzskzfKZlowSOfxSa3yfrUkqOGiA UYjnys0TDkrjhO1aXXjr5my/UURz6JuDkTjfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ME/4+nurOdE1yQJ1DxhO1wjJsToD86j8nY3sLe3Yfc=; b=CKCOU2VGhH/bKRdQCv2g3uOfhUegFXCaTNvg3xnW90ihKTwT19mO2FAqG4JFDgZZn6 ByAH7d6xz9j/DAqjg+31a+zDgnMXz9LfcPPAfJwqb6Kki/7LSaIKrcH+CU8oRMGlBHkg BhwZDgiqgckL2hcCBrZlSRahsTEQY+q7Iam10I4F39rmewGGQSP9vxNLwReYS0Y2gymy NeOZtCIO6uwOoN1inz5J7YPtTI6ApjKEvXONXivpzrUgyJyXkGJNSsxitGo2clCxqZLG HjAu+7+yUSMF6k4pc3zaSRgU/iayVpxZMpR2W3PYPq4tkPfN/b7BeH6MBB5EN0h2gTr6 /35A== X-Gm-Message-State: AA+aEWZWDQM5MwtrjKbFg6NGPUhfy+kVIj23NTrrTuLTPHAmQ4tjYwPx TlZTdUw+O91LBB1p7kYI6ZoRTuAhfQM= X-Google-Smtp-Source: AFSGD/VgnxymKu5E3oNyzpG0XeACRndGhKZRGJ5IPnEXgHorwwYeWv+alYlRlS5GqyMyJvQQgdwFAA== X-Received: by 2002:a62:7f93:: with SMTP id a141mr223597pfd.96.1545115195527; Mon, 17 Dec 2018 22:39:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:08 -0800 Message-Id: <20181218063911.2112-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 31/34] target/ppc: Add set_vscr_sat X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is required before changing the representation of the register. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/int_helper.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 75201bbba6..38aa3e85a6 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -480,6 +480,11 @@ uint32_t helper_mfvscr(CPUPPCState *env) return env->vscr; } =20 +static inline void set_vscr_sat(CPUPPCState *env) +{ + env->vscr |=3D 1 << VSCR_SAT; +} + void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i; @@ -593,7 +598,7 @@ VARITHFPFMA(nmsubfp, float_muladd_negate_result | float= _muladd_negate_c); } \ } \ if (sat) { \ - env->vscr |=3D (1 << VSCR_SAT); \ + set_vscr_sat(env); \ } \ } #define VARITHSAT_SIGNED(suffix, element, optype, cvt) \ @@ -865,7 +870,7 @@ void helper_vcmpbfp_dot(CPUPPCState *env, ppc_avr_t *r,= ppc_avr_t *a, } \ } \ if (sat) { \ - env->vscr |=3D (1 << VSCR_SAT); \ + set_vscr_sat(env); \ } \ } VCT(uxs, cvtsduw, u32) @@ -916,7 +921,7 @@ void helper_vmhaddshs(CPUPPCState *env, ppc_avr_t *r, p= pc_avr_t *a, } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -933,7 +938,7 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -1061,7 +1066,7 @@ void helper_vmsumshs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -1114,7 +1119,7 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -1633,7 +1638,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) } \ *r =3D result; \ if (dosat && sat) { \ - env->vscr |=3D (1 << VSCR_SAT); \ + set_vscr_sat(env); \ } \ } #define I(x, y) (x) @@ -2106,7 +2111,7 @@ void helper_vsumsws(CPUPPCState *env, ppc_avr_t *r, p= pc_avr_t *a, ppc_avr_t *b) *r =3D result; =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -2133,7 +2138,7 @@ void helper_vsum2sws(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, ppc_avr_t *b) =20 *r =3D result; if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -2152,7 +2157,7 @@ void helper_vsum4sbs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, ppc_avr_t *b) } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -2169,7 +2174,7 @@ void helper_vsum4shs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, ppc_avr_t *b) } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 @@ -2188,7 +2193,7 @@ void helper_vsum4ubs(CPUPPCState *env, ppc_avr_t *r, = ppc_avr_t *a, ppc_avr_t *b) } =20 if (sat) { - env->vscr |=3D (1 << VSCR_SAT); + set_vscr_sat(env); } } =20 --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545116547816353.3690365782594; Mon, 17 Dec 2018 23:02:27 -0800 (PST) Received: from localhost ([::1]:52157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9Oc-0003pF-Dm for importer@patchew.org; Tue, 18 Dec 2018 02:02:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92z-0001jf-AQ for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92s-0002u6-UT for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:05 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:44043) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92s-0002qx-JL for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:58 -0500 Received: by mail-pl1-x644.google.com with SMTP id e11so6705029plt.11 for ; Mon, 17 Dec 2018 22:39:57 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ID7FIZGaJQwmRQTNTunXnGYY3XJ2vCL6udRBHw0u68A=; b=ge24hGTBfsdMHDymsPFRP2MnV6V00YW7Q9TJ+IM8aNKC6pC/vLutGU/PAGZqGCC0kc e2gPkPsa/ABL2P6wS/IFDSduHsyNJu94I/DZO3gMasDnvBqtqAPcDKjH0AqkwJ4rJORy r8E1EVRyR+oSrtKEJSUJYHSGgQ/HArql5isQY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ID7FIZGaJQwmRQTNTunXnGYY3XJ2vCL6udRBHw0u68A=; b=Sr4E0MqRbx4RAAJ20pdUF3ygNtEHXZ8HYvcBCZ1+2GlNNfkwcoKEjAs8Yq3dJyIrkP fxe6GudX8Yz2EH7s/22ddBt0FpCrFJZNxXiuCTrA8VnoxAwYpG6FRClgWbVIiRJL2lum Z2KSY8/JKceSD+Pl8xdkFKhsaQwZZCQ87GANyAB0qXcETgMg9Gy//bDgmgSI678px/87 cAEhEWxKAN1qzJsZ5NH1G1zatzhpibSRUa24wJmSQyKLoOvb24y1WmLbyTpiyk6hwD6x Le/5OoQB0iCstbv41ObQoltd4hdUwD//3qzhLtX/xqXSaHFWqGWWGuQ2rgnGAVGw0vpU XH+g== X-Gm-Message-State: AA+aEWYJGdmkitlf0KX5Y2/FvDmXdFfBdpEEX3G4QlWof5VGR9QbJb8b 7cSwKRxIBA+cq3iTNmmIWbYE4QE81aM= X-Google-Smtp-Source: AFSGD/WM/eW8koAlcZ911GjSZfyrcaN6JKimPBFGSviwHsG/SQEsdjBLEgZwGrFTbOh620HYFv4b+Q== X-Received: by 2002:a17:902:765:: with SMTP id 92mr15406336pli.242.1545115196631; Mon, 17 Dec 2018 22:39:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:09 -0800 Message-Id: <20181218063911.2112-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change the representation of VSCR_SAT such that it is easy to set from vector code. Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/cpu.h | 4 +++- target/ppc/int_helper.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a2fe6058b1..26d2e16720 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1063,10 +1063,12 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Vector status and control register */ + /* Vector status and control register, minus VSCR_SAT. */ uint32_t vscr; /* VSX registers (including FP and AVR) */ ppc_vsr_t vsr[64] QEMU_ALIGNED(16); + /* Non-zero if and only if VSCR_SAT should be set. */ + ppc_vsr_t vscr_sat; /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 38aa3e85a6..9dbcbcd87a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -471,18 +471,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh) =20 void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { - env->vscr =3D vscr; + env->vscr =3D vscr & ~(1u << VSCR_SAT); + /* Which bit we set is completely arbitrary, but clear the rest. */ + env->vscr_sat.u64[0] =3D vscr & (1u << VSCR_SAT); + env->vscr_sat.u64[1] =3D 0; set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } =20 uint32_t helper_mfvscr(CPUPPCState *env) { - return env->vscr; + uint32_t sat =3D (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) !=3D 0; + return env->vscr | (sat << VSCR_SAT); } =20 static inline void set_vscr_sat(CPUPPCState *env) { - env->vscr |=3D 1 << VSCR_SAT; + /* The choice of non-zero value is arbitrary. */ + env->vscr_sat.u32[0] =3D 1; } =20 void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545115715875518.3499810808138; Mon, 17 Dec 2018 22:48:35 -0800 (PST) Received: from localhost ([::1]:52067 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9BC-0008W4-4c for importer@patchew.org; Tue, 18 Dec 2018 01:48:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ934-0001sJ-KN for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92v-0002xK-1i for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:10 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34389) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92u-0002tc-MX for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:40:00 -0500 Received: by mail-pf1-x444.google.com with SMTP id h3so7665511pfg.1 for ; Mon, 17 Dec 2018 22:39:59 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5IUcjCqITmxuoIPgM27ilGyi87YBj9+/Mr6P+i3IEFo=; b=YU5E2L8QpC7avK1PCm8kZivQAeBOfDZ+CFKHXU5VPBdt9Iwk9vREEmkoZSjRpNdZuO WsZxwwVNyLMpSXo4XbCOCWeMP+sQE5rmz4al6knCwxD2sKPoY4++8k3GruoE2YySEHF8 BkkYYf4+0wOjM5Wx0Rvo4469UiAPZDtGmXlMw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5IUcjCqITmxuoIPgM27ilGyi87YBj9+/Mr6P+i3IEFo=; b=WkNYx3BTdca7uCrGvV2c+t+IToRj6WBPdXttbglp0eq4jO3TqwSfBbR/xqp2lQPGGs dlA/ocEOaiIOK0xSEiDn73H7nLhhIzJ5OgKgorgX5w8Y1znaH7D5LjAq6ozqzwrHTSqp sMCR5IOyjDfR0wpM5dLjTMBttbpj7wmUWrfrL1GWr4ej1QqZpoM7rEG4lGvD0ITx8VXD iOKDuBLLIAPgRth5gjYo10M+3/H5UWH8G7wL3sIkEy0JafN20fd2QpG/ac0Rb4+Y/IKE gCGUvJx06iflBUkZRCvieLc9w/y7U/kig/zbrgmKIBRHHj5yYJ/+RGobQJzoNTxvygSz iFfA== X-Gm-Message-State: AA+aEWZ06KhM3i6cIxT97XmLsaD//6nDcTDGBQgKBwMXrDZVYZMaDwem OzpmwQNQyj5euPdwA5wGC5JdAZITnaA= X-Google-Smtp-Source: AFSGD/U/npA8a1siBKrxmlsBKbZ6riV9MrVGKCR+1QjUjcDtKiGwcN34LpCN7aVaXBiX1r6o7KumOA== X-Received: by 2002:a63:ee4c:: with SMTP id n12mr14335103pgk.21.1545115197874; Mon, 17 Dec 2018 22:39:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:10 -0800 Message-Id: <20181218063911.2112-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/helper.h | 24 ++++++------ target/ppc/int_helper.c | 18 ++------- target/ppc/translate/vmx-impl.inc.c | 57 +++++++++++++++++++++++------ 3 files changed, 61 insertions(+), 38 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7dbb08b9dd..3daf6bf863 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -219,18 +219,18 @@ DEF_HELPER_2(vprtybq, void, avr, avr) DEF_HELPER_3(vsubcuw, void, avr, avr, avr) DEF_HELPER_2(lvsl, void, avr, tl) DEF_HELPER_2(lvsr, void, avr, tl) -DEF_HELPER_4(vaddsbs, void, env, avr, avr, avr) -DEF_HELPER_4(vaddshs, void, env, avr, avr, avr) -DEF_HELPER_4(vaddsws, void, env, avr, avr, avr) -DEF_HELPER_4(vsubsbs, void, env, avr, avr, avr) -DEF_HELPER_4(vsubshs, void, env, avr, avr, avr) -DEF_HELPER_4(vsubsws, void, env, avr, avr, avr) -DEF_HELPER_4(vaddubs, void, env, avr, avr, avr) -DEF_HELPER_4(vadduhs, void, env, avr, avr, avr) -DEF_HELPER_4(vadduws, void, env, avr, avr, avr) -DEF_HELPER_4(vsububs, void, env, avr, avr, avr) -DEF_HELPER_4(vsubuhs, void, env, avr, avr, avr) -DEF_HELPER_4(vsubuws, void, env, avr, avr, avr) +DEF_HELPER_FLAGS_5(vaddsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vaddshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vaddsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsubsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsubshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsubsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vaddubs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vadduhs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vadduws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsububs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsubuhs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) +DEF_HELPER_FLAGS_5(vsubuws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32) DEF_HELPER_3(vadduqm, void, avr, avr, avr) DEF_HELPER_4(vaddecuq, void, avr, avr, avr, avr) DEF_HELPER_4(vaddeuqm, void, avr, avr, avr, avr) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 9dbcbcd87a..22671c71e5 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -583,27 +583,17 @@ VARITHFPFMA(nmsubfp, float_muladd_negate_result | flo= at_muladd_negate_c); } =20 #define VARITHSAT_DO(name, op, optype, cvt, element) \ - void helper_v##name(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \ - ppc_avr_t *b) \ + void helper_v##name(ppc_avr_t *r, ppc_avr_t *vscr_sat, \ + ppc_avr_t *a, ppc_avr_t *b, uint32_t desc) \ { \ int sat =3D 0; \ int i; \ \ for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - switch (sizeof(r->element[0])) { \ - case 1: \ - VARITHSAT_CASE(optype, op, cvt, element); \ - break; \ - case 2: \ - VARITHSAT_CASE(optype, op, cvt, element); \ - break; \ - case 4: \ - VARITHSAT_CASE(optype, op, cvt, element); \ - break; \ - } \ + VARITHSAT_CASE(optype, op, cvt, element); \ } \ if (sat) { \ - set_vscr_sat(env); \ + vscr_sat->u32[0] =3D 1; \ } \ } #define VARITHSAT_SIGNED(suffix, element, optype, cvt) \ diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 1c0c461241..c6a53a9f63 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -548,22 +548,55 @@ GEN_VXFORM(vslo, 6, 16); GEN_VXFORM(vsro, 6, 17); GEN_VXFORM(vaddcuw, 0, 6); GEN_VXFORM(vsubcuw, 0, 22); -GEN_VXFORM_ENV(vaddubs, 0, 8); + +#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ +static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ + TCGv_vec sat, TCGv_vec a, \ + TCGv_vec b) \ +{ \ + TCGv_vec x =3D tcg_temp_new_vec_matching(t); \ + glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \ + glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \ + tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \ + tcg_gen_or_vec(VECE, sat, sat, x); \ + tcg_temp_free_vec(x); \ +} \ +static void glue(gen_, NAME)(DisasContext *ctx) \ +{ \ + static const GVecGen4 g =3D { \ + .fniv =3D glue(glue(gen_, NAME), _vec), \ + .fno =3D glue(gen_helper_, NAME), \ + .opc =3D glue(glue(INDEX_op_, NORM), _vec), \ + .write_aofs =3D true, \ + .vece =3D VECE, \ + }; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \ + offsetof(CPUPPCState, vscr_sat), \ + avr64_offset(rA(ctx->opcode), true), \ + avr64_offset(rB(ctx->opcode), true), \ + 16, 16, &g); \ +} + +GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8); GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \ vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_ENV(vadduhs, 0, 9); +GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9); GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \ vmul10euq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_ENV(vadduws, 0, 10); -GEN_VXFORM_ENV(vaddsbs, 0, 12); -GEN_VXFORM_ENV(vaddshs, 0, 13); -GEN_VXFORM_ENV(vaddsws, 0, 14); -GEN_VXFORM_ENV(vsububs, 0, 24); -GEN_VXFORM_ENV(vsubuhs, 0, 25); -GEN_VXFORM_ENV(vsubuws, 0, 26); -GEN_VXFORM_ENV(vsubsbs, 0, 28); -GEN_VXFORM_ENV(vsubshs, 0, 29); -GEN_VXFORM_ENV(vsubsws, 0, 30); +GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10); +GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12); +GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13); +GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14); +GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24); +GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25); +GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26); +GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); +GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); +GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); GEN_VXFORM(vadduqm, 0, 4); GEN_VXFORM(vaddcuq, 0, 5); GEN_VXFORM3(vaddeuqm, 30, 0); --=20 2.17.2 From nobody Fri May 3 16:12:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545117155111901.5777113853868; Mon, 17 Dec 2018 23:12:35 -0800 (PST) Received: from localhost ([::1]:52228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ9YM-0002j9-Jk for importer@patchew.org; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/I3d68xBX6LV2DWN7Eockqiaqe8EorKU9+KADTiohnY=; b=D0tSZ6+YGrK9fHWN/ksDKJzgAe6fcHxWCpSCu1iNee+iT4UysXEG7wv0vZUPr2Bu1G eGC265KTD88WkyXE2fZd/ypH3NwYCWLpeGUXQzIqsSSGvlofkipLFsgFiCHtR7lq8OXu hLNAb3os+Uo1DkNzNUVgODIA0evtH1anFPYWs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/I3d68xBX6LV2DWN7Eockqiaqe8EorKU9+KADTiohnY=; b=XgC2RYhDEd1bgzwJKH4ehGOlXNqRewXDXTBgf6rN+c2So3n50aLomOuj4k9Z2wsPw0 18EzeRrwmuem1nU89GojHsHRSTFwM23o5uFl4e2CJksy11cI6TseThkjLoqLAC7z96zL 7Y+po28WDtoc3zWhmvWjM/KDMfvuotXh/WPL/fRuTz31DXDOTpIbdpkpCDhS8LNBF/5j qa/nuhk4M3y3Mnm5KtEX1gJokSNV3SJ1SGQTyPvKtTzb943mWpGCnBU8Bf0ReowJDKgp owtta1DKR4U2RodIKdnnZOLf60RTga54PJimUbfBYYe99YGEZcehLR100QKEb5tUzyAj P6GA== X-Gm-Message-State: AA+aEWaC4VPeGN2qzziqY5MfYBKw+phpVgfIpdJHXcPnOGX0ehzOmQX/ 6WygVCKBgW3Wo8JYvPpokEDG7UG2caw= X-Google-Smtp-Source: AFSGD/UVIN19u+m+XBfOYXLWXtfIdghrW7YReoMRzMKWy+aFX58kuoNYbiMEtb9kmfIjgWUpjt0W4g== X-Received: by 2002:a62:6143:: with SMTP id v64mr15518102pfb.142.1545115199561; Mon, 17 Dec 2018 22:39:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:39:11 -0800 Message-Id: <20181218063911.2112-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 34/34] target/ppc: convert vmin* and vmax* to vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/helper.h | 16 --------------- target/ppc/int_helper.c | 27 ------------------------ target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++--------------- 3 files changed, 16 insertions(+), 59 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3daf6bf863..18910d18a4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -117,22 +117,6 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr) DEF_HELPER_3(vavgsb, void, avr, avr, avr) DEF_HELPER_3(vavgsh, void, avr, avr, avr) DEF_HELPER_3(vavgsw, void, avr, avr, avr) -DEF_HELPER_3(vminsb, void, avr, avr, avr) -DEF_HELPER_3(vminsh, void, avr, avr, avr) -DEF_HELPER_3(vminsw, void, avr, avr, avr) -DEF_HELPER_3(vminsd, void, avr, avr, avr) -DEF_HELPER_3(vmaxsb, void, avr, avr, avr) -DEF_HELPER_3(vmaxsh, void, avr, avr, avr) -DEF_HELPER_3(vmaxsw, void, avr, avr, avr) -DEF_HELPER_3(vmaxsd, void, avr, avr, avr) -DEF_HELPER_3(vminub, void, avr, avr, avr) -DEF_HELPER_3(vminuh, void, avr, avr, avr) -DEF_HELPER_3(vminuw, void, avr, avr, avr) -DEF_HELPER_3(vminud, void, avr, avr, avr) -DEF_HELPER_3(vmaxub, void, avr, avr, avr) -DEF_HELPER_3(vmaxuh, void, avr, avr, avr) -DEF_HELPER_3(vmaxuw, void, avr, avr, avr) -DEF_HELPER_3(vmaxud, void, avr, avr, avr) DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr) DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr) DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 22671c71e5..b9793364fd 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -937,33 +937,6 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r,= ppc_avr_t *a, } } =20 -#define VMINMAX_DO(name, compare, element) \ - void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ - { \ - int i; \ - \ - for (i =3D 0; i < ARRAY_SIZE(r->element); i++) { \ - if (a->element[i] compare b->element[i]) { \ - r->element[i] =3D b->element[i]; \ - } else { \ - r->element[i] =3D a->element[i]; \ - } \ - } \ - } -#define VMINMAX(suffix, element) \ - VMINMAX_DO(min##suffix, >, element) \ - VMINMAX_DO(max##suffix, <, element) -VMINMAX(sb, s8) -VMINMAX(sh, s16) -VMINMAX(sw, s32) -VMINMAX(sd, s64) -VMINMAX(ub, u8) -VMINMAX(uh, u16) -VMINMAX(uw, u32) -VMINMAX(ud, u64) -#undef VMINMAX_DO -#undef VMINMAX - void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t = *c) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index c6a53a9f63..399d18707f 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -412,22 +412,22 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); -GEN_VXFORM(vmaxub, 1, 0); -GEN_VXFORM(vmaxuh, 1, 1); -GEN_VXFORM(vmaxuw, 1, 2); -GEN_VXFORM(vmaxud, 1, 3); -GEN_VXFORM(vmaxsb, 1, 4); -GEN_VXFORM(vmaxsh, 1, 5); -GEN_VXFORM(vmaxsw, 1, 6); -GEN_VXFORM(vmaxsd, 1, 7); -GEN_VXFORM(vminub, 1, 8); -GEN_VXFORM(vminuh, 1, 9); -GEN_VXFORM(vminuw, 1, 10); -GEN_VXFORM(vminud, 1, 11); -GEN_VXFORM(vminsb, 1, 12); -GEN_VXFORM(vminsh, 1, 13); -GEN_VXFORM(vminsw, 1, 14); -GEN_VXFORM(vminsd, 1, 15); +GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0); +GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1); +GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2); +GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3); +GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4); +GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5); +GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6); +GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7); +GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8); +GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9); +GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10); +GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11); +GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12); +GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13); +GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14); +GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15); GEN_VXFORM(vavgub, 1, 16); GEN_VXFORM(vabsdub, 1, 16); GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \ --=20 2.17.2