From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545086418384709.9308317011427; Mon, 17 Dec 2018 14:40:18 -0800 (PST) Received: from localhost ([::1]:50184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Yf-0003AZ-Ao for importer@patchew.org; Mon, 17 Dec 2018 17:40:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Tl-0007UA-2n for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ1Th-0007PR-O3 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:12 -0500 Received: from 12.mo1.mail-out.ovh.net ([87.98.162.229]:55468) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ1Th-0007K1-5v for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:09 -0500 Received: from player718.ha.ovh.net (unknown [10.109.159.154]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 216A114AA58 for ; Mon, 17 Dec 2018 23:35:02 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id CA83CDBCE62; Mon, 17 Dec 2018 22:34:56 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:39 +0100 Message-Id: <20181217223445.28594-2-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2636013157178182630 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.162.229 Subject: [Qemu-devel] [PATCH v9 1/7] target/ppc: fix the PPC_BIT definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Change the PPC_BIT macro to use ULL instead of UL and the PPC_BIT32 and PPC_BIT8 not to use any suffix. This fixes a compile breakage on windows. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ab68abe8a23c..527181c0f09f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -70,9 +70,9 @@ #define PPC_ELF_MACHINE EM_PPC #endif =20 -#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) -#define PPC_BIT32(bit) (0x80000000UL >> (bit)) -#define PPC_BIT8(bit) (0x80UL >> (bit)) +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BIT32(bit) (0x80000000 >> (bit)) +#define PPC_BIT8(bit) (0x80 >> (bit)) #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ PPC_BIT32(bs)) --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545086274501763.3098547914086; Mon, 17 Dec 2018 14:37:54 -0800 (PST) Received: from localhost ([::1]:50169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1WL-0000xn-Eo for importer@patchew.org; Mon, 17 Dec 2018 17:37:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Tm-0007Uq-LI for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ1Ti-0007Py-0T for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:13 -0500 Received: from 7.mo178.mail-out.ovh.net ([46.105.58.91]:45581) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ1Th-0007NM-Kx for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:09 -0500 Received: from player718.ha.ovh.net (unknown [10.109.159.132]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 9D69F430E2 for ; Mon, 17 Dec 2018 23:35:06 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id 06EE9DBCE6A; Mon, 17 Dec 2018 22:35:02 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:40 +0100 Message-Id: <20181217223445.28594-3-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2637420532706216934 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.58.91 Subject: [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" And remove the intermediate MASK_TO_LSH macro which does not add any value. This fixes a compile breakage on windows. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 527181c0f09f..f4ef4f214564 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -78,18 +78,21 @@ PPC_BIT32(bs)) #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(= bs)) =20 +/* + * OPAL PPC bitmask field manipulation, used in XIVE, PHB3 and PHB4 + */ #if HOST_LONG_BITS =3D=3D 32 -# define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1) +# define GETFIELD(m, v) (((v) & (m)) >> ctz32(m)) +# define SETFIELD(m, v, val) \ + (((v) & ~(m)) | ((((typeof(v))(val)) << ctz32(m)) & (m))) #elif HOST_LONG_BITS =3D=3D 64 -# define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1) +# define GETFIELD(m, v) (((v) & (m)) >> ctz64(m)) +# define SETFIELD(m, v, val) \ + (((v) & ~(m)) | ((((typeof(v))(val)) << ctz64(m)) & (m))) #else # error Unknown sizeof long #endif =20 -#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) -#define SETFIELD(m, v, val) \ - (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) - /*************************************************************************= ****/ /* Exception vectors definitions = */ enum { --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154508645028015.883281254424446; Mon, 17 Dec 2018 14:40:50 -0800 (PST) Received: from localhost ([::1]:50191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1ZA-0003dG-FB for importer@patchew.org; Mon, 17 Dec 2018 17:40:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Tq-0007WA-HH for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ1Tm-0007UV-Kg for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:18 -0500 Received: from 9.mo5.mail-out.ovh.net ([178.32.96.204]:39021) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ1Tl-0007SH-35 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:13 -0500 Received: from player718.ha.ovh.net (unknown [10.109.159.152]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id AAB3320B1DF for ; Mon, 17 Dec 2018 23:35:11 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id 9FCB4DBCE7B; Mon, 17 Dec 2018 22:35:06 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:41 +0100 Message-Id: <20181217223445.28594-4-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2638827908335963110 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.96.204 Subject: [Qemu-devel] [PATCH v9 3/7] spapr/xive: fix compilation breakage on windows X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index aaa5865c4080..3ceabe668b16 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -589,12 +589,14 @@ static target_ulong h_int_get_source_info(PowerPCCPU = *cpu, } =20 if (lisn >=3D xive->nr_irqs) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 if (!xive_eas_is_valid(&xive->eat[lisn])) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 @@ -701,13 +703,15 @@ static target_ulong h_int_set_source_config(PowerPCCP= U *cpu, } =20 if (lisn >=3D xive->nr_irqs) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 eas =3D xive->eat[lisn]; if (!xive_eas_is_valid(&eas)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 @@ -724,8 +728,8 @@ static target_ulong h_int_set_source_config(PowerPCCPU = *cpu, } =20 if (spapr_xive_priority_is_reserved(priority)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n", - priority); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld + " is reserved\n", priority); return H_P4; } =20 @@ -793,13 +797,15 @@ static target_ulong h_int_get_source_config(PowerPCCP= U *cpu, } =20 if (lisn >=3D xive->nr_irqs) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 eas =3D xive->eat[lisn]; if (!xive_eas_is_valid(&eas)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 @@ -870,8 +876,8 @@ static target_ulong h_int_get_queue_info(PowerPCCPU *cp= u, */ =20 if (spapr_xive_priority_is_reserved(priority)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n", - priority); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld + " is reserved\n", priority); return H_P3; } =20 @@ -956,8 +962,8 @@ static target_ulong h_int_set_queue_config(PowerPCCPU *= cpu, */ =20 if (spapr_xive_priority_is_reserved(priority)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n", - priority); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld + " is reserved\n", priority); return H_P3; } =20 @@ -1102,8 +1108,8 @@ static target_ulong h_int_get_queue_config(PowerPCCPU= *cpu, */ =20 if (spapr_xive_priority_is_reserved(priority)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n", - priority); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld + " is reserved\n", priority); return H_P3; } =20 @@ -1268,13 +1274,15 @@ static target_ulong h_int_esb(PowerPCCPU *cpu, } =20 if (lisn >=3D xive->nr_irqs) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 eas =3D xive->eat[lisn]; if (!xive_eas_is_valid(&eas)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 @@ -1330,13 +1338,15 @@ static target_ulong h_int_sync(PowerPCCPU *cpu, } =20 if (lisn >=3D xive->nr_irqs) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 eas =3D xive->eat[lisn]; if (!xive_eas_is_valid(&eas)) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn); + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx= "\n", + lisn); return H_P2; } =20 --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545086257687345.28602868244354; Mon, 17 Dec 2018 14:37:37 -0800 (PST) Received: from localhost ([::1]:50167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1W0-0000iF-GO for importer@patchew.org; Mon, 17 Dec 2018 17:37:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58556) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Tu-0007XW-3q for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ1Tq-0007Xj-Sf for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:22 -0500 Received: from 17.mo3.mail-out.ovh.net ([87.98.178.58]:43361) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ1Tq-0007Vi-LS for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:18 -0500 Received: from player718.ha.ovh.net (unknown [10.109.159.132]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 5B8A61ECAB9 for ; Mon, 17 Dec 2018 23:35:16 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id 8FD97DBCE93; Mon, 17 Dec 2018 22:35:11 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:42 +0100 Message-Id: <20181217223445.28594-5-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2640235285583858662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.178.58 Subject: [Qemu-devel] [PATCH v9 4/7] spapr: add an extra OV5 field to the sPAPR IRQ backend X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The interrupt modes supported by the hypervisor are advertised to the guest with new bits definitions of the option vector 5 of property "ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are defined as follow : 0b00 PAPR 2.7 and earlier (Legacy systems) 0b01 XIVE Exploitation mode only 0b10 Either available If the client/guest selects the XIVE interrupt mode, it informs the hypervisor by returning the value 0b01 in byte 23 bits 0-1. A 0b00 value indicates the use of the XICS interrupt mode (Legacy systems). The sPAPR IRQ backend is extended with these definitions and the values are directly used to populate the "ibm,arch-vec-5-platform-support" property. The interrupt mode is advertised under TCG and under KVM. Although a KVM XIVE device is not yet available, the machine can still operate with kernel_irqchip=3Doff. However, we apply a restriction on the CPU which is required to be a POWER9 when a XIVE interrupt controller is in use. Signed-off-by: C=C3=A9dric Le Goater --- Changes since v8 : - reworked XIVE capability in ibm,arch-vec-5-platform-support=20 include/hw/ppc/spapr.h | 6 ++++++ include/hw/ppc/spapr_irq.h | 1 + hw/ppc/spapr.c | 33 ++++++++++++++++++++++++++------- hw/ppc/spapr_irq.c | 3 +++ 4 files changed, 36 insertions(+), 7 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index b1a2515107da..c3a04d5fc13d 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -829,5 +829,11 @@ int spapr_caps_post_migration(sPAPRMachineState *spapr= ); =20 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, Error **errp); +/* + * XIVE definitions + */ +#define SPAPR_OV5_XIVE_LEGACY 0x0 +#define SPAPR_OV5_XIVE_EXPLOIT 0x40 +#define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform = */ =20 #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 63061a009b4c..b34d5a00381b 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -33,6 +33,7 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr); typedef struct sPAPRIrq { uint32_t nr_irqs; uint32_t nr_msis; + uint8_t ov5; =20 void (*init)(sPAPRMachineState *spapr, Error **errp); int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp= ); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7a0ab2da5488..51f254866006 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1095,15 +1095,19 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr,= void *fdt) spapr_dt_rtas_tokens(fdt, rtas); } =20 -/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU featur= es - * that the guest may request and thus the valid values for bytes 24..26 of - * option vector 5: */ -static void spapr_dt_ov5_platform_support(void *fdt, int chosen) +/* + * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU + * and the XIVE features that the guest may request and thus the valid + * values for bytes 23..26 of option vector 5: + */ +static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *= fdt, + int chosen) { PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 char val[2 * 4] =3D { - 23, 0x00, /* Xive mode, filled in below. */ + 23, smc->irq->ov5, /* Xive mode. */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables =3D=3D no, GTSE =3D=3D n= o. */ 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ @@ -1111,7 +1115,11 @@ static void spapr_dt_ov5_platform_support(void *fdt,= int chosen) =20 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, first_ppc_cpu->compat_pvr)) { - /* If we're in a pre POWER9 compat mode then the guest should do h= ash */ + /* + * If we're in a pre POWER9 compat mode then the guest should + * do hash and use the legacy interrupt mode + */ + val[1] =3D 0x00; /* XICS */ val[3] =3D 0x00; /* Hash */ } else if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { @@ -1189,7 +1197,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr,= void *fdt) _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); } =20 - spapr_dt_ov5_platform_support(fdt, chosen); + spapr_dt_ov5_platform_support(spapr, fdt, chosen); =20 g_free(stdout_path); g_free(bootlist); @@ -2659,6 +2667,17 @@ static void spapr_machine_init(MachineState *machine) /* advertise support for ibm,dyamic-memory-v2 */ spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); =20 + /* advertise XIVE on POWER9 machines */ + if (smc->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { + if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3= _00, + 0, spapr->max_compat_pvr)) { + spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); + } else { + error_report("XIVE-only machines require a POWER9 CPU"); + exit(1); + } + } + /* init CPUs */ spapr_init_cpus(spapr); =20 diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index f835ea939cbf..79f06308995b 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -216,6 +216,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *= spapr, int version_id) sPAPRIrq spapr_irq_xics =3D { .nr_irqs =3D SPAPR_IRQ_XICS_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_NR_MSIS, + .ov5 =3D SPAPR_OV5_XIVE_LEGACY, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, @@ -342,6 +343,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spa= pr, Error **errp) sPAPRIrq spapr_irq_xive =3D { .nr_irqs =3D SPAPR_IRQ_XIVE_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XIVE_NR_MSIS, + .ov5 =3D SPAPR_OV5_XIVE_EXPLOIT, =20 .init =3D spapr_irq_init_xive, .claim =3D spapr_irq_claim_xive, @@ -466,6 +468,7 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, b= ool align, Error **errp) sPAPRIrq spapr_irq_xics_legacy =3D { .nr_irqs =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, + .ov5 =3D SPAPR_OV5_XIVE_LEGACY, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545086261632452.6170327803361; Mon, 17 Dec 2018 14:37:41 -0800 (PST) Received: from localhost ([::1]:50168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1W4-0000kx-8k for importer@patchew.org; Mon, 17 Dec 2018 17:37:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ1Ty-0007cz-Sm for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ1Tv-0007bG-Lp for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:26 -0500 Received: from 1.mo6.mail-out.ovh.net ([46.105.56.136]:34031) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZ1Tv-0007Zk-CE for qemu-devel@nongnu.org; Mon, 17 Dec 2018 17:35:23 -0500 Received: from player718.ha.ovh.net (unknown [10.109.143.209]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 1669D19EA68 for ; Mon, 17 Dec 2018 23:35:21 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id 2C817DBCE9B; Mon, 17 Dec 2018 22:35:16 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:43 +0100 Message-Id: <20181217223445.28594-6-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2641642660571089894 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.56.136 Subject: [Qemu-devel] [PATCH v9 5/7] spapr: introduce an 'ic-mode' machine option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This option is used to select the interrupt controller mode (XICS or XIVE) with which the machine will operate. XICS being the default mode for now. When running a machine with the XIVE interrupt mode backend, the guest OS is required to have support for the XIVE exploitation mode. In the case of legacy OS, the mode selected by CAS should be XICS and the OS should fail to boot. However, QEMU could possibly detect it, terminate the boot process and reset to stop in the SLOF firmware. This is not yet handled. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/hw/ppc/spapr.h | 1 + hw/ppc/spapr.c | 50 +++++++++++++++++++++++++++++++++++------ hw/ppc/spapr_cpu_core.c | 3 +-- hw/ppc/spapr_irq.c | 34 +++++++++------------------- 4 files changed, 55 insertions(+), 33 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index c3a04d5fc13d..36033b89d31a 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -181,6 +181,7 @@ struct sPAPRMachineState { int32_t irq_map_nr; unsigned long *irq_map; sPAPRXive *xive; + sPAPRIrq *irq; =20 bool cmd_line_caps[SPAPR_CAP_NUM]; sPAPRCapabilities def, eff, mig; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 51f254866006..aefa0f4ea430 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1104,10 +1104,9 @@ static void spapr_dt_ov5_platform_support(sPAPRMachi= neState *spapr, void *fdt, int chosen) { PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 char val[2 * 4] =3D { - 23, smc->irq->ov5, /* Xive mode. */ + 23, spapr->irq->ov5, /* Xive mode. */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables =3D=3D no, GTSE =3D=3D n= o. */ 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ @@ -1276,7 +1275,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); =20 /* /interrupt controller */ - smc->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, + spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_XICP); =20 ret =3D spapr_populate_memory(spapr, fdt); @@ -1297,7 +1296,8 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, } =20 QLIST_FOREACH(phb, &spapr->phbs, list) { - ret =3D spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, smc->irq->nr= _msis); + ret =3D spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, + spapr->irq->nr_msis); if (ret < 0) { error_report("couldn't setup PCI devices in fdt"); exit(1); @@ -2668,7 +2668,7 @@ static void spapr_machine_init(MachineState *machine) spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); =20 /* advertise XIVE on POWER9 machines */ - if (smc->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { + if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3= _00, 0, spapr->max_compat_pvr)) { spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); @@ -3088,9 +3088,38 @@ static void spapr_set_vsmt(Object *obj, Visitor *v, = const char *name, visit_type_uint32(v, name, (uint32_t *)opaque, errp); } =20 +static char *spapr_get_ic_mode(Object *obj, Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(obj); + + if (spapr->irq =3D=3D &spapr_irq_xics_legacy) { + return g_strdup("legacy"); + } else if (spapr->irq =3D=3D &spapr_irq_xics) { + return g_strdup("xics"); + } else if (spapr->irq =3D=3D &spapr_irq_xive) { + return g_strdup("xive"); + } + g_assert_not_reached(); +} + +static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(obj); + + /* The legacy IRQ backend can not be set */ + if (strcmp(value, "xics") =3D=3D 0) { + spapr->irq =3D &spapr_irq_xics; + } else if (strcmp(value, "xive") =3D=3D 0) { + spapr->irq =3D &spapr_irq_xive; + } else { + error_setg(errp, "Bad value for \"ic-mode\" property"); + } +} + static void spapr_instance_init(Object *obj) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(obj); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 spapr->htab_fd =3D -1; spapr->use_hotplug_event_source =3D true; @@ -3124,6 +3153,14 @@ static void spapr_instance_init(Object *obj) " the host's SMT mode", &error_abort); object_property_add_bool(obj, "vfio-no-msix-emulation", spapr_get_msix_emulation, NULL, NULL); + + /* The machine class defines the default interrupt controller mode */ + spapr->irq =3D smc->irq; + object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, + spapr_set_ic_mode, NULL); + object_property_set_description(obj, "ic-mode", + "Specifies the interrupt controller mode (xics, xive)", + NULL); } =20 static void spapr_machine_finalizefn(Object *obj) @@ -3846,9 +3883,8 @@ static void spapr_pic_print_info(InterruptStatsProvid= er *obj, Monitor *mon) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(obj); - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); =20 - smc->irq->print_info(spapr, mon); + spapr->irq->print_info(spapr, mon); } =20 int spapr_get_vcpu_id(PowerPCCPU *cpu) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1811cd48db90..82666436e9b4 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -214,7 +214,6 @@ static void spapr_cpu_core_unrealize(DeviceState *dev, = Error **errp) static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, sPAPRCPUCore *sc, Error **errp) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); CPUPPCState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); Error *local_err =3D NULL; @@ -233,7 +232,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMa= chineState *spapr, qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); =20 - cpu->intc =3D smc->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err= ); + cpu->intc =3D spapr->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_e= rr); if (local_err) { goto error_unregister; } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 79f06308995b..0999a2b2d69c 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -94,8 +94,7 @@ error: static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - int nr_irqs =3D smc->irq->nr_irqs; + int nr_irqs =3D spapr->irq->nr_irqs; Error *local_err =3D NULL; =20 if (kvm_enabled()) { @@ -234,7 +233,6 @@ sPAPRIrq spapr_irq_xics =3D { static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); uint32_t nr_servers =3D spapr_max_server_number(spapr); DeviceState *dev; int i; @@ -248,7 +246,7 @@ static void spapr_irq_init_xive(sPAPRMachineState *spap= r, Error **errp) } =20 dev =3D qdev_create(NULL, TYPE_SPAPR_XIVE); - qdev_prop_set_uint32(dev, "nr-irqs", smc->irq->nr_irqs); + qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs); /* * 8 XIVE END structures per CPU. One for each available priority */ @@ -361,50 +359,38 @@ sPAPRIrq spapr_irq_xive =3D { */ void spapr_irq_init(sPAPRMachineState *spapr, Error **errp) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - /* Initialize the MSI IRQ allocator. */ if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { - spapr_irq_msi_init(spapr, smc->irq->nr_msis); + spapr_irq_msi_init(spapr, spapr->irq->nr_msis); } =20 - smc->irq->init(spapr, errp); + spapr->irq->init(spapr, errp); } =20 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - - return smc->irq->claim(spapr, irq, lsi, errp); + return spapr->irq->claim(spapr, irq, lsi, errp); } =20 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - - smc->irq->free(spapr, irq, num); + spapr->irq->free(spapr, irq, num); } =20 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - - return smc->irq->qirq(spapr, irq); + return spapr->irq->qirq(spapr, irq); } =20 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - - return smc->irq->post_load(spapr, version_id); + return spapr->irq->post_load(spapr, version_id); } =20 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp) { - sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - - if (smc->irq->reset) { - smc->irq->reset(spapr, errp); + if (spapr->irq->reset) { + spapr->irq->reset(spapr, errp); } } =20 --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545086449242613.7467033163703; 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Mon, 17 Dec 2018 22:35:21 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:44 +0100 Message-Id: <20181217223445.28594-7-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2642768558340344806 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.107.143 Subject: [Qemu-devel] [PATCH v9 6/7] spapr: change default CPU type to POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index aefa0f4ea430..8ea680fcde1e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3967,7 +3967,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) =20 smc->dr_lmb_enabled =3D true; smc->update_dt_enabled =3D true; - mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); mc->has_hotpluggable_cpus =3D true; smc->resize_hpt_default =3D SPAPR_RESIZE_HPT_ENABLED; fwc->get_dev_path =3D spapr_get_fw_dev_path; @@ -4066,6 +4066,7 @@ static void spapr_machine_3_1_class_options(MachineCl= ass *mc) =20 spapr_machine_4_0_class_options(mc); SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1); + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); smc->update_dt_enabled =3D false; } =20 --=20 2.17.2 From nobody Wed May 8 19:03:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Mon, 17 Dec 2018 17:35:32 -0500 Received: from player718.ha.ovh.net (unknown [10.109.160.5]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id D30C3177501 for ; Mon, 17 Dec 2018 23:35:30 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player718.ha.ovh.net (Postfix) with ESMTPSA id B492EDBCEB3; Mon, 17 Dec 2018 22:35:25 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Mon, 17 Dec 2018 23:34:45 +0100 Message-Id: <20181217223445.28594-8-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181217223445.28594-1-clg@kaod.org> References: <20181217223445.28594-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2644175933490760678 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrudeigedgtdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.181.248 Subject: [Qemu-devel] [PATCH v9 7/7] MAINTAINERS: PPC: add a XIVE section X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 83c127f0d6e4..6a648d29a9bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1009,6 +1009,14 @@ F: tests/libqos/*spapr* F: tests/rtas* F: tests/libqos/rtas* =20 +XIVE +M: David Gibson +M: C=C3=A9dric Le Goater +L: qemu-ppc@nongnu.org +S: Supported +F: hw/*/*xive* +F: include/hw/*/*xive* + virtex_ml507 M: Edgar E. Iglesias L: qemu-ppc@nongnu.org --=20 2.17.2