From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077563106749.2715263029852; Mon, 17 Dec 2018 12:12:43 -0800 (PST) Received: from localhost ([::1]:49377 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzFp-0001pc-OT for importer@patchew.org; Mon, 17 Dec 2018 15:12:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40869) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8h-0005P1-N1 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8Q-0001Ul-3N for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:09 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42708 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8N-0001RM-Gg for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BB1B01A471E; Mon, 17 Dec 2018 21:04:55 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id 309FF1A1D0C; Mon, 17 Dec 2018 21:04:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:39 +0100 Message-Id: <20181217200444.14812-2-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU, and LXHU instructions. They were for some reason forgotten in previous commits. The MXU opcode list and decoding engine should be now complete. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 140 +++++++++++++++++++++++++++++----------- 1 file changed, 102 insertions(+), 38 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e9c23a594b..e0c8d8c2f7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1663,12 +1663,21 @@ enum { * =E2=94=82 20..18 * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN - * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU_LXB =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_S32ALNI - * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_S32NOR - * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_S32AND - * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=9C= =E2=94=80 101 =E2=94=80 OPC_MXU_S32OR - * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI =E2=94=9C= =E2=94=80 110 =E2=94=80 OPC_MXU_S32XOR - * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI =E2=94=94= =E2=94=80 111 =E2=94=80 OPC_MXU_S32LUI + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_S32ALNI + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_S32NOR + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32AND + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_S32OR + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_S32XOR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_S32LUI + * =E2=94=82 + * =E2=94=82 7..5 + * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_LXB + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_LXH + * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_LXW + * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_LXBU + * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=94= =E2=94=80 101 =E2=94=80 OPC_MXU_LXHU + * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI + * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL @@ -1678,15 +1687,15 @@ enum { * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_D32SARV * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_Q16SLLV * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV - * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV + * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV * =E2=94=82 * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL + * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU * =E2=94=82 * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ + * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN @@ -1694,7 +1703,7 @@ enum { * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOV * =E2=94=82 * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC + * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL @@ -1750,7 +1759,7 @@ enum { OPC_MXU_S8SDI =3D 0x25, OPC_MXU__POOL15 =3D 0x26, OPC_MXU__POOL16 =3D 0x27, - OPC_MXU_LXB =3D 0x28, + OPC_MXU__POOL17 =3D 0x28, /* not assigned 0x29 */ OPC_MXU_S16LDD =3D 0x2A, OPC_MXU_S16STD =3D 0x2B, @@ -1764,11 +1773,11 @@ enum { OPC_MXU_D32SAR =3D 0x33, OPC_MXU_Q16SLL =3D 0x34, OPC_MXU_Q16SLR =3D 0x35, - OPC_MXU__POOL17 =3D 0x36, + OPC_MXU__POOL18 =3D 0x36, OPC_MXU_Q16SAR =3D 0x37, - OPC_MXU__POOL18 =3D 0x38, - OPC_MXU__POOL19 =3D 0x39, - OPC_MXU__POOL20 =3D 0x3A, + OPC_MXU__POOL19 =3D 0x38, + OPC_MXU__POOL20 =3D 0x39, + OPC_MXU__POOL21 =3D 0x3A, OPC_MXU_Q16SCOP =3D 0x3B, OPC_MXU_Q8MADL =3D 0x3C, OPC_MXU_S32SFL =3D 0x3D, @@ -1940,6 +1949,17 @@ enum { /* * MXU pool 17 */ +enum { + OPC_MXU_LXB =3D 0x00, + OPC_MXU_LXH =3D 0x01, + OPC_MXU_LXW =3D 0x03, + OPC_MXU_LXBU =3D 0x04, + OPC_MXU_LXHU =3D 0x05, +}; + +/* + * MXU pool 18 + */ enum { OPC_MXU_D32SLLV =3D 0x00, OPC_MXU_D32SLRV =3D 0x01, @@ -1950,7 +1970,7 @@ enum { }; =20 /* - * MXU pool 18 + * MXU pool 19 */ enum { OPC_MXU_Q8MUL =3D 0x00, @@ -1958,7 +1978,7 @@ enum { }; =20 /* - * MXU pool 19 + * MXU pool 20 */ enum { OPC_MXU_Q8MOVZ =3D 0x00, @@ -1970,7 +1990,7 @@ enum { }; =20 /* - * MXU pool 20 + * MXU pool 21 */ enum { OPC_MXU_Q8MAC =3D 0x00, @@ -25331,12 +25351,58 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) * Decode MXU pool17 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+---------+-----+-----------+ + * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15| + * +-----------+---------+---------+---+---------+-----+-----------+ + * + */ +static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 6, 2); + + switch (opcode) { + case OPC_MXU_LXW: + /* TODO: Implement emulation of LXW instruction. */ + MIPS_INVAL("OPC_MXU_LXW"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXH: + /* TODO: Implement emulation of LXH instruction. */ + MIPS_INVAL("OPC_MXU_LXH"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXHU: + /* TODO: Implement emulation of LXHU instruction. */ + MIPS_INVAL("OPC_MXU_LXHU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXB: + /* TODO: Implement emulation of LXB instruction. */ + MIPS_INVAL("OPC_MXU_LXB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXBU: + /* TODO: Implement emulation of LXBU instruction. */ + MIPS_INVAL("OPC_MXU_LXBU"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} +/* + * + * Decode MXU pool18 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL17| + * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18| * +-----------+---------+-----+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25380,15 +25446,15 @@ static void decode_opc_mxu__pool17(CPUMIPSState *= env, DisasContext *ctx) =20 /* * - * Decode MXU pool18 + * Decode MXU pool19 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL18| + * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19| * +-----------+---+---+-------+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); =20 @@ -25406,15 +25472,15 @@ static void decode_opc_mxu__pool18(CPUMIPSState *= env, DisasContext *ctx) =20 /* * - * Decode MXU pool19 + * Decode MXU pool20 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL19| + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20| * +-----------+---------+-----+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25458,15 +25524,15 @@ static void decode_opc_mxu__pool19(CPUMIPSState *= env, DisasContext *ctx) =20 /* * - * Decode MXU pool20 + * Decode MXU pool21 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL20| + * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21| * +-----------+---+---+-------+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); =20 @@ -25669,10 +25735,8 @@ static void decode_opc_mxu(CPUMIPSState *env, Disa= sContext *ctx) case OPC_MXU__POOL16: decode_opc_mxu__pool16(env, ctx); break; - case OPC_MXU_LXB: - /* TODO: Implement emulation of LXB instruction. */ - MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); + case OPC_MXU__POOL17: + decode_opc_mxu__pool17(env, ctx); break; case OPC_MXU_S16LDD: /* TODO: Implement emulation of S16LDD instruction. */ @@ -25724,23 +25788,23 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) MIPS_INVAL("OPC_MXU_Q16SLR"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU__POOL17: - decode_opc_mxu__pool17(env, ctx); + case OPC_MXU__POOL18: + decode_opc_mxu__pool18(env, ctx); break; case OPC_MXU_Q16SAR: /* TODO: Implement emulation of Q16SAR instruction. */ MIPS_INVAL("OPC_MXU_Q16SAR"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU__POOL18: - decode_opc_mxu__pool18(env, ctx); - break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); break; case OPC_MXU__POOL20: decode_opc_mxu__pool20(env, ctx); break; + case OPC_MXU__POOL21: + decode_opc_mxu__pool21(env, ctx); + break; case OPC_MXU_Q16SCOP: /* TODO: Implement emulation of Q16SCOP instruction. */ MIPS_INVAL("OPC_MXU_Q16SCOP"); --=20 2.17.1 From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077288046361.1296511478878; Mon, 17 Dec 2018 12:08:08 -0800 (PST) Received: from localhost ([::1]:49349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzBO-0006uw-JT for importer@patchew.org; Mon, 17 Dec 2018 15:08:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40728) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8T-0005De-Ew for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8Q-0001UP-1M for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:05 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42696 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8N-0001Qw-Gd for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 13EC01A472D; Mon, 17 Dec 2018 21:04:56 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id BCBE91A472B; Mon, 17 Dec 2018 21:04:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:40 +0100 Message-Id: <20181217200444.14812-3-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 2/6] target/mips: MXU: Add generic naming for optn2 constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add generic naming involving generig suffixes OPTN0, OPTN1, OPTN2, OPTN3 for four optn2 constants. Suffixes WW, LW, HW, XW are not quite appropriate for some instructions using optn2. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e0c8d8c2f7..74d16ce52e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24238,6 +24238,11 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) #define MXU_EPTN2_SS 3 =20 /* MXU operand getting pattern 'optn2' */ +#define MXU_OPTN2_PTN0 0 +#define MXU_OPTN2_PTN1 1 +#define MXU_OPTN2_PTN2 2 +#define MXU_OPTN2_PTN3 3 +/* alternative naming scheme for 'optn2' */ #define MXU_OPTN2_WW 0 #define MXU_OPTN2_LW 1 #define MXU_OPTN2_HW 2 --=20 2.17.1 From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077262690855.5706400672739; Mon, 17 Dec 2018 12:07:42 -0800 (PST) Received: from localhost ([::1]:49348 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzAz-0006gX-7R for importer@patchew.org; Mon, 17 Dec 2018 15:07:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8T-0005Di-HR for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8Q-0001Ua-3T for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:05 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42701 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8N-0001R8-Gh for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5BCBD1A4720; Mon, 17 Dec 2018 21:04:56 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id 102671A1D0C; Mon, 17 Dec 2018 21:04:56 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:41 +0100 Message-Id: <20181217200444.14812-4-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 3/6] target/mips: MXU: Improve textual description X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Improve textual description of MXU extension. These are mostly comment formatting changes. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 74 ++++++++++++++++++++++++----------------- 1 file changed, 44 insertions(+), 30 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 74d16ce52e..e3a5a73e59 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1399,10 +1399,12 @@ enum { =20 =20 /* - * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D * - * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of M= IPS32 + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MI= PS32 * instructions set. It is designed to fit the needs of signal, graphical = and * video processing applications. MXU instruction set is used in Xburst fa= mily * of microprocessors by Ingenic. @@ -1410,39 +1412,31 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is * the control register. * - * The notation used in MXU assembler mnemonics - * -------------------------------------------- * - * Registers: + * The notation used in MXU assembler mnemonics + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Register operands: * * XRa, XRb, XRc, XRd - MXU registers * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers * - * Subfields: + * Non-register operands: * - * aptn1 - 1-bit accumulate add/subtract pattern - * aptn2 - 2-bit accumulate add/subtract pattern - * eptn2 - 2-bit execute add/subtract pattern - * optn2 - 2-bit operand pattern - * optn3 - 3-bit operand pattern - * sft4 - 4-bit shift amount - * strd2 - 2-bit stride amount + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount * * Prefixes: * - * - * S 32 - * D 16 - * Q 8 - * - * Suffixes: - * - * E - Expand results - * F - Fixed point multiplication - * L - Low part result - * R - Doing rounding - * V - Variable instead of immediate - * W - Combine above L and V + * Level of parallelism: Operand size: + * S - single operation at a time 32 - word + * D - two operations in parallel 16 - half word + * Q - four operations in parallel 8 - byte * * Operations: * @@ -1486,6 +1480,19 @@ enum { * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) * XOR - Logical bitwise 'exclusive or' operation * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * + * The list of MXU instructions grouped by functionality + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * * Load/Store instructions Multiplication instructions * ----------------------- --------------------------- * @@ -1563,6 +1570,13 @@ enum { * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb * * + * The opcode organization of MXU instructions + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning = of + * other bits up to the instruction level is as follows: + * * bits * 05..00 * @@ -1700,7 +1714,7 @@ enum { * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ - * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOV + * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOVN * =E2=94=82 * =E2=94=82 23..22 * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC @@ -1712,10 +1726,10 @@ enum { * =E2=94=94=E2=94=80 111111 =E2=94=80 (overlaps= with SDBBP) * * - * Compiled after: + * Compiled after: * * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it - * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 */ =20 enum { --=20 2.17.1 From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077382304537.399382151752; Mon, 17 Dec 2018 12:09:42 -0800 (PST) Received: from localhost ([::1]:49360 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzCu-0008OE-FV for importer@patchew.org; Mon, 17 Dec 2018 15:09:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8T-0005Dg-G8 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8Q-0001UU-3Y for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:05 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42707 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8N-0001RI-Gf for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A4C231A4738; Mon, 17 Dec 2018 21:04:56 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5C5D91A4733; Mon, 17 Dec 2018 21:04:56 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:42 +0100 Message-Id: <20181217200444.14812-5-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/6] target/mips: MXU: Add handlers for logic instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add translation handlers for logic MXU instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 182 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 170 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e3a5a73e59..c74a831a17 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24649,6 +24649,172 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *= ctx) } =20 =20 +/* + * MXU instruction category: logic + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32NOR S32AND S32OR S32XOR + */ + +/* + * S32NOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'nor' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32NOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 1s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the negation of XR= c */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRa zero register -> just set destination to the negation of XR= b */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to the negation of X= Rb */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32AND XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'and' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32AND(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* one of operands zero register -> just set destination to all 0s= */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32OR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'or' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+--+--+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32OR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to the content of XR= b */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); + } +} + +/* + * S32XOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'xor' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32XOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else { + /* the most general case */ + tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + + /* * Decoding engine for MXU * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -25334,24 +25500,16 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32NOR: - /* TODO: Implement emulation of S32NOR instruction. */ - MIPS_INVAL("OPC_MXU_S32NOR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32NOR(ctx); break; case OPC_MXU_S32AND: - /* TODO: Implement emulation of S32AND instruction. */ - MIPS_INVAL("OPC_MXU_S32AND"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32AND(ctx); break; case OPC_MXU_S32OR: - /* TODO: Implement emulation of S32OR instruction. */ - MIPS_INVAL("OPC_MXU_S32OR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32OR(ctx); break; case OPC_MXU_S32XOR: - /* TODO: Implement emulation of S32XOR instruction. */ - MIPS_INVAL("OPC_MXU_S32XOR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32XOR(ctx); break; case OPC_MXU_S32LUI: /* TODO: Implement emulation of S32LUI instruction. */ --=20 2.17.1 From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077483359878.8255780972012; Mon, 17 Dec 2018 12:11:23 -0800 (PST) Received: from localhost ([::1]:49373 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzEY-0001Cy-2f for importer@patchew.org; Mon, 17 Dec 2018 15:11:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8h-0005P0-Mz for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8R-0001Wn-Sf for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:09 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42730 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8R-0001V3-BI for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:03 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id F3A951A473B; Mon, 17 Dec 2018 21:04:56 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id A127F1A1D0C; Mon, 17 Dec 2018 21:04:56 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:43 +0100 Message-Id: <20181217200444.14812-6-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 5/6] target/mips: MXU: Add handlers for max/min instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add translation handlers for max/min MXU instructions. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 356 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 335 insertions(+), 21 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c74a831a17..339de8c32b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24815,6 +24815,338 @@ static void gen_mxu_S32XOR(DisasContext *ctx) } =20 =20 +/* + * MXU instruction category max/min + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32MAX D16MAX Q8MAX + * S32MIN D16MIN Q8MIN + */ + +/* + * S32MAX XRa, XRb, XRc + * Update XRa with the maximum of signed 32-bit integers contained + * in XRb and XRc. + * + * S32MIN XRa, XRb, XRc + * Update XRa with the minimum of signed 32-bit integers contained + * in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do max/min operation with one operand 0 */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } + } +} + +/* + * D16MAX + * Update XRa with the 16-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * D16MIN + * Update XRa with the 16-bit-wise minimums of signed integers + * contained in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRc =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRa =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRa =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do half-word-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + tcg_gen_shli_i32(t1, t1, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + +/* + * Q8MAX + * Update XRa with the 8-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * Q8MIN + * Update XRa with the 8-bit-wise minimums of signed integers + * contained in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - make it be the first...*/ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do byte-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + + /* the leftmost byte (byte 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* byte 2 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x00FF0000); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + /* byte 1 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FF00); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 24); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + /* byte 0 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x000000FF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 24); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + /* the leftmost byte (byte 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* byte 2 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FF0000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x00FF0000); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8); + tcg_gen_shli_i32(t1, t1, 8); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + /* byte 1 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FF00); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FF00); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + tcg_gen_shli_i32(t1, t1, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 24); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + /* byte 0 */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x000000FF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 24); + tcg_gen_shli_i32(t1, t1, 24); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + + /* * Decoding engine for MXU * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -24836,34 +25168,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *= env, DisasContext *ctx) =20 switch (opcode) { case OPC_MXU_S32MAX: - /* TODO: Implement emulation of S32MAX instruction. */ - MIPS_INVAL("OPC_MXU_S32MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_S32MIN: - /* TODO: Implement emulation of S32MIN instruction. */ - MIPS_INVAL("OPC_MXU_S32MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32MAX_S32MIN(ctx); break; case OPC_MXU_D16MAX: - /* TODO: Implement emulation of D16MAX instruction. */ - MIPS_INVAL("OPC_MXU_D16MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_D16MIN: - /* TODO: Implement emulation of D16MIN instruction. */ - MIPS_INVAL("OPC_MXU_D16MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_D16MAX_D16MIN(ctx); break; case OPC_MXU_Q8MAX: - /* TODO: Implement emulation of Q8MAX instruction. */ - MIPS_INVAL("OPC_MXU_Q8MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_Q8MIN: - /* TODO: Implement emulation of Q8MIN instruction. */ - MIPS_INVAL("OPC_MXU_Q8MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_Q8MAX_Q8MIN(ctx); break; case OPC_MXU_Q8SLT: /* TODO: Implement emulation of Q8SLT instruction. */ --=20 2.17.1 From nobody Wed May 8 02:18:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545077229104430.07056514438193; Mon, 17 Dec 2018 12:07:09 -0800 (PST) Received: from localhost ([::1]:49347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYzAQ-0006Fk-70 for importer@patchew.org; Mon, 17 Dec 2018 15:07:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYz8U-0005EG-D2 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYz8R-0001WZ-QD for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:06 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42731 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gYz8R-0001V6-8a for qemu-devel@nongnu.org; Mon, 17 Dec 2018 15:05:03 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3FF191A1D0C; Mon, 17 Dec 2018 21:04:57 +0100 (CET) Received: from localhost.localdomain (unknown [109.207.46.66]) by mail.rt-rk.com (Postfix) with ESMTPSA id F068E1A472B; Mon, 17 Dec 2018 21:04:56 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, jancraig@amazon.com, smarkovic@wavecomp.com, amarkovic@wavecomp.com Date: Mon, 17 Dec 2018 21:04:44 +0100 Message-Id: <20181217200444.14812-7-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> References: <20181217200444.14812-1-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 6/6] target/mips: MXU: Add handlers for an align instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add translation handler for S32ALNI MXU instruction. Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Markovic --- target/mips/translate.c | 197 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 339de8c32b..96905b78ac 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25147,6 +25147,199 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) } =20 =20 +/* + * MXU instruction category: align + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32ALN S32ALNI + */ + +/* + * S32ALNI XRc, XRb, XRa, optn3 + * Arrange bytes from XRb and XRc according to one of five sets of + * rules determined by optn3, and place the result in XRa. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * + */ +static void gen_mxu_S32ALNI(DisasContext *ctx) +{ + uint32_t optn3, pad, XRc, XRb, XRa; + + optn3 =3D extract32(ctx->opcode, 23, 3); + pad =3D extract32(ctx->opcode, 21, 2); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just appropriatelly shift XRc into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], + 8 * (4 - optn3)); + break; + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + break; + } + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just appropriatelly shift XRb into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3= ); + break; + case MXU_OPTN3_PTN4: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just rotation or moving from any of them = */ + switch (optn3) { + case MXU_OPTN3_PTN0: + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn= 3); + break; + } + } else { + /* the most general case */ + switch (optn3) { + case MXU_OPTN3_PTN0: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* | A B C D | E F G H */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } + break; + case MXU_OPTN3_PTN1: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A | B C D E | F G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); + tcg_gen_shli_i32(t0, t0, 8); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + tcg_gen_shri_i32(t1, t1, 24); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN2: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B | C D E F | G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_shli_i32(t0, t0, 16); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + tcg_gen_shri_i32(t1, t1, 16); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN3: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B C | D E F G | H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); + tcg_gen_shli_i32(t0, t0, 24); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); + tcg_gen_shri_i32(t1, t1, 8); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN4: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* A B C D | E F G H | */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } + break; + } + } +} + + /* * Decoding engine for MXU * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -25809,9 +26002,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32ALNI: - /* TODO: Implement emulation of S32ALNI instruction. */ - MIPS_INVAL("OPC_MXU_S32ALNI"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32ALNI(ctx); break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); --=20 2.17.1