From nobody Mon Apr 29 01:21:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545061022241591.732373093269; Mon, 17 Dec 2018 07:37:02 -0800 (PST) Received: from localhost ([::1]:47295 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYuQe-0006aW-GK for importer@patchew.org; Mon, 17 Dec 2018 10:03:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYuOe-0005Sb-1n for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYuOZ-0006nc-H4 for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:27 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:34359) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gYuOX-0006jZ-Hq for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:22 -0500 Received: by mail-wm1-x341.google.com with SMTP id y185so4937245wmd.1 for ; Mon, 17 Dec 2018 07:01:19 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g67sm17615303wmd.38.2018.12.17.07.01.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 07:01:16 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8006B3E051A; Mon, 17 Dec 2018 15:01:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=27/FB81GdHmJNf6tIRTZBoPUJ2kQ0dZVx7C5EDrLRuk=; b=A5RlX4ZNXTnsf6BskgBSckdqHQPAgc0q7+ADnfSg7Ho8QBel8Sn6k12XaoINpX0F7Z FcspVJz20aCPyaY368Et0TA33ukJtiDTOG9S4EjVYOUSZZ9oEVZdOkoE0dqyVMZRnKvQ BjYMPiIv28y+QNpvZRLReE1Q7oo1HEBdDgBMw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=27/FB81GdHmJNf6tIRTZBoPUJ2kQ0dZVx7C5EDrLRuk=; b=lbX8L9DnszBZONm4NA9J0BaapAG1Ska/PAKLIw+hKG6ySqswvrNfBCThWb64jWpEMb jo1SJnWt7kngRKBnlVcnEDOz9pSMIhN0tuHY3368vMzbPFHgCbPvvEsfNiroBERgCoLk tk/qF2EMTkXvBQAG9avTJMT6AIyMzmGjRmcsh0UlK1hk9jr/jawXaBfXEiivUKYiVKML CEshIkjrUaxVpmxnjyqnHJI/OUA+YVmlVLVxvA70iF/Hkiaf3jraxY96ks6CQ/f/WbzC 3BhzuKrUSBZOxb5RD723FCyBI8d160tDPpdZEd9X2WAhmX48eDmHGoPUJf1JpjciVc7P GfUw== X-Gm-Message-State: AA+aEWYXEQyog1fYvQmIHH935rX6bYPpXUrMqmc2QnW2Ooo36kYC8flp /fVAuCw+hBKb2kelxjLPHa8cmg== X-Google-Smtp-Source: AFSGD/WhfWkOM18agHWQgmL5wFA6FoWV4+6Y81xKokuHeLKm/NntCWGo8BnbTe4H26k8ktAVl+xEdw== X-Received: by 2002:a1c:ae15:: with SMTP id x21mr11737600wme.146.1545058877691; Mon, 17 Dec 2018 07:01:17 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 15:01:13 +0000 Message-Id: <20181217150116.10446-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217150116.10446-1-alex.bennee@linaro.org> References: <20181217150116.10446-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v1 1/4] accel/tcg: export some cputlb functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , cota@braap.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Crosthwaite Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In preparation for having softmmu helpers in their own file rather than generated as part of softmmu-template.h we need to make a couple of helper functions public outside of cputlb. Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/cputlb.c | 21 +++++++++++---------- accel/tcg/cputlb.h | 21 +++++++++++++++++++++ 2 files changed, 32 insertions(+), 10 deletions(-) create mode 100644 accel/tcg/cputlb.h diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af6bd8ccf9..3cae7335d0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "cputlb.h" #include "exec/exec-all.h" #include "exec/memory.h" #include "exec/address-spaces.h" @@ -675,10 +676,10 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofa= il(void *ptr) return ram_addr; } =20 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - target_ulong addr, uintptr_t retaddr, - bool recheck, MMUAccessType access_type, int size) +uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + target_ulong addr, uintptr_t retaddr, + bool recheck, MMUAccessType access_type, int size) { CPUState *cpu =3D ENV_GET_CPU(env); hwaddr mr_offset; @@ -743,10 +744,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, return val; } =20 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - uint64_t val, target_ulong addr, - uintptr_t retaddr, bool recheck, int size) +void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + uint64_t val, target_ulong addr, + uintptr_t retaddr, bool recheck, int size) { CPUState *cpu =3D ENV_GET_CPU(env); hwaddr mr_offset; @@ -809,8 +810,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, =20 /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ -static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, - size_t elt_ofs, target_ulong page) +bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, + size_t elt_ofs, target_ulong page) { size_t vidx; =20 diff --git a/accel/tcg/cputlb.h b/accel/tcg/cputlb.h new file mode 100644 index 0000000000..da09f45b86 --- /dev/null +++ b/accel/tcg/cputlb.h @@ -0,0 +1,21 @@ +/* + * CPU TLB Helpers + */ + +#ifndef CPUTLB_H +#define CPUTBL_H + +uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + target_ulong addr, uintptr_t retaddr, + bool recheck, MMUAccessType access_type, int size); + +void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + uint64_t val, target_ulong addr, + uintptr_t retaddr, bool recheck, int size); + +bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, + size_t elt_ofs, target_ulong page); + +#endif --=20 2.17.1 From nobody Mon Apr 29 01:21:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1545066556095724.7624667117059; Mon, 17 Dec 2018 09:09:16 -0800 (PST) Received: from localhost ([::1]:47313 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYuTK-00005I-9L for importer@patchew.org; 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Mon, 17 Dec 2018 07:01:20 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 15:01:14 +0000 Message-Id: <20181217150116.10446-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217150116.10446-1-alex.bennee@linaro.org> References: <20181217150116.10446-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v1 2/4] accel/tcg: introduce softmmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , cota@braap.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Crosthwaite Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Instead of expanding a series of macros to generate the load/store helpers we move stuff into common functions and rely on the compiler to eliminate the dead code for each variant. Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/softmmu.c | 452 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 accel/tcg/softmmu.c diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c new file mode 100644 index 0000000000..e08730736f --- /dev/null +++ b/accel/tcg/softmmu.c @@ -0,0 +1,452 @@ +/* + * Software MMU support + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cputlb.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "tcg/tcg.h" + +#ifdef TARGET_WORDS_BIGENDIAN +#define NEED_BE_BSWAP 0 +#define NEED_LE_BSWAP 1 +#else +#define NEED_BE_BSWAP 1 +#define NEED_LE_BSWAP 0 +#endif + +/* + * Byte Swap Helper + * + * This should all dead code away depending on the build host and + * access type. + */ + +static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endia= n) +{ + if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { + switch (size) { + case 1: return val; + case 2: return bswap16(val); + case 4: return bswap32(val); + case 8: return bswap64(val); + default: + g_assert_not_reached(); + } + } else { + return val; + } +} + +/* Macro to call the above, with local variables from the use context. */ +#define VICTIM_TLB_HIT(TY, ADDR) \ + victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ + (ADDR) & TARGET_PAGE_MASK) + +/* + * Load Helpers + * + * We support two different access types. SOFTMMU_CODE_ACCESS is + * specifically for reading instructions from system memory. It is + * called by the translation loop and in some helpers where the code + * is disassembled. It shouldn't be called directly by guest code. + */ + +static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr, + size_t size, bool big_endian, + bool code_read) +{ + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D code_read ? entry->addr_code : entry->addr_r= ead; + unsigned a_bits =3D get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + tcg_target_ulong res; + + /* Handle unaligned */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!VICTIM_TLB_HIT(addr_code, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, size, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + } + tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + uint64_t tmp; + + if ((addr & (size - 1)) !=3D 0) { + goto do_unaligned_access; + } + + tmp =3D io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + addr & tlb_addr & TLB_RECHECK, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size); + return handle_bswap(tmp, size, big_endian); + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >=3D TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + tcg_target_ulong r1, r2; + unsigned shift; + do_unaligned_access: + addr1 =3D addr & ~(size - 1); + addr2 =3D addr1 + size; + r1 =3D load_helper(env, addr1, oi, retaddr, size, big_endian, code= _read); + r2 =3D load_helper(env, addr2, oi, retaddr, size, big_endian, code= _read); + shift =3D (addr & (size - 1)) * 8; + + if (big_endian) { + /* Big-endian combine. */ + res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); + } else { + /* Little-endian combine. */ + res =3D (r1 >> shift) | (r2 << ((size * 8) - shift)); + } + return res; + } + + haddr =3D addr + entry->addend; + + switch (size) { + case 1: + res =3D ldub_p((uint8_t *)haddr); + break; + case 2: + if (big_endian) { + res =3D lduw_be_p((uint8_t *)haddr); + } else { + res =3D lduw_le_p((uint8_t *)haddr); + } + break; + case 4: + if (big_endian) { + res =3D ldl_be_p((uint8_t *)haddr); + } else { + res =3D ldl_le_p((uint8_t *)haddr); + } + break; + case 8: + if (big_endian) { + res =3D ldq_be_p((uint8_t *)haddr); + } else { + res =3D ldq_le_p((uint8_t *)haddr); + } + break; + default: + g_assert_not_reached(); + break; + } + + return res; +} + +/* + * For the benefit of TCG generated code, we want to avoid the + * complication of ABI-specific return type promotion and always + * return a value extended to the register size of the host. This is + * tcg_target_long, except in the case of a 32-bit host and 64-bit + * data, and for that we always have uint64_t. + * + * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. + */ + +tcg_target_ulong __attribute__((flatten)) +helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, false); +} + +/* + * Code Access + */ + +uint8_t __attribute__((flatten)) +helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, true); +} + +uint16_t __attribute__((flatten)) +helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, true); +} + +uint16_t __attribute__((flatten)) +helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, true); +} + +uint32_t __attribute__((flatten)) +helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, true); +} + +uint32_t __attribute__((flatten)) +helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, true); +} + +uint64_t __attribute__((flatten)) +helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, true); +} + +uint64_t __attribute__((flatten)) +helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, true); +} + +/* Provide signed versions of the load routines as well. We can of course + avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + +/* + * Store Helpers + */ + +static void store_helper(CPUArchState *env, target_ulong addr, uint64_t va= l, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian) +{ + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D tlb_addr_write(entry); + unsigned a_bits =3D get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); + } + tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + + if ((addr & (size - 1)) !=3D 0) { + goto do_unaligned_access; + } + + io_writex(env, iotlbentry, mmu_idx, + handle_bswap(val, size, big_endian), + addr, retaddr, tlb_addr & TLB_RECHECK, size); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >=3D TARGET_PAGE_SIZE)) { + int i; + uintptr_t index2; + CPUTLBEntry *entry2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* Ensure the second page is in the TLB. Note that the first page + is already guaranteed to be filled, and that the second page + cannot evict the first. */ + page2 =3D (addr + size) & TARGET_PAGE_MASK; + index2 =3D tlb_index(env, mmu_idx, page2); + entry2 =3D tlb_entry(env, mmu_idx, index2); + tlb_addr2 =3D tlb_addr_write(entry2); + if (!tlb_hit_page(tlb_addr2, page2) + && !VICTIM_TLB_HIT(addr_write, page2)) { + tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* XXX: not efficient, but simple. */ + /* This loop must go in the forward direction to avoid issues + with self-modifying code in Windows 64-bit. */ + for (i =3D 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 =3D val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 =3D val >> (i * 8); + } + store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + } + return; + } + + haddr =3D addr + entry->addend; + + switch (size) { + case 1: + stb_p((uint8_t *)haddr, val); + break; + case 2: + if (big_endian) { + stw_be_p((uint8_t *)haddr, val); + } else { + stw_le_p((uint8_t *)haddr, val); + } + break; + case 4: + if (big_endian) { + stl_be_p((uint8_t *)haddr, val); + } else { + stl_le_p((uint8_t *)haddr, val); + } + break; + case 8: + if (big_endian) { + stq_be_p((uint8_t *)haddr, val); + } else { + stq_le_p((uint8_t *)haddr, val); + } + break; + default: + g_assert_not_reached(); + break; + } +} + +void __attribute__((flatten)) +helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 1, false); +} + +void __attribute__((flatten)) +helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, false); +} + +void __attribute__((flatten)) +helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, true); +} + +void __attribute__((flatten)) +helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, false); +} + +void __attribute__((flatten)) +helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, true); +} + +void __attribute__((flatten)) +helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, false); +} + +void __attribute__((flatten)) +helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, true); +} --=20 2.17.1 From nobody Mon Apr 29 01:21:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v1 3/4] accel/tcg: use TLB helpers from softmmu.o X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , cota@braap.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Crosthwaite Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/Makefile.objs | 1 + accel/tcg/cputlb.c | 42 ----------------------------------------- 2 files changed, 1 insertion(+), 42 deletions(-) diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index d381a02f34..6b0b96633d 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,5 +1,6 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o +obj-$(CONFIG_SOFTMMU) +=3D softmmu.o obj-y +=3D tcg-runtime.o tcg-runtime-gvec.o obj-y +=3D cpu-exec.o cpu-exec-common.o translate-all.o obj-y +=3D translator.o diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3cae7335d0..ab07689d0e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -983,28 +983,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, targ= et_ulong addr, cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); } =20 -#ifdef TARGET_WORDS_BIGENDIAN -# define TGT_BE(X) (X) -# define TGT_LE(X) BSWAP(X) -#else -# define TGT_BE(X) BSWAP(X) -# define TGT_LE(X) (X) -#endif - -#define MMUSUFFIX _mmu - -#define DATA_SIZE 1 -#include "softmmu_template.h" - -#define DATA_SIZE 2 -#include "softmmu_template.h" - -#define DATA_SIZE 4 -#include "softmmu_template.h" - -#define DATA_SIZE 8 -#include "softmmu_template.h" - /* First set of helpers allows passing in of OI and RETADDR. This makes them callable from other helpers. */ =20 @@ -1061,23 +1039,3 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, #define DATA_SIZE 8 #include "atomic_template.h" #endif - -/* Code access functions. */ - -#undef MMUSUFFIX -#define MMUSUFFIX _cmmu -#undef GETPC -#define GETPC() ((uintptr_t)0) -#define SOFTMMU_CODE_ACCESS - -#define DATA_SIZE 1 -#include "softmmu_template.h" - -#define DATA_SIZE 2 -#include "softmmu_template.h" - -#define DATA_SIZE 4 -#include "softmmu_template.h" - -#define DATA_SIZE 8 -#include "softmmu_template.h" --=20 2.17.1 From nobody Mon Apr 29 01:21:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15450667857101016.7066671054444; Mon, 17 Dec 2018 09:13:05 -0800 (PST) Received: from localhost ([::1]:47314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYuU1-0000Z1-7h for importer@patchew.org; Mon, 17 Dec 2018 10:07:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gYuOh-0005UQ-Eg for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gYuOd-0006r2-3x for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:31 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45698) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gYuOa-0006kO-HP for qemu-devel@nongnu.org; Mon, 17 Dec 2018 10:01:25 -0500 Received: by mail-wr1-x443.google.com with SMTP id t6so12423366wrr.12 for ; Mon, 17 Dec 2018 07:01:20 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e17sm519918wrs.79.2018.12.17.07.01.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 07:01:18 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id BC4EB3E0561; Mon, 17 Dec 2018 15:01:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1/XdpbRKmlJy8f1cW4lZs50OoWkLjbwpb+QIpBzU2B4=; b=YIznzVP4HP6kNFwP4OQSk8V0f3cog8Kc/M0qsMDjiyLNvbFJZSKzZDedGnQtAQp6DF /wUBKTCFJqaSrTppN+/gHR/KVOtqH9bJhGW7/2YLVFV2OkzfY8wtYwyW6Eir3wG2RSBg GPK6er1v4aWMiWCiYx2UvCS0NFYUw82GpVUR8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1/XdpbRKmlJy8f1cW4lZs50OoWkLjbwpb+QIpBzU2B4=; b=o8b2LmLLUX3Qt4OPtvCOu6yc5k93uiSM438Z8aoQU+nzIIwO/WXG2LO3PqRxjaF6CG rX35Bn0x+TrmIx1wti45lPMSxVimd9zi2dPqVGlTaVOz1k2JWsdFlRXAwMqJBsAfTmEu VDW6M1Bn7fL8OBvjMJWBAH3O7erM2aYW8I2N54R9EESCTR/tzJpEZrEpDuDiMPAxa7Kr nD2hCs9wdU6Bz5RaF14NLw0G1eQRVk1YJzVnSx6GYJd7fIhop+afvbho+ALnMoOEwnu7 TeZfgSnLER9L4Zc/a8XMwvFYwIqR02aOWftGEnpr+a913TpZr76O9x50LIsuigTd5jsF TFlw== X-Gm-Message-State: AA+aEWaMLVPGAp7JJJQG/7oEmANptRHerIGEtn6Pp85zYT8eN5g5VhSL MG2IfpZJRZWyhHL2iBEt/1+bmQ== X-Google-Smtp-Source: AFSGD/UeLmD7M9alXAv+Z4P6pYbjkw4c4kmxqOSy55tCUo1XHuzdNcWJcWHtKSz8zrDVx5jllsH02g== X-Received: by 2002:adf:fe8f:: with SMTP id l15mr10432330wrr.313.1545058878930; Mon, 17 Dec 2018 07:01:18 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 15:01:16 +0000 Message-Id: <20181217150116.10446-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181217150116.10446-1-alex.bennee@linaro.org> References: <20181217150116.10446-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v1 4/4] accel/tcg: remove softmmu_template.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/softmmu_template.h | 446 ----------------------------------- 1 file changed, 446 deletions(-) delete mode 100644 accel/tcg/softmmu_template.h diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h deleted file mode 100644 index b0adea045e..0000000000 --- a/accel/tcg/softmmu_template.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Software MMU support - * - * Generate helpers used by TCG for qemu_ld/st ops and code load - * functions. - * - * Included from target op helpers and exec.c. - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#if DATA_SIZE =3D=3D 8 -#define SUFFIX q -#define LSUFFIX q -#define SDATA_TYPE int64_t -#define DATA_TYPE uint64_t -#elif DATA_SIZE =3D=3D 4 -#define SUFFIX l -#define LSUFFIX l -#define SDATA_TYPE int32_t -#define DATA_TYPE uint32_t -#elif DATA_SIZE =3D=3D 2 -#define SUFFIX w -#define LSUFFIX uw -#define SDATA_TYPE int16_t -#define DATA_TYPE uint16_t -#elif DATA_SIZE =3D=3D 1 -#define SUFFIX b -#define LSUFFIX ub -#define SDATA_TYPE int8_t -#define DATA_TYPE uint8_t -#else -#error unsupported data size -#endif - - -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in t= he - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS= . */ -#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE =3D=3D 8 -# define WORD_TYPE DATA_TYPE -# define USUFFIX SUFFIX -#else -# define WORD_TYPE tcg_target_ulong -# define USUFFIX glue(u, SUFFIX) -# define SSUFFIX glue(s, SUFFIX) -#endif - -#ifdef SOFTMMU_CODE_ACCESS -#define READ_ACCESS_TYPE MMU_INST_FETCH -#define ADDR_READ addr_code -#else -#define READ_ACCESS_TYPE MMU_DATA_LOAD -#define ADDR_READ addr_read -#endif - -#if DATA_SIZE =3D=3D 8 -# define BSWAP(X) bswap64(X) -#elif DATA_SIZE =3D=3D 4 -# define BSWAP(X) bswap32(X) -#elif DATA_SIZE =3D=3D 2 -# define BSWAP(X) bswap16(X) -#else -# define BSWAP(X) (X) -#endif - -#if DATA_SIZE =3D=3D 1 -# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name helper_le_ld_name -# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name helper_le_lds_name -# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name helper_le_st_name -#else -# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX) -# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX) -# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX) -#endif - -#ifndef SOFTMMU_CODE_ACCESS -static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr, - bool recheck, - MMUAccessType access_type) -{ - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, - access_type, DATA_SIZE); -} -#endif - -WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->ADDR_READ; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - tlb_addr =3D entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res =3D TGT_LE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~(DATA_SIZE - 1); - addr2 =3D addr1 + DATA_SIZE; - res1 =3D helper_le_ld_name(env, addr1, oi, retaddr); - res2 =3D helper_le_ld_name(env, addr2, oi, retaddr); - shift =3D (addr & (DATA_SIZE - 1)) * 8; - - /* Little-endian combine. */ - res =3D (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr =3D addr + entry->addend; -#if DATA_SIZE =3D=3D 1 - res =3D glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); -#else - res =3D glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr); -#endif - return res; -} - -#if DATA_SIZE > 1 -WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->ADDR_READ; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - tlb_addr =3D entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res =3D TGT_BE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~(DATA_SIZE - 1); - addr2 =3D addr1 + DATA_SIZE; - res1 =3D helper_be_ld_name(env, addr1, oi, retaddr); - res2 =3D helper_be_ld_name(env, addr2, oi, retaddr); - shift =3D (addr & (DATA_SIZE - 1)) * 8; - - /* Big-endian combine. */ - res =3D (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr =3D addr + entry->addend; - res =3D glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); - return res; -} -#endif /* DATA_SIZE > 1 */ - -#ifndef SOFTMMU_CODE_ACCESS - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ -#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS -WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr); -} - -# if DATA_SIZE > 1 -WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr); -} -# endif -#endif - -static inline void glue(io_write, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - DATA_TYPE val, - target_ulong addr, - uintptr_t retaddr, - bool recheck) -{ - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, - recheck, DATA_SIZE); -} - -void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_addr_write(entry); - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D TGT_LE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, - retaddr, tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i =3D 0; i < DATA_SIZE; ++i) { - /* Little-endian extract. */ - uint8_t val8 =3D val >> (i * 8); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr =3D addr + entry->addend; -#if DATA_SIZE =3D=3D 1 - glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); -#else - glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); -#endif -} - -#if DATA_SIZE > 1 -void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_addr_write(entry); - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D TGT_BE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr, - tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i =3D 0; i < DATA_SIZE; ++i) { - /* Big-endian extract. */ - uint8_t val8 =3D val >> (((DATA_SIZE - 1) * 8) - (i * 8)); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr =3D addr + entry->addend; - glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); -} -#endif /* DATA_SIZE > 1 */ -#endif /* !defined(SOFTMMU_CODE_ACCESS) */ - -#undef READ_ACCESS_TYPE -#undef DATA_TYPE -#undef SUFFIX -#undef LSUFFIX -#undef DATA_SIZE -#undef ADDR_READ -#undef WORD_TYPE -#undef SDATA_TYPE -#undef USUFFIX -#undef SSUFFIX -#undef BSWAP -#undef helper_le_ld_name -#undef helper_be_ld_name -#undef helper_le_lds_name -#undef helper_be_lds_name -#undef helper_le_st_name -#undef helper_be_st_name --=20 2.17.1