From nobody Fri Nov 7 02:26:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544765572470474.7275223082329; Thu, 13 Dec 2018 21:32:52 -0800 (PST) Received: from localhost ([::1]:59471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXg5Z-0002nr-Jt for importer@patchew.org; Fri, 14 Dec 2018 00:32:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxX-0004Ow-6Z for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxV-0005Ky-B1 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:22 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:37360) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxT-0005Jn-Dr for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:19 -0500 Received: by mail-ot1-x341.google.com with SMTP id 40so4318573oth.4 for ; Thu, 13 Dec 2018 21:24:17 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K33mNHUcprNraw8i7ozzfhPn3gQjuDAdVvhTCmVz184=; b=GF6+U6H4wL53TEndcpTqe4cNkqfGntkiwgPNGz9FBpe0eIrYsF0Z5j4KjRl5S+RzXW ufnhaykitY5+V7itU64bvBxjZRLTa1et62Qk/aAiojKSG7bAL2RCe5tDhTkvOTtnl5/w KWW5p3nMNW9pG0Y9PElpAOX3Akbyd6gqsIRww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K33mNHUcprNraw8i7ozzfhPn3gQjuDAdVvhTCmVz184=; b=ivmK8ofrUyhYclQ5/uOBxL2SJE9vCeDOMUqOFt5FpxRBxEsFSEuXzYc0KQ5HEi4vtS 2CENOW5MqpnYwVpAUX3ffK/wsWuEIUZfbDPNU0HHFCyl7uIuCpoV5TfFy9U6suOJC08z CfbGokmExSa6WihMiUawfGd4W+2ysQyV9OegNM4H8hQKQi+5v+ZMpVGsGrcVgb+/c8Wj C2HxGrfvyMPFXYEvL8h65r+3HnvJeebFYlTLv7TKg8IVMzn+MJg8oCK4Wqwzv5BB2zcV 69S2AUudyNtjuy9Qcrym1PPY0F+zDDEGaYXDYvNqgeVpcHWjCXvWP8E/tOxygKykAsCt oarw== X-Gm-Message-State: AA+aEWaEymTRdBQ4XffQz+twykE2xXPblQrnzDCVoQiOO6KQR9w7dHIW tU1FGO7fGWn8Ki8EWA26Jj4eg5NG+sihIw== X-Google-Smtp-Source: AFSGD/X0AcdMW3Zwswgx1GFPboq1CkTRuMbEBgsay0SnBsveuIl57mvyjA0hbx2AM2VTMd1h0NWGsg== X-Received: by 2002:a9d:6c3:: with SMTP id 61mr1224874otx.314.1544765056702; Thu, 13 Dec 2018 21:24:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:46 -0600 Message-Id: <20181214052410.11863-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 03/27] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Fix whitespace, comment grammar. --- target/arm/cpu.h | 4 ++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 26 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cd2519d43e..898243c93e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3032,6 +3032,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE_SHIFT 8 +#define ARM_TBFLAG_PAUTH_ACTIVE_MASK (1ull << ARM_TBFLAG_PAUTH_ACTIVE_SH= IFT) =20 /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -3074,6 +3076,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN(F) \ (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE(F) \ + (((F) & ARM_TBFLAG_PAUTH_ACTIVE_MASK) >> ARM_TBFLAG_PAUTH_ACTIVE_SHIFT) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7..d8a8bb4e9c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 644599b29d..bd0cff5c27 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12981,6 +12981,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { + flags |=3D ARM_TBFLAG_PAUTH_ACTIVE_MASK; + } + } } else { *pc =3D env->regs[15]; flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..7c1cc1ce8e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13407,6 +13407,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->sve_excp_el =3D ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); dc->sve_len =3D (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->pauth_active =3D ARM_TBFLAG_PAUTH_ACTIVE(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.17.2