From nobody Fri Nov 7 02:36:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544766405717891.2775606855779; Thu, 13 Dec 2018 21:46:45 -0800 (PST) Received: from localhost ([::1]:59542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgJA-0006Zp-KB for importer@patchew.org; Fri, 14 Dec 2018 00:46:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004ma-5v for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxo-0005Tx-5X for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:37728) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxk-0005Rp-Hi for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:38 -0500 Received: by mail-oi1-x243.google.com with SMTP id y23so3631596oia.4 for ; Thu, 13 Dec 2018 21:24:34 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/I3auZHuWfajL94gMEfxagNYYa9G7egKOKTHpoNXvLA=; b=OfbMA9W1gZY/aXkoO+cxCt+cox6mMjTkx1uya9f81Dk6XmLXopZ9BM1pYghkGtSbxr tljP8ghxTL7dhOsc8n5FX7ikDkhxXlCiDeDA+hLudsoR7fIyzOuOVMSb46aIHYyP7Nu7 W3/aUXvO2qJpeg/Lk0dnA2YZ2b2T68fJDwfgg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/I3auZHuWfajL94gMEfxagNYYa9G7egKOKTHpoNXvLA=; b=AlU54BByZtwiYiKZvKPeZuRDt2jdEiS6xyKegn9sU6n9r3Pgo4glfhE5eUR/j7Lxjd yODG3y6Cip3mgim9udpNbPOaHzCzbnm1jXgZ/LZxsSvyCVwOFmrz+bzMErdw9xuTYMGv 9uj3gMg93Cf7MpyWUoUOMdxUr+XZoud3YEoNsGWmaeD8vfaY3QXY32RSVqnKNB6eDcYH A6shn6JGrchvbTQXesRxj3J8D5kKv+ourFcSDFC1B/powOAxFRkAXn7yooBFQhpTpBFA lhQRgOY8uccEUfdWMY4G8/5g9vJ8KRr+CIh4KcZdHb6Fs/xno9wvqmtXNvWGrD7V1nTa WYew== X-Gm-Message-State: AA+aEWaZ35ivf6e6Ef3YMukHgYAYBhIOYb+12oJtRPVl7sRNVx5GglMx 9rOo0r6q/GD90qV3TaMwYOLWOyqgO+rHuQ== X-Google-Smtp-Source: AFSGD/WQ7uDcRvhUoT69e+dtrmCy4nq6xe+4E2gV5aJB8APYVXxWrKJ9ZG9ToXjj0saJ+ns9x5lhgg== X-Received: by 2002:aca:43c6:: with SMTP id q189mr1015778oia.340.1544765073735; Thu, 13 Dec 2018 21:24:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:01 -0600 Message-Id: <20181214052410.11863-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v2 18/27] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 35 -------------------------- target/arm/helper.c | 61 ++++++++++++--------------------------------- 2 files changed, 16 insertions(+), 80 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3cc7a069ce..7c7dbc216c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3079,41 +3079,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *e= nv) } #endif =20 -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3422fa5943..bd1b683766 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mm= u_idx) return mmu_idx; } =20 -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13048,9 +13006,22 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, =20 *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); - flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); + +#ifndef CONFIG_USER_ONLY + /* Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + { + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0, p1; + + p0 =3D aa64_va_parameters(env, 0, stage1, false); + p1 =3D aa64_va_parameters(env, -1, stage1, false); + + flags |=3D p0.tbi << ARM_TBFLAG_TBI0_SHIFT; + flags |=3D p1.tbi << ARM_TBFLAG_TBI1_SHIFT; + } +#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.17.2