From nobody Tue Feb 10 09:01:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544765204662784.1317635494572; Thu, 13 Dec 2018 21:26:44 -0800 (PST) Received: from localhost ([::1]:59442 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfzn-0005wo-EU for importer@patchew.org; Fri, 14 Dec 2018 00:26:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55757) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxi-0004TS-G9 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxd-0005PX-Cs for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:32 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]:33295) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxd-0005Ot-7c for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:29 -0500 Received: by mail-oi1-x231.google.com with SMTP id c206so3659730oib.0 for ; Thu, 13 Dec 2018 21:24:29 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6OI+UPAp5FYiypogPPtR+ujzpAY2Etryh32yM0PnSA8=; b=LRBEBCsqDcD2qLOy5opoKDajZWn06n+J86t5+kf8en2QR/Rk3vhRXIPcyMITi5TXCT 4iQP2598Jqdh09sPPp6Y1esir7V/v/iAvxfBMc8TbWaRK+EKwP5xxjBBe/913QRjginq x5ns8v5DwptBibTX4FV4piagkRGJNeVP2y53s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6OI+UPAp5FYiypogPPtR+ujzpAY2Etryh32yM0PnSA8=; b=pC0SJ2eYYgfPxbf/WU1tVarWcqoIJbu77zQng21u3IbjulHPpATnkHMUqy840IG72h dd4JnKw/IVPHebvtOn+qU+LLf266dK0paWe21ANggQqV8/tKEvr8mVk4qoIAHj6dsMFl 6GBzrveE8kkx5HTtd0UN9BmP/aXIWJ5WTMMz1+iYGPSV3kbnuXgvbcF+ge78kgIgSfSL h4qbOAgDigiJLwKk59lfXavxN/r5JnVcI8rboB98Umq8LhcCdg7gHjA4T3pCXmlIe+qf G4Max1WQWZW6uGJeBXgAPrlWB4sf8sa/yqKhci/f62qUPe6b2nDF2Oeg2SvXQOOfO2+Q qRNQ== X-Gm-Message-State: AA+aEWZpZVerSk907N437Zoova+X497C/YZ8yWV3gl72E8QPzcLrTyHi 8XoxLsjToZzfFx0ZCeZ5k2VXHoQfT/xLcg== X-Google-Smtp-Source: AFSGD/WEyu5u0f6g8SHVPKN3OHmAlxQFW3qti6PJH0i65RwXObbCw5AqZsp5qhLfcAtW/XW7tjTsTw== X-Received: by 2002:aca:2803:: with SMTP id 3mr1011816oix.85.1544765068221; Thu, 13 Dec 2018 21:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:56 -0600 Message-Id: <20181214052410.11863-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::231 Subject: [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 62 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e62d248894..c57c89d98a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3146,6 +3146,65 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, s->be_data | size | MO_ALIGN); } =20 +/* PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+------------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * Rs: the source register for the operation + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn =3D extract32(insn, 5, 5); + bool is_wback =3D extract32(insn, 11, 1); + bool use_key_a =3D !extract32(insn, 23, 1); + int offset, memidx; + TCGv_i64 tcg_addr, tcg_rt; + + if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset =3D sextract32(offset << size, 10 + size, 0); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt =3D cpu_reg(s, rt); + memidx =3D get_mem_index(s); + do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, + /* is_signed */ false, /* extend */ false, memidx, + /* iss_valid */ true, /* iss_srt */ rt, + /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3171,6 +3230,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: --=20 2.17.2