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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 13 Dec 2018 14:54:42 +0000
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Subject: [Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD
extension
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From: Richard Henderson <richard.henderson@linaro.org>
The bulk of the work here, beyond base HPD, is defining the
TTBCR2 register. In addition we must check TTBCR.T2E, which
is not present (RES0) for AArch64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 9 +++++++++
target/arm/cpu.c | 4 ++++
target/arm/helper.c | 37 +++++++++++++++++++++++++++++--------
3 files changed, 42 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b8dbdb5e014..11ec2cce767 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1548,6 +1548,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
FIELD(ID_ISAR6, SB, 12, 4)
FIELD(ID_ISAR6, SPECRES, 16, 4)
=20
+FIELD(ID_MMFR4, SPECSEI, 0, 4)
+FIELD(ID_MMFR4, AC2, 4, 4)
+FIELD(ID_MMFR4, XNX, 8, 4)
+FIELD(ID_MMFR4, CNP, 12, 4)
+FIELD(ID_MMFR4, HPDS, 16, 4)
+FIELD(ID_MMFR4, LSM, 20, 4)
+FIELD(ID_MMFR4, CCIDX, 24, 4)
+FIELD(ID_MMFR4, EVT, 28, 4)
+
FIELD(ID_AA64ISAR0, AES, 4, 4)
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 60411f6bfe0..0b185f8d309 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1932,6 +1932,10 @@ static void arm_max_initfn(Object *obj)
t =3D cpu->isar.id_isar6;
t =3D FIELD_DP32(t, ID_ISAR6, DP, 1);
cpu->isar.id_isar6 =3D t;
+
+ t =3D cpu->id_mmfr4;
+ t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+ cpu->id_mmfr4 =3D t;
}
#endif
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 57af6b77a1b..037cece1334 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2728,6 +2728,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu =3D arm_env_get_cpu(env);
+ TCR *tcr =3D raw_ptr(env, ri);
=20
if (arm_feature(env, ARM_FEATURE_LPAE)) {
/* With LPAE the TTBCR could result in a change of ASID
@@ -2735,6 +2736,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
*/
tlb_flush(CPU(cpu));
}
+ /* Preserve the high half of TCR_EL1, set via TTBCR2. */
+ value =3D deposit64(tcr->raw_tcr, 0, 32, value);
vmsa_ttbcr_raw_write(env, ri, value);
}
=20
@@ -2837,6 +2840,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {
REGINFO_SENTINEL
};
=20
+/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
+ * qemu tlbs nor adjusting cached masks.
+ */
+static const ARMCPRegInfo ttbcr2_reginfo =3D {
+ .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .=
opc2 =3D 3,
+ .access =3D PL1_RW, .type =3D ARM_CP_ALIAS,
+ .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
+ offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
+};
+
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5437,6 +5450,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else {
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
+ /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
+ if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) !=3D 0) {
+ define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
+ }
}
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
@@ -9751,12 +9768,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta=
rget_ulong address,
if (tg =3D=3D 2) { /* 16KB pages */
stride =3D 11;
}
- if (aarch64) {
- if (el > 1) {
- hpd =3D extract64(tcr->raw_tcr, 24, 1);
- } else {
- hpd =3D extract64(tcr->raw_tcr, 41, 1);
- }
+ if (aarch64 && el > 1) {
+ hpd =3D extract64(tcr->raw_tcr, 24, 1);
+ } else {
+ hpd =3D extract64(tcr->raw_tcr, 41, 1);
+ }
+ if (!aarch64) {
+ /* For aarch32, hpd0 is not enabled without t2e as well. */
+ hpd &=3D extract64(tcr->raw_tcr, 6, 1);
}
} else {
/* We should only be here if TTBR1 is valid */
@@ -9773,8 +9792,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar=
get_ulong address,
if (tg =3D=3D 1) { /* 16KB pages */
stride =3D 11;
}
- if (aarch64) {
- hpd =3D extract64(tcr->raw_tcr, 42, 1);
+ hpd =3D extract64(tcr->raw_tcr, 42, 1);
+ if (!aarch64) {
+ /* For aarch32, hpd1 is not enabled without t2e as well. */
+ hpd &=3D extract64(tcr->raw_tcr, 6, 1);
}
}
=20
--=20
2.19.2