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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 13 Dec 2018 14:54:41 +0000
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Subject: [Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD
extension
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From: Richard Henderson <richard.henderson@linaro.org>
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
interpret the bits as if ARMv8.1-HPD is present without checking.
We will need a slightly different check for hpd for aarch32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 4 ++++
target/arm/helper.c | 27 ++++++++++++++++++++-------
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0babe483ac2..1a4289c9dda 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj)
t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
cpu->isar.id_aa64pfr0 =3D t;
=20
+ t =3D cpu->isar.id_aa64mmfr1;
+ t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
+ cpu->isar.id_aa64mmfr1 =3D t;
+
/* Replicate the same data to the 32-bit id registers. */
u =3D cpu->isar.id_isar5;
u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1dad277804f..57af6b77a1b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9636,6 +9636,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
bool ttbr1_valid =3D true;
uint64_t descaddrmask;
bool aarch64 =3D arm_el_is_aa64(env, el);
+ bool hpd =3D false;
=20
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -9750,6 +9751,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar=
get_ulong address,
if (tg =3D=3D 2) { /* 16KB pages */
stride =3D 11;
}
+ if (aarch64) {
+ if (el > 1) {
+ hpd =3D extract64(tcr->raw_tcr, 24, 1);
+ } else {
+ hpd =3D extract64(tcr->raw_tcr, 41, 1);
+ }
+ }
} else {
/* We should only be here if TTBR1 is valid */
assert(ttbr1_valid);
@@ -9765,6 +9773,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
if (tg =3D=3D 1) { /* 16KB pages */
stride =3D 11;
}
+ if (aarch64) {
+ hpd =3D extract64(tcr->raw_tcr, 42, 1);
+ }
}
=20
/* Here we should have set up all the parameters for the translation:
@@ -9858,7 +9869,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
descaddr =3D descriptor & descaddrmask;
=20
if ((descriptor & 2) && (level < 3)) {
- /* Table entry. The top five bits are attributes which may
+ /* Table entry. The top five bits are attributes which may
* propagate down through lower levels of the table (and
* which are all arranged so that 0 means "no effect", so
* we can gather them up by ORing in the bits at each level).
@@ -9883,15 +9894,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta=
rget_ulong address,
break;
}
/* Merge in attributes from table descriptors */
- attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
- attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APTable[1] =3D> AP=
[2] */
+ attrs |=3D nstable << 3; /* NS */
+ if (hpd) {
+ /* HPD disables all the table attributes except NSTable. */
+ break;
+ }
+ attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=
=3D 1
* means "force PL1 access only", which means forcing AP[1] to 0.
*/
- if (extract32(tableattrs, 2, 1)) {
- attrs &=3D ~(1 << 4);
- }
- attrs |=3D nstable << 3; /* NS */
+ attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> =
AP[1] */
+ attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A=
P[2] */
break;
}
/* Here descaddr is the final physical address, and attributes
--=20
2.19.2