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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Thu, 13 Dec 2018 14:54:40 +0000
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Subject: [Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write
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From: Richard Henderson <richard.henderson@linaro.org>
Because EL3 has a fixed execution mode, we can properly decide
which of the bits are RES{0,1}.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 2 --
target/arm/helper.c | 14 +++++++++-----
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 20d97b66def..b8dbdb5e014 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint3=
2_t val, uint32_t mask)
#define SCR_FIEN (1U << 21)
#define SCR_ENSCXT (1U << 25)
#define SCR_ATA (1U << 26)
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
=20
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf020364e1d..1dad277804f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const ARMC=
PRegInfo *ri,
=20
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v=
alue)
{
- /* We only mask off bits that are RES0 both for AArch64 and AArch32.
- * For bits that vary between AArch32/64, code needs to check the
- * current execution mode before directly using the feature bit.
- */
- uint32_t valid_mask =3D SCR_AARCH64_MASK | SCR_AARCH32_MASK;
+ /* Begin with base v8.0 state. */
+ uint32_t valid_mask =3D 0x3fff;
+
+ if (arm_el_is_aa64(env, 3)) {
+ value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */
+ valid_mask &=3D ~SCR_NET;
+ } else {
+ valid_mask &=3D ~(SCR_RW | SCR_ST);
+ }
=20
if (!arm_feature(env, ARM_FEATURE_EL2)) {
valid_mask &=3D ~SCR_HCE;
--=20
2.19.2