From nobody Thu Nov 6 23:01:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544702327023980.1917216290182; Thu, 13 Dec 2018 03:58:47 -0800 (PST) Received: from localhost ([::1]:51930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPdd-00025v-5M for importer@patchew.org; Thu, 13 Dec 2018 06:58:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPaB-0007dT-TJ for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXPa6-00007G-JS for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:11 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXPa6-000069-Ba for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:06 -0500 Received: by mail-wm1-x342.google.com with SMTP id c126so2096223wmh.0 for ; Thu, 13 Dec 2018 03:55:06 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v5sm2174274wrn.71.2018.12.13.03.55.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 03:55:04 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 844A43E035F; Thu, 13 Dec 2018 11:55:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2WKnsWU8peQgKSPMtKad0YkSHbbdgmPXuVtkQNcYNoU=; b=dYMnoe7QWiKtyHhcJDjD4B5nuaEo8q04K6tsbW0Z2KdmFfnDgtsK+/cjBcAu3aDwQK 0+b9TlFf1665Qp18UEnru5Jtd0Q9DnH9Vc34IWhBrTtnv47QV5rdAdI6wI9axoRqgEK2 /TJlr7sKLaZkK8NqaLBpTv5yf61ineFqUySkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2WKnsWU8peQgKSPMtKad0YkSHbbdgmPXuVtkQNcYNoU=; b=CRFGWYNloC01+K1/Yt1FUYT4HS63OoHKGvnqLRZQxXYTkZoJ9KnKPZE//+/A9whJcR 6uHCW6CGtuUR0RHwgaTenbSKyUlrMNq6CVb3Zhlml4anhd0MeC4vXQHqOlV8G6tqmvIn sLSu/fIRuIAL+lnSjF+0kwt3fTr8d3CEow1FjKwrtnZnQU1kVghe07Zl3Ogu8cYNxQSf N1IzOBnCxk5DXMmFuPwodmeif5kCp8W4blNTNvKZv6s+uusPXazeBj+UgVoEl4k5sOWP d7FXnjIpcbKmfFefGihdumq02z8qK/U2j05cnh6O95C6Bx1dHf1eM3ME33oDfDqmZsNE e1Uw== X-Gm-Message-State: AA+aEWamL1eXGuYXeJYyp2bVnOPsbIfUVpgspuGLCDt1i3mp0S9Lx0h5 /lTbg6RlJQoYsFmhotoX9JehWtMkxyI= X-Google-Smtp-Source: AFSGD/WZFlL+4ehxbcz+tKSww0ARsVSOxRlYMrcIQa7dwQ6gW/hQhjWzH8gbBYBKS6i8MxnlCftc2w== X-Received: by 2002:a1c:c90b:: with SMTP id f11mr9889949wmb.33.1544702105176; Thu, 13 Dec 2018 03:55:05 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 11:55:02 +0000 Message-Id: <20181213115503.24188-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181213115503.24188-1-alex.bennee@linaro.org> References: <20181213115503.24188-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v1 1/2] target/arm: kvm64 make guest debug AA32 break point aware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Peter Maydell , Omair Javaid , ard.biesheuvel@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) When supported by the hardware we can run AA32 guests or even AA64 EL1 code with AA32 EL0 mode code. Inserting a AA64 break point into AA32 code tends to break things. This is especially acute with gdb as it inserts temporary breakpoints when stepping through code. The heuristic of checking the current mode works but it's not perfect. A user could be placing a break point in code after a mode switch and that will still fail. However there doesn't seem to be a way to force a hbreak by default. According to "set breakpoint auto-hw on": This is the default behavior. When GDB sets a breakpoint, it will try to use the target memory map to decide if software or hardware breakpoint must be used. Reported-by: Ard Biesheuvel Signed-off-by: Alex Benn=C3=A9e Cc: Omair Javaid --- target/arm/kvm64.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0a502091e7..dd564a59b7 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -989,14 +989,20 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 -/* C6.6.29 BRK instruction */ +/* BRK (A64) and BKPT (A32) instructions */ static const uint32_t brk_insn =3D 0xd4200000; +static const uint32_t bkpt_insn =3D 0xe1200070; =20 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) { + CPUARMState *env =3D &ARM_CPU(cs)->env; + int el =3D arm_current_el(env); + bool is_aa64 =3D arm_el_is_aa64(env, el); + const uint32_t *bpi =3D is_aa64 ? &brk_insn : &bkpt_insn; + if (have_guest_debug) { if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 0) || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)bpi, 4, 1)) { return -EINVAL; } return 0; @@ -1012,7 +1018,7 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struc= t kvm_sw_breakpoint *bp) =20 if (have_guest_debug) { if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk !=3D brk_insn || + !(brk =3D=3D brk_insn || brk =3D=3D bkpt_insn) || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 1)) { return -EINVAL; } @@ -1055,6 +1061,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_de= bug_exit_arch *debug_exit) return false; } break; + case EC_AA32_BKPT: case EC_AA64_BKPT: if (kvm_find_sw_breakpoint(cs, env->pc)) { return true; --=20 2.17.1 From nobody Thu Nov 6 23:01:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544702328265726.922602673731; Thu, 13 Dec 2018 03:58:48 -0800 (PST) Received: from localhost ([::1]:51931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPde-00027e-QT for importer@patchew.org; Thu, 13 Dec 2018 06:58:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPaB-0007dV-TW for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXPa8-00008H-6B for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:11 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37550) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXPa7-00007N-6q for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:07 -0500 Received: by mail-wm1-x342.google.com with SMTP id g67so2091756wmd.2 for ; Thu, 13 Dec 2018 03:55:07 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g201sm1255645wme.43.2018.12.13.03.55.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 03:55:04 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 9997A3E0363; Thu, 13 Dec 2018 11:55:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ekMfKo3ZA6YOlbMnD8F8r3Cf15l5nuMJM++IxWwQXiA=; b=LHqBUJQpc+kgMPo+3cbVB81x78OGSqdD07GFNZDNxvZ7yh+Q+J09iCAgETHjVD0bOo RU04Y0n1rRWKMeogvvv+4qIO1bdClFqI1hltmZdVVCnM4hyTDZ0kPkWyMQFb7qXbdm3Q U4bI+B0jgwjZ7aExf7rg7A1uOxdpF+wTBrApw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v1 2/2] target/arm: defer setting up of aarch64 gdb until arm_cpu_realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Peter Maydell , Omair Javaid , ard.biesheuvel@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) If we setup earlier we miss the parsing of the aarch64 state of the CPU. If the user has booted up with: qemu-system-aarch64 -cpu host,aarch64=3Doff -enable-kvm we end up presenting an aarch64 view of the world via the gdbstub and hilarity ensues. Reported-by: Ard Biesheuvel Signed-off-by: Alex Benn=C3=A9e Cc: Omair Javaid Reviewed-by: Richard Henderson --- include/hw/arm/arm.h | 2 ++ target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 20 +++++++++++++++----- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index ffed39252d..f9a7a6e2fb 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -171,4 +171,6 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, ticks. */ extern int system_clock_scale; =20 +void arm_cpu_enable_aarch64_gdbstub(CPUClass *cc); + #endif /* HW_ARM_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..100a72ff81 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -890,9 +890,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. */ +#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + CPUClass *cc =3D CPU_GET_CLASS(cs); no_aa32 =3D !cpu_isar_feature(aa64_aa32, cpu); + arm_cpu_enable_aarch64_gdbstub(cc); } +#endif =20 if (arm_feature(env, ARM_FEATURE_V7VE)) { /* v7 Virtualization Extensions. In real hardware this implies diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..53cde60557 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -434,12 +434,14 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) return g_strdup("aarch64"); } =20 -static void aarch64_cpu_class_init(ObjectClass *oc, void *data) -{ - CPUClass *cc =3D CPU_CLASS(oc); +/* + * We can only setup aarch64 gdb support once we realize the CPU + * object and know what mode it has been booted in. This is called + * from arm_cpu_realize. + */ =20 - cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; - cc->set_pc =3D aarch64_cpu_set_pc; +void arm_cpu_enable_aarch64_gdbstub(CPUClass *cc) +{ cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; @@ -447,6 +449,14 @@ static void aarch64_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_arch_name =3D aarch64_gdb_arch_name; } =20 +static void aarch64_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc =3D CPU_CLASS(oc); + + cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; + cc->set_pc =3D aarch64_cpu_set_pc; +} + static void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { --=20 2.17.1