From nobody Mon Feb 9 17:59:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154467468076543.444262764569885; Wed, 12 Dec 2018 20:18:00 -0800 (PST) Received: from localhost ([::1]:50276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXIRj-0001G0-Mr for importer@patchew.org; Wed, 12 Dec 2018 23:17:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXIC6-0003eu-LE for qemu-devel@nongnu.org; Wed, 12 Dec 2018 23:01:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXIC3-000276-TC for qemu-devel@nongnu.org; Wed, 12 Dec 2018 23:01:50 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:34979) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXIC2-0001vl-Nq; Wed, 12 Dec 2018 23:01:47 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 43Fg3J61kfz9sDr; Thu, 13 Dec 2018 15:01:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1544673692; bh=UATCNSwf0zRf4k4EaLrgA33ptccGmYW2IiQwrNBHcRU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J/B1VE+VmabiSeqIMp7sCXLDrbUCZ0R5xjY6BRtO8y1PWZAHyfJgY0xcXJTXryD73 DkTkAQGfCNdqAfqEgrkd98fWs7mEhXg01g+fyhNVuoK/tbpTlVr7sozST0HZbuuhrG 20+O13FqeeJYlXmUl63IVnKk41yww4SHMDTi/X64= From: David Gibson To: peter.maydell@linaro.org Date: Thu, 13 Dec 2018 15:01:11 +1100 Message-Id: <20181213040126.6768-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213040126.6768-1-david@gibson.dropbear.id.au> References: <20181213040126.6768-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 12/27] e500: simplify IRQ wiring X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, gkurz@kaod.org, qemu-devel@nongnu.org, Greg Kurz , spopovyc@redhat.com, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz The OpenPIC have 5 outputs per connected CPU. The machine init code hence needs a bi-dimensional array (smp_cpu lines, 5 columns) to wire up the irqs between the PIC and the CPUs. The current code first allocates an array of smp_cpus pointers to qemu_irq type, then it allocates another array of smp_cpus * 5 qemu_irq and fills the first array with pointers to each line of the second array. This is rather convoluted. Simplify the logic by introducing a structured type that describes all the OpenPIC outputs for a single CPU, ie, fixed size of 5 qemu_irq, and only allocate a smp_cpu sized array of those. This also allows to use g_new(T, n) instead of g_malloc(sizeof(T) * n) as recommended in HACKING. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- hw/ppc/e500.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e6747fce28..b20fea0dfc 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -685,7 +685,7 @@ static void ppce500_cpu_reset(void *opaque) } =20 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, - qemu_irq **irqs) + IrqLines *irqs) { DeviceState *dev; SysBusDevice *s; @@ -705,7 +705,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500Machi= neState *pms, k =3D 0; for (i =3D 0; i < smp_cpus; i++) { for (j =3D 0; j < OPENPIC_OUTPUT_NB; j++) { - sysbus_connect_irq(s, k++, irqs[i][j]); + sysbus_connect_irq(s, k++, irqs[i].irq[j]); } } =20 @@ -713,7 +713,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500Machi= neState *pms, } =20 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, - qemu_irq **irqs, Error **errp) + IrqLines *irqs, Error **errp) { Error *err =3D NULL; DeviceState *dev; @@ -742,7 +742,7 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500= MachineClass *pmc, =20 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, MemoryRegion *ccsr, - qemu_irq **irqs) + IrqLines *irqs) { MachineState *machine =3D MACHINE(pms); const PPCE500MachineClass *pmc =3D PPCE500_MACHINE_GET_CLASS(pms); @@ -806,15 +806,14 @@ void ppce500_init(MachineState *machine) /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and * 4 respectively */ unsigned int pci_irq_nrs[PCI_NUM_PINS] =3D {1, 2, 3, 4}; - qemu_irq **irqs; + IrqLines *irqs; DeviceState *dev, *mpicdev; CPUPPCState *firstenv =3D NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; PPCE500CCSRState *ccsr; =20 - irqs =3D g_malloc0(smp_cpus * sizeof(qemu_irq *)); - irqs[0] =3D g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); + irqs =3D g_new0(IrqLines, smp_cpus); for (i =3D 0; i < smp_cpus; i++) { PowerPCCPU *cpu; CPUState *cs; @@ -834,10 +833,9 @@ void ppce500_init(MachineState *machine) firstenv =3D env; } =20 - irqs[i] =3D irqs[0] + (i * OPENPIC_OUTPUT_NB); input =3D (qemu_irq *)env->irq_inputs; - irqs[i][OPENPIC_OUTPUT_INT] =3D input[PPCE500_INPUT_INT]; - irqs[i][OPENPIC_OUTPUT_CINT] =3D input[PPCE500_INPUT_CINT]; + irqs[i].irq[OPENPIC_OUTPUT_INT] =3D input[PPCE500_INPUT_INT]; + irqs[i].irq[OPENPIC_OUTPUT_CINT] =3D input[PPCE500_INPUT_CINT]; env->spr_cb[SPR_BOOKE_PIR].default_value =3D cs->cpu_index =3D i; env->mpic_iack =3D pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + = 0xa0; =20 --=20 2.19.2