From nobody Fri May 3 12:01:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544464663183843.182600457933; Mon, 10 Dec 2018 09:57:43 -0800 (PST) Received: from localhost ([::1]:34097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPo4-00082l-W7 for importer@patchew.org; Mon, 10 Dec 2018 12:57:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPnG-0007iw-VG for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:56:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWPnF-0000rW-Ak for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:56:34 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gWPnF-0000p7-2Z for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:56:33 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gWPnC-0000U1-JG; Mon, 10 Dec 2018 17:56:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 17:56:30 +0000 Message-Id: <20181210175630.30643-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC] target/microblaze: Switch to transaction_failed hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Switch the microblaze target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. For microblaze this makes no difference because none of the target CPU code needs to make loads or stores by physical address. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- A straightforward conversion, but tagged RFC because I don't have any microblaze test images and have tested only with "make check". target/microblaze/cpu.h | 7 ++++--- target/microblaze/cpu.c | 2 +- target/microblaze/op_helper.c | 20 ++++++++++---------- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3c4e0ba80ac..03ca91007d5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -388,9 +388,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) -void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size); +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #endif =20 #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b546a2c18e..49876b19b38 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -297,7 +297,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D mb_cpu_handle_mmu_fault; #else - cc->do_unassigned_access =3D mb_cpu_unassigned_access; + cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; #endif dc->vmsd =3D &vmstate_mb_cpu; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 7cdbbcccaef..d25d3b626c8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -486,18 +486,18 @@ void helper_mmu_write(CPUMBState *env, uint32_t ext, = uint32_t rn, uint32_t v) mmu_write(env, ext, rn, v); } =20 -void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size) +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { MicroBlazeCPU *cpu; CPUMBState *env; - - qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=3D%d exe= =3D%d\n", - addr, is_write ? 1 : 0, is_exec ? 1 : 0); - if (cs =3D=3D NULL) { - return; - } + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx + " physaddr 0x" TARGET_FMT_plx "size %d access type %s\n", + addr, physaddr, size, + access_type =3D=3D MMU_INST_FETCH ? "INST_FETCH" : + (access_type =3D=3D MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_= STORE")); cpu =3D MICROBLAZE_CPU(cs); env =3D &cpu->env; if (!(env->sregs[SR_MSR] & MSR_EE)) { @@ -505,7 +505,7 @@ void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, } =20 env->sregs[SR_EAR] =3D addr; - if (is_exec) { + if (access_type =3D=3D MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] =3D ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); --=20 2.19.2