From nobody Mon Apr 29 05:29:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544463588461471.1124143288423; Mon, 10 Dec 2018 09:39:48 -0800 (PST) Received: from localhost ([::1]:33993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPX1-0004wW-9s for importer@patchew.org; Mon, 10 Dec 2018 12:39:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPRN-00080l-3f for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWPRK-0004Pb-Ln for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:56 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53448) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gWPRK-0004Oe-Cg for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gWPRH-0000QH-3P; Mon, 10 Dec 2018 17:33:51 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 17:33:50 +0000 Message-Id: <20181210173350.13073-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC] hw/alpha/typhoon: Stop calling cpu_unassigned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The typhoon MemoryRegionOps callbacks directly call cpu_unassigned_access(), presumably as the old-fashioned way to provoke a CPU exception. This won't work since commit 6ad4d7eed05a1e235 when we switched Alpha over to the transaction_failed hook API, because now cpu_unassigned_access() is a no-op for Alpha. Make the MemoryRegionOps callbacks use the read_with_attrs and write_with_attrs hooks, so they can signal a failure that should cause a CPU exception by returning MEMTX_ERROR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Richard Henderson --- RFC because untested, since I don't have an alpha test image. hw/alpha/typhoon.c | 47 ++++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 8004afe45b3..cbacea5fbd8 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) } } =20 -static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult cchip_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { CPUState *cpu =3D current_cpu; TyphoonState *s =3D opaque; @@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } =20 - return ret; + *data =3D ret; + return MEMTX_OK; } =20 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) @@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, u= nsigned size) return 0; } =20 -static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t ret =3D 0; @@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } =20 - return ret; + *data =3D ret; + return MEMTX_OK; } =20 -static void cchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult cchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t oldval, newval; @@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } =20 static void dchip_write(void *opaque, hwaddr addr, @@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr, /* Skip this. It's all related to DRAM timing and setup. */ } =20 -static void pchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult pchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s =3D opaque; uint64_t oldval; @@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } =20 static const MemoryRegionOps cchip_ops =3D { - .read =3D cchip_read, - .write =3D cchip_write, + .read_with_attrs =3D cchip_read, + .write_with_attrs =3D cchip_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 8, @@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops =3D { }; =20 static const MemoryRegionOps pchip_ops =3D { - .read =3D pchip_read, - .write =3D pchip_write, + .read_with_attrs =3D pchip_read, + .write_with_attrs =3D pchip_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 8, --=20 2.19.2