From nobody Sun Feb 8 07:07:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544463600918409.39633095600095; Mon, 10 Dec 2018 09:40:00 -0800 (PST) Received: from localhost ([::1]:33996 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPXD-00057R-BW for importer@patchew.org; Mon, 10 Dec 2018 12:39:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPPU-0006NB-2u for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:32:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWPPS-0003cU-5u for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:31:59 -0500 Received: from mx1.redhat.com ([209.132.183.28]:29013) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gWPPS-0003cC-0K for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:31:58 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6CEA888E50; Mon, 10 Dec 2018 17:31:56 +0000 (UTC) Received: from dgilbert-t530.redhat.com (unknown [10.36.118.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0FBDC1001F5E; Mon, 10 Dec 2018 17:31:53 +0000 (UTC) From: "Dr. David Alan Gilbert (git)" To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 17:31:45 +0000 Message-Id: <20181210173151.16629-2-dgilbert@redhat.com> In-Reply-To: <20181210173151.16629-1-dgilbert@redhat.com> References: <20181210173151.16629-1-dgilbert@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Mon, 10 Dec 2018 17:31:56 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH 1/7] virtio: Add shared memory capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sweil@redhat.com, swhiteho@redhat.com, stefanha@redhat.com, vgoyal@redhat.com, miklos@szeredi.hu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: "Dr. David Alan Gilbert" Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' and the data structure 'virtio_pci_shm_cap' to go with it. They allow defining shared memory regions with sizes and offsets of 2^32 and more. Multiple instances of the capability are allowed and distinguished by a device-specific 'id'. Signed-off-by: Dr. David Alan Gilbert --- hw/virtio/virtio-pci.c | 20 ++++++++++++++++++++ include/standard-headers/linux/virtio_pci.h | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a954799267..1e737531b5 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1163,6 +1163,26 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *pr= oxy, return offset; } =20 +static int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, + uint64_t offset, uint64_t length, + uint8_t id) +{ + struct virtio_pci_shm_cap cap =3D { + .cap.cap_len =3D sizeof cap, + .cap.cfg_type =3D VIRTIO_PCI_CAP_SHARED_MEMORY_CFG, + }; + uint32_t mask32 =3D ~0; + + cap.cap.bar =3D bar; + cap.cap.length =3D cpu_to_le32(length & mask32); + cap.length_hi =3D cpu_to_le32((length >> 32) & mask32); + cap.cap.offset =3D cpu_to_le32(offset & mask32); + cap.offset_hi =3D cpu_to_le32((offset >> 32) & mask32); + cap.id =3D id; + return virtio_pci_add_mem_cap(proxy, &cap.cap); +} + static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr, unsigned size) { diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard= -headers/linux/virtio_pci.h index 9262acd130..745d7a1942 100644 --- a/include/standard-headers/linux/virtio_pci.h +++ b/include/standard-headers/linux/virtio_pci.h @@ -113,6 +113,8 @@ #define VIRTIO_PCI_CAP_DEVICE_CFG 4 /* PCI configuration access */ #define VIRTIO_PCI_CAP_PCI_CFG 5 +/* Additional shared memory capability */ +#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 =20 /* This is the PCI capability header: */ struct virtio_pci_cap { @@ -163,6 +165,13 @@ struct virtio_pci_cfg_cap { uint8_t pci_cfg_data[4]; /* Data for BAR access. */ }; =20 +struct virtio_pci_shm_cap { + struct virtio_pci_cap cap; + uint32_t offset_hi; /* Most sig 32 bits of offset */ + uint32_t length_hi; /* Most sig 32 bits of length */ + uint8_t id; /* To distinguish shm chunks */ +}; + /* Macro versions of offsets for the Old Timers! */ #define VIRTIO_PCI_CAP_VNDR 0 #define VIRTIO_PCI_CAP_NEXT 1 --=20 2.19.2