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[88.21.202.172]) by smtp.gmail.com with ESMTPSA id r76-v6sm10574641wmb.21.2018.12.09.11.37.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 09 Dec 2018 11:37:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=n3VUfFZCypUWEo5ApDoz2AmNCqEt2SRisr211rzgw6Y=; b=kkwGNBrqSa8m48rPo5pXsGt2l2fuy4XUZm7P0AtvoaB3ngES+sV1reVqG7GCR8n4ca AKgffgQKVy3gpI3zFhRixz76qH+j30jJIQxyYh7LXghjIK8YVFGlZFj/d7ZIrJlzEQH6 HDl7ILBkdU028i2d05mZ/hYMhHeKyXXesBaMy+rAAPLwT9niGNmuhHK4ttmqJEz69yyE I92YuHUDEuiOH8PgbpcblTBWyhipvduUBBNe3oN7wMgrUT0pBLRCdphOnr1zYuA/OaeF leLGq4MvJ4Wok4NY+7jQGfTZHp2BZ7k9SVaPTx61UBsFJb/TWVrBdV9FqvN3nwGssZLz 225w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=n3VUfFZCypUWEo5ApDoz2AmNCqEt2SRisr211rzgw6Y=; b=Piu2GNpJ8LHqTwdaebmyqfo2elpjTz1AFaGkpchMxEXM7XezG6LRBsmiz07+r0bsJa T4l2mc3gi1OlcVTPl6ZTCy+iD31vCAFbj04T8bcUTrEiTsXAjOGWyXYeF2I5hgTbVrOV PtLqASucuRsgETVjH9us7P4hikWiQVpX+Sio6CIpdaAlyIO0Isva3PvefOD2NjuyYp+A 4ksebs55r26+16nuyjc2MI1gu2NzOswCzuR/FclQlRqOxrPbKwtL34qZfwszKTOO4VS+ oU05c9h22yJqYsne581NZYSKTUu+gJg8jU616R+NDe0aHiUdB91KQAARdGL1697pA3cP mdOg== X-Gm-Message-State: AA+aEWZyAiM6fRtd2mjeg78Sk2g0vx9oLTFX+fwBpkJCsaNcDrDH4qI+ nCS1cCX7oQ6wP0a+PEwelhY= X-Google-Smtp-Source: AFSGD/UFLFg3xIxVqDeQbvv/3J5gnS6yZgsK7CMVtEROiZ2uA+SYoS/mnf7nUm85ZG7EUBp5ewVNRA== X-Received: by 2002:a1c:68d7:: with SMTP id d206mr7968464wmc.43.1544384273193; Sun, 09 Dec 2018 11:37:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Beniamino Galvani , Peter Maydell , Charlie Smurthwaite Date: Sun, 9 Dec 2018 20:37:42 +0100 Message-Id: <20181209193742.7582-1-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH] hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply defi= ne the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite Tested-by: Charlie Smurthwaite Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- There is an unmerged Linux patch where this SRAM seems used by the EMAC: https://patchwork.kernel.org/patch/6515451/ hw/arm/allwinner-a10.c | 5 +++++ include/hw/arm/allwinner-a10.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875cdb5..0bb0aa3b64 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/devices.h" #include "hw/arm/allwinner-a10.h" +#include "hw/misc/unimp.h" =20 static void aw_a10_init(Object *obj) { @@ -85,6 +86,10 @@ static void aw_a10_realize(DeviceState *dev, Error **err= p) sysbus_connect_irq(sysbusdev, 4, s->irq[67]); sysbus_connect_irq(sysbusdev, 5, s->irq[68]); =20 + memory_region_init_ram(&s->sram_a, NULL, "sram A", 48 * KiB, &error_fa= tal); + memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_= a); + create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); + /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index efb8fc8123..389e128d0f 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -35,6 +35,7 @@ typedef struct AwA10State { AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; + MemoryRegion sram_a; } AwA10State; =20 #define ALLWINNER_H_ --=20 2.17.2