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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U+yA0gpIKvjd3st8336MWjcYGoymhOrHRSCnKqU8W1M=; b=AIZY0ejoG1yXxsUlm3vBzEUoACwtyVyxXKTsJEN9MKhIyIBGVxmTCCD3Y1d6FwKRa8 ZG+PA2qipXo5XdDy7yPLJ7NGxm3AMcQ/5b+o13rgwtd0g5jHYGFv5sii6w9JCBc6UlFN usS6jm9wEJIsdeELqrhdL5BfkOWvWpSa26TdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U+yA0gpIKvjd3st8336MWjcYGoymhOrHRSCnKqU8W1M=; b=ljYoN0Y8JA6NJa6xLp2VdpKAzF0gbBb1qChmxbr046qJeOve7nS9fj0030F4RON3iJ qwOOKkACXRJoX3ruROa7Zws32zWMo4qYBnp2eXT2HtX5k11ZQSoZ43AWZ1OfQ3vLj9s7 ZVMyxQwh5P09HoJa+vC2V91xMAULXLjsx8tt5cO2L+LL7P1WPNiOlgdTLCqU6wWRhsNg p7Netzmbmeo4wCkBfZfKW0hsaazEvQJe6/JV4EYmbc+hfAufLXq9Ih/PAOMrAnpvjoD8 Xs2uxeMz57VecvfScIWxE9UJDKLf3rG1MQNqIiKWTIkrSPHq1u8XUnYpP5su/3o63C+k 31vA== X-Gm-Message-State: AA+aEWYutx+HOrKkFAiw8lhS1ka2HMHBHeo/RMmViQrs4SzKe7tgYFpO 101p1wbYlshmJ0XvIMINQMK5hcgdpiY= X-Google-Smtp-Source: AFSGD/UFIL0NrZMm0R8FsFkwBi5tHFNKFI6QyKZQh7R3Ol03ARAwnTeO9O7i+O5E+7miBhIWLU/HzQ== X-Received: by 2002:a9d:3e4a:: with SMTP id h10mr1179313otg.74.1544179033691; Fri, 07 Dec 2018 02:37:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:31 -0600 Message-Id: <20181207103631.28193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH 26/26] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can perform this with fewer operations. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++++++++++++++------------------------ 1 file changed, 23 insertions(+), 42 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 99e1405dff..15080cbb3c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 @@ -276,56 +276,37 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + bool tbi0 =3D s->tbi0, tbi1 =3D s->tbi1; =20 if (s->current_el <=3D 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (s->tbi0 && s->tbi1) { - TCGv_i64 tmp_reg =3D tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval =3D tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + if (tbi0 || tbi1) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); =20 - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi0 !=3D tbi1) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); =20 - if (s->tbi0) { - /* tbi0=3D=3D1, tbi1=3D=3D0, so 0-fill upper byte if bit 5= 5 =3D 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); - } else { - /* tbi0=3D=3D0, tbi1=3D=3D1, so 1-fill upper byte if bit 5= 5 =3D 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi0 ? TCG_COND_GE : TCG_COND_LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ - if (s->tbi0) { + } else { + if (tbi0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } =20 typedef struct DisasCompare64 { --=20 2.17.2