From nobody Tue Feb 10 19:17:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544173716982946.2460263954459; Fri, 7 Dec 2018 01:08:36 -0800 (PST) Received: from localhost ([::1]:44867 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVC7f-0005nb-A1 for importer@patchew.org; Fri, 07 Dec 2018 04:08:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVBwu-0002Z3-Bb for qemu-devel@nongnu.org; Fri, 07 Dec 2018 03:57:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVBwq-0000Qa-Ab for qemu-devel@nongnu.org; Fri, 07 Dec 2018 03:57:28 -0500 Received: from chuckie.co.uk ([82.165.15.123]:38302 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gVBwq-0000BE-1X; Fri, 07 Dec 2018 03:57:24 -0500 Received: from host86-191-82-245.range86-191.btcentralplus.com ([86.191.82.245] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1gVBwq-00034L-7q; Fri, 07 Dec 2018 08:57:25 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Fri, 7 Dec 2018 08:56:34 +0000 Message-Id: <20181207085635.4291-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181207085635.4291-1-mark.cave-ayland@ilande.co.uk> References: <20181207085635.4291-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.191.82.245 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [RFC PATCH 5/6] target/ppc: convert VMX logical instructions to use vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/translate.c | 1 + target/ppc/translate/vmx-impl.inc.c | 64 ++++++++++++++++++++++-----------= ---- 2 files changed, 40 insertions(+), 25 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5923c688cd..92d023864e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -24,6 +24,7 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" =20 diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 30046c6e31..b252fce71b 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -14,6 +14,11 @@ static inline TCGv_ptr gen_avr_ptr(int reg) return r; } =20 +static inline long avr64_offset(int reg, bool high) +{ + return offsetof(CPUPPCState, avr[reg].u64[(high ? 0 : 1)]); +} + #define GEN_VR_LDX(name, opc2, opc3) = \ static void glue(gen_, name)(DisasContext *ctx) = \ { = \ @@ -257,41 +262,50 @@ GEN_VX_VMUL10(vmul10euq, 1, 0); GEN_VX_VMUL10(vmul10cuq, 0, 1); GEN_VX_VMUL10(vmul10ecuq, 1, 1); =20 -/* Logical operations */ -#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) = \ +#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv_i64 t0 =3D tcg_temp_new_i64(); \ - TCGv_i64 t1 =3D tcg_temp_new_i64(); \ - TCGv_i64 avr =3D tcg_temp_new_i64(); \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ \ + tcg_op(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rA(ctx->opcode), true), \ + avr64_offset(rB(ctx->opcode), true), \ + 16, 16); \ +} + +#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - get_avr64(t0, rA(ctx->opcode), true); \ - get_avr64(t1, rB(ctx->opcode), true); \ - tcg_op(avr, t0, t1); \ - set_avr64(rD(ctx->opcode), avr, true); \ \ - get_avr64(t0, rA(ctx->opcode), false); \ - get_avr64(t1, rB(ctx->opcode), false); \ - tcg_op(avr, t0, t1); \ - set_avr64(rD(ctx->opcode), avr, false); \ + tcg_op(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rA(ctx->opcode), true), \ + avr64_offset(rB(ctx->opcode), true), \ + 16, 16); \ \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(avr); \ + tcg_gen_gvec_not(vece, \ + avr64_offset(rD(ctx->opcode), true), \ + avr64_offset(rD(ctx->opcode), true), \ + 16, 16); \ } =20 -GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); -GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); -GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); -GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); -GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); -GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); -GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); -GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); +/* Logical operations */ +GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); +GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); +GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); +GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); +GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20); +GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26); +GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22); +GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); =20 #define GEN_VXFORM(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) = \ --=20 2.11.0