From nobody Sat Apr 20 10:44:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544119740303348.82715710323214; Thu, 6 Dec 2018 10:09:00 -0800 (PST) Received: from localhost ([::1]:42407 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy54-000452-W1 for importer@patchew.org; Thu, 06 Dec 2018 13:08:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy1L-0000hi-RJ for qemu-devel@nongnu.org; Thu, 06 Dec 2018 13:05:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUxsK-0004Cz-Lc for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:51 -0500 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]:38354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gUxsK-0004Co-Eq for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:48 -0500 Received: by mail-oi1-x229.google.com with SMTP id a77so1141009oii.5 for ; Thu, 06 Dec 2018 09:55:48 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id 18sm873756otf.59.2018.12.06.09.55.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Dec 2018 09:55:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lymSPyxoxv+wHA3sFaphw5duWIjjDuHM+r2rpCTXu0Y=; b=BSXk06VBIUJSZdsX1a+AgGD59ymJCznNFDOvpoYDPUn8N/Ac19oTKtItWX3YT8FiyL Lw4YWTr3QVmrfO9mASR+vIY4UdbOk+7KNplHfpz4YV3oRtj11rL/ASeDiMw9bCFUb2aO eMhZN7drj0owaNMBcEX+KI82YnFbR7ojjpjyI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lymSPyxoxv+wHA3sFaphw5duWIjjDuHM+r2rpCTXu0Y=; b=HkYQTsGDgIgd4x3Et6xY2gz4poq8qlgvasVeJMHdBWNxYuze+afUSwTUXTt/2pp3aM YXdNlyqen7aI4d5g9sfI/M4FoD5cVnHzWZRhfNQIZZGD5eS3kRASLI3HHHJXa2Xdc5KP xz4wsWcx8jmrk0SGCB+lKkgYjLoA0PJvjlc+cn5NhNzPNkD7nccuM5OKYL0riEzL7ecj uEF3M8csfdoVGwfwpp2Mqvgr0DOjnuAsnrCXojK4SvLHDzcOM8Ecid07DLEGRRcx9VQh qEFDgUuObP8DlVgoO7E9SgnTG7mCSHUnGD+7sPr0iXRkrFerDD4wrEdV80CDFZsPVbps 4BJg== X-Gm-Message-State: AA+aEWbmCEF+HHQoECrPYjo04Hijf3aMScLoNUluzo9PDqkcKInWDmZV 279WzyoUUmjnhH6oNnKYuR1VIvCGg9oxeQ== X-Google-Smtp-Source: AFSGD/Xi3knz0Kv5WXUKpDyowsQPT/DPaw/Svas3ZzVqgRjBcRPItbaEPi6FrKQWCxINOyVXOVKSDg== X-Received: by 2002:aca:2dc8:: with SMTP id t191mr17201468oit.235.1544118947216; Thu, 06 Dec 2018 09:55:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Dec 2018 11:55:39 -0600 Message-Id: <20181206175541.29508-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181206175541.29508-1-richard.henderson@linaro.org> References: <20181206175541.29508-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::229 Subject: [Qemu-devel] [PATCH v3 1/3] target/arm: Introduce arm_hcr_el2_eff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into account, as documented for the plethora of bits in HCR_EL2. Signed-off-by: Richard Henderson ---- v3: Fix set of bits affected by just TGE. Reorder the bits to ascending order. Zap VF,VI,VSE when !TGE and ![FIA]MO. --- target/arm/cpu.h | 67 ++++++++-------------------------- hw/intc/arm_gicv3_cpuif.c | 21 +++++------ target/arm/helper.c | 76 ++++++++++++++++++++++++++++++++++----- 3 files changed, 93 insertions(+), 71 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11ec2cce76..05ac883b6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1729,6 +1729,14 @@ static inline bool arm_is_secure(CPUARMState *env) } #endif =20 +/** + * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. + * E.g. when in secure state, fields in HCR_EL2 are suppressed, + * "for all purposes other than a direct read or write access of HCR_EL2." + * Not included here is HCR_RW. + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env); + /* Return true if the specified exception level is running in AArch64 stat= e. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -2414,54 +2422,6 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -/** - * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO. - * Depending on the values of HCR_EL2.E2H and TGE, this may be - * "behaves as 1 for all purposes other than direct read/write" or - * "behaves as 0 for all purposes other than direct read/write" - */ -static inline bool arm_hcr_el2_imo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_IMO; - } -} - -/** - * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO. - */ -static inline bool arm_hcr_el2_fmo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_FMO; - } -} - -/** - * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO. - */ -static inline bool arm_hcr_el2_amo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_AMO; - } -} - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { @@ -2470,6 +2430,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, bool secure =3D arm_is_secure(env); bool pstate_unmasked; int8_t unmasked =3D 0; + uint64_t hcr_el2; =20 /* Don't take exceptions if they target a lower EL. * This check should catch any exceptions that would not be taken but = left @@ -2479,6 +2440,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, return false; } =20 + hcr_el2 =3D arm_hcr_el2_eff(env); + switch (excp_idx) { case EXCP_FIQ: pstate_unmasked =3D !(env->daif & PSTATE_F); @@ -2489,13 +2452,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, break; =20 case EXCP_VFIQ: - if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TG= E)) { + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TG= E)) { + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } @@ -2534,7 +2497,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * to the CPSR.F setting otherwise we further assess the s= tate * below. */ - hcr =3D arm_hcr_el2_fmo(env); + hcr =3D hcr_el2 & HCR_FMO; scr =3D (env->cp15.scr_el3 & SCR_FIQ); =20 /* When EL3 is 32-bit, the SCR.FW bit controls whether the @@ -2551,7 +2514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * when setting the target EL, so it does not have a furth= er * affect here. */ - hcr =3D arm_hcr_el2_imo(env); + hcr =3D hcr_el2 & HCR_IMO; scr =3D false; break; default: diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 068a8e8e9b..cbad6037f1 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -85,8 +85,8 @@ static bool icv_access(CPUARMState *env, int hcr_flags) * * access if NS EL1 and either IMO or FMO =3D=3D 1: * CTLR, DIR, PMR, RPR */ - bool flagmatch =3D ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) || - ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env)); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool flagmatch =3D hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); =20 return flagmatch && arm_current_el(env) =3D=3D 1 && !arm_is_secure_below_el3(env); @@ -1552,8 +1552,9 @@ static void icc_dir_write(CPUARMState *env, const ARM= CPRegInfo *ri, /* No need to include !IsSecure in route_*_to_el2 as it's only * tested in cases where we know !IsSecure is true. */ - route_fiq_to_el2 =3D arm_hcr_el2_fmo(env); - route_irq_to_el2 =3D arm_hcr_el2_imo(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + route_fiq_to_el2 =3D hcr_el2 & HCR_FMO; + route_irq_to_el2 =3D hcr_el2 & HCR_IMO; =20 switch (arm_current_el(env)) { case 3: @@ -1895,8 +1896,8 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState= *env, if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) =3D=3D (SCR_FIQ | SCR_IR= Q)) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - (arm_hcr_el2_imo(env) =3D=3D 0 && arm_hcr_el2_fmo(env) =3D= =3D 0)) { + /* Note that arm_hcr_el2_eff takes secure state into account. = */ + if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) =3D=3D 0) { r =3D CP_ACCESS_TRAP_EL3; } break; @@ -1936,8 +1937,8 @@ static CPAccessResult gicv3_dir_access(CPUARMState *e= nv, static CPAccessResult gicv3_sgi_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) && - arm_current_el(env) =3D=3D 1 && !arm_is_secure_below_el3(env)) { + if (arm_current_el(env) =3D=3D 1 && + (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) !=3D 0) { /* Takes priority over a possible EL3 trap */ return CP_ACCESS_TRAP_EL2; } @@ -1961,7 +1962,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *e= nv, if (env->cp15.scr_el3 & SCR_FIQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_FMO) =3D=3D 0) { r =3D CP_ACCESS_TRAP_EL3; } break; @@ -2000,7 +2001,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *e= nv, if (env->cp15.scr_el3 & SCR_IRQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_IMO) =3D=3D 0) { r =3D CP_ACCESS_TRAP_EL3; } break; diff --git a/target/arm/helper.c b/target/arm/helper.c index 037cece133..63e02e9fa2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1331,9 +1331,10 @@ static void csselr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs =3D ENV_GET_CPU(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint64_t ret =3D 0; =20 - if (arm_hcr_el2_imo(env)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |=3D CPSR_I; } @@ -1343,7 +1344,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMC= PRegInfo *ri) } } =20 - if (arm_hcr_el2_fmo(env)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |=3D CPSR_F; } @@ -4008,6 +4009,61 @@ static void hcr_writelow(CPUARMState *env, const ARM= CPRegInfo *ri, hcr_write(env, NULL, value); } =20 +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret =3D env->cp15.hcr_el2; + + if (arm_is_secure_below_el3(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + ret =3D 0; + } else if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.4. */ + if (ret & HCR_E2H) { + ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); + } else { + ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); + } else { + if (!(ret & HCR_FMO)) { + ret &=3D ~HCR_VF; + } + if (!(ret & HCR_IMO)) { + ret &=3D ~HCR_VI; + } + if (!(ret & HCR_AMO)) { + ret &=3D ~HCR_VSE; + } + } + + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_IO, @@ -6526,12 +6582,13 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint= 32_t excp_idx, uint32_t cur_el, bool secure) { CPUARMState *env =3D cs->env_ptr; - int rw; - int scr; - int hcr; + bool rw; + bool scr; + bool hcr; int target_el; /* Is the highest EL AArch64? */ - int is64 =3D arm_feature(env, ARM_FEATURE_AARCH64); + bool is64 =3D arm_feature(env, ARM_FEATURE_AARCH64); + uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { rw =3D ((env->cp15.scr_el3 & SCR_RW) =3D=3D SCR_RW); @@ -6543,18 +6600,19 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint= 32_t excp_idx, rw =3D is64; } =20 + hcr_el2 =3D arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: scr =3D ((env->cp15.scr_el3 & SCR_IRQ) =3D=3D SCR_IRQ); - hcr =3D arm_hcr_el2_imo(env); + hcr =3D hcr_el2 & HCR_IMO; break; case EXCP_FIQ: scr =3D ((env->cp15.scr_el3 & SCR_FIQ) =3D=3D SCR_FIQ); - hcr =3D arm_hcr_el2_fmo(env); + hcr =3D hcr_el2 & HCR_FMO; break; default: scr =3D ((env->cp15.scr_el3 & SCR_EA) =3D=3D SCR_EA); - hcr =3D arm_hcr_el2_amo(env); + hcr =3D hcr_el2 & HCR_AMO; break; }; =20 --=20 2.17.2 From nobody Sat Apr 20 10:44:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544119763293132.98603679745656; Thu, 6 Dec 2018 10:09:23 -0800 (PST) Received: from localhost ([::1]:42408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy5S-0004eJ-0G for importer@patchew.org; Thu, 06 Dec 2018 13:09:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy1L-0000gP-Fq for qemu-devel@nongnu.org; Thu, 06 Dec 2018 13:05:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUxsL-0004DT-SN for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:51 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:36906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gUxsL-0004DF-NH for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:49 -0500 Received: by mail-ot1-x344.google.com with SMTP id 40so1243008oth.4 for ; Thu, 06 Dec 2018 09:55:49 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id 18sm873756otf.59.2018.12.06.09.55.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Dec 2018 09:55:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zq48Z2eg8XJ9v15+H+TssxaHrkLh4uLulKFqydJ78JY=; b=f9TtAPLxFBF5bJ/ZYZnolpiW9nKPe7R1KFA4P5niSJ0sXsYEgVSC8hgCw0JTtrf6M8 Pdb++tmc0u0oXRKsPx81Xo8C5gzXJZ4F7hn7NPNCa9VXenfmJn7YcqYI6U+/Hbnm7e7r clk2So4vIiq4jSsQqjgPpH7VFcHbUWNgs+StI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zq48Z2eg8XJ9v15+H+TssxaHrkLh4uLulKFqydJ78JY=; b=qLcLTlz7rm26liqo4dNmL/BxcPZjkDA/HwP/dv9hI6qmkRSb+glGDK1IB4J3oCmeLT CApLgXZt543MQyCXJRnXr1Xy82e/IcK0RiCABr9ILi2TcOkqYLEiIP0p44XSmy5R+ulB ArwyiDLiA/SiSyXbcdyKuWENwbwTyN3OL7mH1ADitHCHk1zjP/SXO2RfTnweoLZ/AepA fnhxsx2B0OCxrwfajy8uwuUVHOjjv0WlQmMimwOsMexh6KO8T8iZNnxYoLoschPKRp9y og+/SN7OwzTJyad4pf0CMvIFco9UThbvvMBonhvRlbJEu5lVbLgG0d+Mquk/lZxLIAQK 8aJw== X-Gm-Message-State: AA+aEWbXRaeZTt3fZztJcrh6PMorKplD6jZURwVuZfl5jmWs+pvMu0bb FZmjiFvnl+TC4Nnrdr4GqHzn2lOyaGoxdg== X-Google-Smtp-Source: AFSGD/X5U4xj5/msq9xo2i/lfJ+YL9lSNL2Ce0NJR2RnhhEQhzSX/Nchj270QE3o8hxjL08Ptlmt8w== X-Received: by 2002:a9d:3646:: with SMTP id w64mr17587875otb.118.1544118948548; Thu, 06 Dec 2018 09:55:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Dec 2018 11:55:40 -0600 Message-Id: <20181206175541.29508-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181206175541.29508-1-richard.henderson@linaro.org> References: <20181206175541.29508-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v3 2/3] target/arm: Use arm_hcr_el2_eff more places X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since arm_hcr_el2_eff includes a check against arm_is_secure_below_el3, we can often remove a nearby check against secure state. In some cases, sort the call to arm_hcr_el2_eff to the end of a short-circuit logical sequence. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Do not change regime_translation_disabled. --- target/arm/helper.c | 12 +++++------- target/arm/op_helper.c | 14 ++++++-------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 63e02e9fa2..4d25bafd12 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -448,7 +448,7 @@ static CPAccessResult access_tdosa(CPUARMState *env, co= nst ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tdosa =3D (env->cp15.mdcr_el2 & MDCR_TDOSA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -468,7 +468,7 @@ static CPAccessResult access_tdra(CPUARMState *env, con= st ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tdra =3D (env->cp15.mdcr_el2 & MDCR_TDRA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -488,7 +488,7 @@ static CPAccessResult access_tda(CPUARMState *env, cons= t ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tda =3D (env->cp15.mdcr_el2 & MDCR_TDA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -4576,8 +4576,7 @@ int sve_exception_el(CPUARMState *env, int el) if (disabled) { /* route_to_el2 */ return (arm_feature(env, ARM_FEATURE_EL2) - && !arm_is_secure(env) - && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1); + && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); } =20 /* Check CPACR.FPEN. */ @@ -6226,9 +6225,8 @@ static int bad_mode_switch(CPUARMState *env, int mode= , CPSRWriteType write_type) * and CPS are treated as illegal mode changes. */ if (write_type =3D=3D CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { + (arm_hcr_el2_eff(env) & HCR_TGE)) { return 1; } return 0; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0d6e89e474..ef72361a36 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,8 +33,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, { CPUState *cs =3D CPU(arm_env_get_cpu(env)); =20 - if ((env->cp15.hcr_el2 & HCR_TGE) && - target_el =3D=3D 1 && !arm_is_secure(env)) { + if (target_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* * Redirect NS EL1 exceptions to NS EL2. These are reported with * their original syndrome register value, with the exception of @@ -428,9 +427,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the * bits will be zero indicating no trap. */ - if (cur_el < 2 && !arm_is_secure(env)) { - mask =3D (is_wfe) ? HCR_TWE : HCR_TWI; - if (env->cp15.hcr_el2 & mask) { + if (cur_el < 2) { + mask =3D is_wfe ? HCR_TWE : HCR_TWI; + if (arm_hcr_el2_eff(env) & mask) { return 2; } } @@ -995,7 +994,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrom= e) exception_target_el(env)); } =20 - if (!secure && cur_el =3D=3D 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + if (cur_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. * We also want an EL2 guest to be able to forbid its EL1 from * making PSCI calls into QEMU's "firmware" via HCR.TSC. @@ -1098,8 +1097,7 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } =20 - if (new_el =3D=3D 1 && (env->cp15.hcr_el2 & HCR_TGE) - && !arm_is_secure_below_el3(env)) { + if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } =20 --=20 2.17.2 From nobody Sat Apr 20 10:44:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544119699374485.7284752375426; Thu, 6 Dec 2018 10:08:19 -0800 (PST) Received: from localhost ([::1]:42405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy4Q-00031I-1l for importer@patchew.org; Thu, 06 Dec 2018 13:08:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46157) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUy1L-0000hl-CR for qemu-devel@nongnu.org; Thu, 06 Dec 2018 13:05:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUxsN-0004ED-Ah for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:52 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:35642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gUxsN-0004Dx-4k for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:55:51 -0500 Received: by mail-oi1-x243.google.com with SMTP id v6so1152975oif.2 for ; Thu, 06 Dec 2018 09:55:51 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id 18sm873756otf.59.2018.12.06.09.55.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Dec 2018 09:55:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0B/G4FmI+h9HzG+GTEg9D78s05gOBmsBKnkq5yNo1VA=; b=aBrYWT2pGZa6nsajrZ0BL2VIREtecjJ6D0v8RdW+dO2wAR8uSftW9AeweASShC8EsG R0bxmx4Hq+6kl0Wrd8SBiRmNqEN3l2xgLu08Ne7B3IJvt7Fa/OtkGCHrJH2o2DMuzgYP rmHMdjMxwzlUqcXBnqFr0elZ7ywHK/L3PVnmc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0B/G4FmI+h9HzG+GTEg9D78s05gOBmsBKnkq5yNo1VA=; b=R/lwHcsU79ycUaZfcWQgD48vVrIVdDaQtc70TKcy0iTU+oNqxS+EPQ70+FzvD1RhYg PAKXBST167t4QX9FrQGSHN+b7XZ4dqNPDUKSeFXfNM6IPrGxeOLC0oEJDlAVT1K7e05c rlutykKDsLbWIJzIlcJi1gJLBS23TZveJfrHFVL1cOVNYRXRpyhEQCNRMAUI34vHSPhd stCS3AFPYE83+LxJMVEMx60e4fHclnkoDAdEcLM+ozaatTCdfB7hiFah6t2JqVTeNCy2 e038QgNg/Pmyr8Vya692x26nGg9RGKGR5eMboXHBYe0CcaTvdtMxPiHecIOvmQdF2m+S +6ww== X-Gm-Message-State: AA+aEWZC2D0GbNU3lJCtVe84NdZprA5xsAaUmh+G6paLXHAxOgGyV4NX 3r73qHGCi2tbvHxLhvKU/RwCKBKWRgN5Yw== X-Google-Smtp-Source: AFSGD/UA92joKFJ7C1ZanCYoISVArxT0xK5De+ePkskGwAqR/YrXJX1tPG82tmi2OPbwI0tttsRugQ== X-Received: by 2002:aca:ea57:: with SMTP id i84mr18368727oih.346.1544118949766; Thu, 06 Dec 2018 09:55:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Dec 2018 11:55:41 -0600 Message-Id: <20181206175541.29508-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181206175541.29508-1-richard.henderson@linaro.org> References: <20181206175541.29508-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v3 3/3] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Mark LORID_EL1 read-only. Add TLOR access checks. Conditionally unmask TLOR in hcr/scr_write. v3: Fix isar_feature_aa64_lor. Split out access_lor_ns. Defer all {E2H,TGE} vs TLOR testing to arm_hcr_el2_eff. --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 1 + target/arm/helper.c | 75 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++ 4 files changed, 93 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05ac883b6b..c943f35dd9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3340,6 +3340,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; } =20 +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1a4289c9dd..1d57be0c91 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -326,6 +326,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 4d25bafd12..1e20956376 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1281,6 +1281,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; + ARMCPU *cpu =3D arm_env_get_cpu(env); =20 if (arm_el_is_aa64(env, 3)) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1303,6 +1304,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) valid_mask &=3D ~SCR_SMD; } } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D SCR_TLOR; + } =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; @@ -3963,6 +3967,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D HCR_TLOR; + } =20 /* Clear RES0 bits. */ value &=3D valid_mask; @@ -5028,6 +5035,42 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, c= onst ARMCPRegInfo *ri) return pfr0; } =20 +/* Shared logic between LORID and the rest of the LOR* registers. + * Secure state has already been delt with. + */ +static CPAccessResult access_lor_ns(CPUARMState *env) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access ok in secure mode. */ + return CP_ACCESS_OK; + } + return access_lor_ns(env); +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + return access_lor_ns(env); +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5769,6 +5812,38 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } =20 + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd36425f1a..e1da1e4d6f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) } return; =20 + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fall through */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fall through */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { --=20 2.17.2