From nobody Fri Apr 19 18:57:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544116514039311.150560316873; Thu, 6 Dec 2018 09:15:14 -0800 (PST) Received: from localhost ([::1]:42195 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUxF2-00061f-MB for importer@patchew.org; Thu, 06 Dec 2018 12:15:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUx8D-0000JY-3H for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:08:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUx84-0002wl-59 for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:08:07 -0500 Received: from mx1.redhat.com ([209.132.183.28]:58360) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUx7k-0002kQ-VN; Thu, 06 Dec 2018 12:07:41 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EAABA3084042; Thu, 6 Dec 2018 17:07:39 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.36.117.0]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5D2675D9D6; Thu, 6 Dec 2018 17:07:38 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, shannon.zhaosl@gmail.com Date: Thu, 6 Dec 2018 18:07:32 +0100 Message-Id: <20181206170733.7469-2-eric.auger@redhat.com> In-Reply-To: <20181206170733.7469-1-eric.auger@redhat.com> References: <20181206170733.7469-1-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.40]); Thu, 06 Dec 2018 17:07:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.0 v2 1/2] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shameerali.kolothum.thodi@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let's report IO-coherent access is supported for translation table walks, descriptor fetches and queues by setting the COHACC override flag. Without that, we observe wrong command opcodes. The DT description also advertises the dma coherency. Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table") Signed-off-by: Eric Auger Reported-by: Shameerali Kolothum Thodi Tested-by: Shameer Kolothum Reviewed-by: Andrew Jones --- - change the commit title - addition of new fields (pxm and id_mapping_index) done in a separate patch --- hw/arm/virt-acpi-build.c | 1 + include/hw/acpi/acpi-defs.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 5785fb697c..aa177ba64d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -448,6 +448,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) smmu->mapping_count =3D cpu_to_le32(1); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->flags =3D ACPI_IORT_SMMU_V3_COHACC_OVERRIDE; smmu->event_gsiv =3D cpu_to_le32(irq); smmu->pri_gsiv =3D cpu_to_le32(irq + 1); smmu->gerr_gsiv =3D cpu_to_le32(irq + 2); diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index af8e023968..532eaf79bd 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -628,6 +628,8 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; =20 +#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 + struct AcpiIortSmmu3 { ACPI_IORT_NODE_HEADER_DEF uint64_t base_address; --=20 2.17.2 From nobody Fri Apr 19 18:57:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544116323820370.6071069416096; Thu, 6 Dec 2018 09:12:03 -0800 (PST) Received: from localhost ([::1]:42180 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUxBy-0003CH-Lg for importer@patchew.org; Thu, 06 Dec 2018 12:12:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUx87-0000Dz-KT for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:08:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUx7u-0002sF-0K for qemu-devel@nongnu.org; Thu, 06 Dec 2018 12:07:56 -0500 Received: from mx1.redhat.com ([209.132.183.28]:39588) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUx7m-0002lx-JU; Thu, 06 Dec 2018 12:07:42 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D094B88E64; Thu, 6 Dec 2018 17:07:41 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.36.117.0]) by smtp.corp.redhat.com (Postfix) with ESMTP id 404E95D9CD; Thu, 6 Dec 2018 17:07:40 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, shannon.zhaosl@gmail.com Date: Thu, 6 Dec 2018 18:07:33 +0100 Message-Id: <20181206170733.7469-3-eric.auger@redhat.com> In-Reply-To: <20181206170733.7469-1-eric.auger@redhat.com> References: <20181206170733.7469-1-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Thu, 06 Dec 2018 17:07:41 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH-for-4.0 v2 2/2] hw/arm/virt-acpi-build: IORT Update for revision D X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shameerali.kolothum.thodi@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let's update the structs according to revision D of the IORT specification and set the IORT node revision fields. In IORT smmuv3 node: the new proximity field is not used as the proximity domain valid flag is not set. The new DeviceId mapping index is not used either as all the SMMU control interrupts are GSIV based. In IORT RC node: the new memory address size limit field is set to 64 bits. Signed-off-by: Eric Auger --- v1 -> v2: - separate patches for SMMUv3 DMA coherency issue and struct update to revision D. - revision fields set --- hw/arm/virt-acpi-build.c | 4 ++++ include/hw/acpi/acpi-defs.h | 10 +++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index aa177ba64d..a34a0958a5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -423,6 +423,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) */ iort_node_offset =3D sizeof(*iort); iort->node_offset =3D cpu_to_le32(iort_node_offset); + iort->revision =3D 0; =20 /* ITS group node */ node_size =3D sizeof(*its) + sizeof(uint32_t); @@ -445,6 +446,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) =20 smmu->type =3D ACPI_IORT_NODE_SMMU_V3; smmu->length =3D cpu_to_le16(node_size); + smmu->revision =3D cpu_to_le32(2); smmu->mapping_count =3D cpu_to_le32(1); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); @@ -470,6 +472,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) =20 rc->type =3D ACPI_IORT_NODE_PCI_ROOT_COMPLEX; rc->length =3D cpu_to_le16(node_size); + rc->revision =3D cpu_to_le32(1); rc->mapping_count =3D cpu_to_le32(1); rc->mapping_offset =3D cpu_to_le32(sizeof(*rc)); =20 @@ -477,6 +480,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc->memory_properties.cache_coherency =3D cpu_to_le32(1); rc->memory_properties.memory_flags =3D 0x3; /* CCA =3D CPM =3D DCAS = =3D 1 */ rc->pci_segment_number =3D 0; /* MCFG pci_segment */ + rc->memory_address_limit =3D 64; =20 /* Identity RID mapping covering the whole input RID range */ idmap =3D &rc->id_mapping_array[0]; diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 532eaf79bd..b4a5104367 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -628,7 +628,11 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; =20 -#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 +enum { + ACPI_IORT_SMMU_V3_COHACC_OVERRIDE =3D 1 << 0, + ACPI_IORT_SMMU_V3_HTTU_OVERRIDE =3D 3 << 1, + ACPI_IORT_SMMU_V3_PXM_VALID =3D 1 << 3 +}; =20 struct AcpiIortSmmu3 { ACPI_IORT_NODE_HEADER_DEF @@ -641,6 +645,8 @@ struct AcpiIortSmmu3 { uint32_t pri_gsiv; uint32_t gerr_gsiv; uint32_t sync_gsiv; + uint32_t pxm; + uint32_t id_mapping_index; AcpiIortIdMapping id_mapping_array[0]; } QEMU_PACKED; typedef struct AcpiIortSmmu3 AcpiIortSmmu3; @@ -650,6 +656,8 @@ struct AcpiIortRC { AcpiIortMemoryAccess memory_properties; uint32_t ats_attribute; uint32_t pci_segment_number; + uint8_t memory_address_limit; + uint8_t reserved2[3]; AcpiIortIdMapping id_mapping_array[0]; } QEMU_PACKED; typedef struct AcpiIortRC AcpiIortRC; --=20 2.17.2