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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z43Io25FDRfAJAuHVfPMb9jTaGXjo3dOTCEiU/3353I=; b=LH6K3IOF8/SuPhQy0BLXEH89DGfboHfMMnOuPIF1wzmD2qbvtiIi3nSJ/CYKxFOBKa gSem0LtVy9Kt1s7QFAYcMpSvaNHYeFY4s/JxGaEA6JJvQX+LI5zWqhuQkMnddDtYj3sa lVWnOgL+Zq8Eh1q6wboHXeegbhKttlyPy8xfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z43Io25FDRfAJAuHVfPMb9jTaGXjo3dOTCEiU/3353I=; b=kW823GmxBWCVHbuou89CNKr+FVwBDw+7KbPOe38z/ANe6Co4LB0brQKbdqWjEQibYA TM39G1L7Pa+lXivH9swfuJs/2YUATQ1BBP2u/ZVu+Seg9VNUTpLA8/q8s9tfm4OqQ84V PSI6a4emqaO0qP0lf+Kiabo82WqyYasDAOZ5Kd8xjkJXlS2s9cp4QAfhccLqs3rppDzr YjQMdzlno21Gajz10w8uUwijGjnG+SfvvvDLuadtK3kJW6ruYiekN2WWBLK5mfoBVUeI nuVEhNz9Th+IBxMFu4EXMNaNqcX7UgZrtH6mnTUJ+MaInbX2ITbIuQEzTPab8KZ0shCc ThJg== X-Gm-Message-State: AA+aEWah3QPFj09y4Ao+JbtmwTbu4sN7dWY0Ofbo+ygjIpdbluuJFDkm ebsJq/ONEOOW9PS0l11LgmN2n37OjqE= X-Google-Smtp-Source: AFSGD/V5s3mqIAFt0NpJP3YZYwTw50hhmIsfKs+4Pofh0lOB2uCPkp7NRsLK0yRyqyNTI3qw9BC20g== X-Received: by 2002:a9d:5f13:: with SMTP id f19mr1235818oti.267.1543869535605; Mon, 03 Dec 2018 12:38:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:37 -0600 Message-Id: <20181203203839.757-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 08/10] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Signed-off-by: Richard Henderson --- v2: Mark LORID_EL1 read-only. Add TLOR access checks. Conditionally unmask TLOR in hcr/scr_write. --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 4 ++ target/arm/helper.c | 91 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 +++++ 4 files changed, 112 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a84101efa9..ba0c368292 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3285,6 +3285,11 @@ static inline bool isar_feature_aa64_atomics(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR1, LO) !=3D 0; +} + static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0babe483ac..aac6283018 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 =3D t; =20 + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + cpu->isar.id_aa64mmfr1 =3D t; + /* Replicate the same data to the 32-bit id registers. */ u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ diff --git a/target/arm/helper.c b/target/arm/helper.c index faf7f922bf..a0ee1fbc5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1281,6 +1281,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; + ARMCPU *cpu =3D arm_env_get_cpu(env); =20 if (arm_el_is_aa64(env, 3)) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1303,6 +1304,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) valid_mask &=3D ~SCR_SMD; } } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D SCR_TLOR; + } =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; @@ -3950,6 +3954,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D HCR_TLOR; + } =20 /* Clear RES0 bits. */ value &=3D valid_mask; @@ -5004,6 +5011,58 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, c= onst ARMCPRegInfo *ri) return pfr0; } =20 +static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + + if (arm_is_secure_below_el3(env)) { + /* Access ok in secure mode. */ + return CP_ACCESS_OK; + } + if (el < 2 && arm_el_is_aa64(env, 2)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + hcr &=3D HCR_TLOR; + } else { + hcr &=3D HCR_TGE | HCR_TLOR; + } + if (hcr =3D=3D HCR_TLOR) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + if (el < 2 && arm_el_is_aa64(env, 2)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + hcr &=3D HCR_TLOR; + } else { + hcr &=3D HCR_TGE | HCR_TLOR; + } + if (hcr =3D=3D HCR_TLOR) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5741,6 +5800,38 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } =20 + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd36425f1a..5952a9d1cc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) } return; =20 + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fallthru */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fallthru */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { --=20 2.17.2