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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6RfiLtXmRtrO+0NSs93kQ3AQ83RCZmslZZ/FXyGURgE=; b=dIKV4CGWmzcAzloLJ5WTuKaKhz4POEzSoF81vE3X8wk1kJHzVv8V5UvkARuFnjjYCO wYSQglVi6UeMMrjaUmnXZ01eT2zaAYB4V0bn0NBiTOqah/UgwY0rcydBL/ewoebCaRNi utTxuR1RPaI4/ArM5XfbNlo9QWeaTnStIw7r4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6RfiLtXmRtrO+0NSs93kQ3AQ83RCZmslZZ/FXyGURgE=; b=VuU1FMT5P91gE7H4ITJdlwr+NsosE4K0bDTwnXWIDKxa98MiVOQlklhUcPvpnbGJCH iBBI3mS1IfYdUaOuRuDjpAIcV844orEZG/Ibw3TH5FApqAYK9DfTk+1Tl3RPFIXxiJh5 FKrdb4F1jys+49a5esMiRS0i508vaTdxOL4GhBJ4u9u5a8F4ygcYjyjhlIVRlkc1wpL1 c8YhduD7c74MoPG4cdADj36fDz5HL4S/gZESW2W7voXgdQtLwYZMCrPoYEFhI2ZekPoX LJP7zgJOxRipwmJVwLxhIQxpQwUP8h2C/xvMZw8cYlzGGcToT3UUpYSJA+v6jE3CN649 gakg== X-Gm-Message-State: AA+aEWbyEptCQzSpVqnSwnu0wUi55J+geMl39LLc/gTnXHqbMR1ASnBL QL1lMus27MOD6iR5LaeCbYRbviIKza8= X-Google-Smtp-Source: AFSGD/WPEbZQnzjoqaoOKdJj/7w365T4snFiyGqwhZzlI+cDnTtuHat2O+PrWC33gwZTRUc5iQy44A== X-Received: by 2002:a9d:491e:: with SMTP id e30mr11657639otf.131.1543869532493; Mon, 03 Dec 2018 12:38:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:35 -0600 Message-Id: <20181203203839.757-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 06/10] target/arm: Use arm_hcr_el2_eff more places X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since arm_hcr_el2_eff includes a check against arm_is_secure_below_el3, we can often remove a nearby check against secure state. In some cases, sort the call to arm_hcr_el2_eff to the end of a short-circuit logical sequence. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++---------- target/arm/op_helper.c | 14 ++++++-------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5874c5a73f..b248dfcd39 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -448,7 +448,7 @@ static CPAccessResult access_tdosa(CPUARMState *env, co= nst ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tdosa =3D (env->cp15.mdcr_el2 & MDCR_TDOSA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -468,7 +468,7 @@ static CPAccessResult access_tdra(CPUARMState *env, con= st ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tdra =3D (env->cp15.mdcr_el2 & MDCR_TDRA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -488,7 +488,7 @@ static CPAccessResult access_tda(CPUARMState *env, cons= t ARMCPRegInfo *ri, int el =3D arm_current_el(env); bool mdcr_el2_tda =3D (env->cp15.mdcr_el2 & MDCR_TDA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); =20 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -4548,8 +4548,7 @@ int sve_exception_el(CPUARMState *env, int el) if (disabled) { /* route_to_el2 */ return (arm_feature(env, ARM_FEATURE_EL2) - && !arm_is_secure(env) - && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1); + && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); } =20 /* Check CPACR.FPEN. */ @@ -6194,9 +6193,8 @@ static int bad_mode_switch(CPUARMState *env, int mode= , CPSRWriteType write_type) * and CPS are treated as illegal mode changes. */ if (write_type =3D=3D CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { + (arm_hcr_el2_eff(env) & HCR_TGE)) { return 1; } return 0; @@ -8797,6 +8795,8 @@ static inline uint32_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { + uint64_t hcr_el2; + if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { @@ -8815,19 +8815,21 @@ static inline bool regime_translation_disabled(CPUA= RMState *env, } } =20 + hcr_el2 =3D arm_hcr_el2_eff(env); + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { /* HCR.DC means HCR.VM behaves as 1 */ - return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; + return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } =20 - if (env->cp15.hcr_el2 & HCR_TGE) { + if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { return true; } } =20 - if ((env->cp15.hcr_el2 & HCR_DC) && + if ((hcr_el2 & HCR_DC) && (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0d6e89e474..780caf387b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,8 +33,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, { CPUState *cs =3D CPU(arm_env_get_cpu(env)); =20 - if ((env->cp15.hcr_el2 & HCR_TGE) && - target_el =3D=3D 1 && !arm_is_secure(env)) { + if (target_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* * Redirect NS EL1 exceptions to NS EL2. These are reported with * their original syndrome register value, with the exception of @@ -428,9 +427,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the * bits will be zero indicating no trap. */ - if (cur_el < 2 && !arm_is_secure(env)) { - mask =3D (is_wfe) ? HCR_TWE : HCR_TWI; - if (env->cp15.hcr_el2 & mask) { + if (cur_el < 2) { + mask =3D is_wfe ? HCR_TWE : HCR_TWI; + if (arm_hcr_el2_eff(env) & mask) { return 2; } } @@ -995,7 +994,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrom= e) exception_target_el(env)); } =20 - if (!secure && cur_el =3D=3D 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + if (!secure && cur_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. * We also want an EL2 guest to be able to forbid its EL1 from * making PSCI calls into QEMU's "firmware" via HCR.TSC. @@ -1098,8 +1097,7 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } =20 - if (new_el =3D=3D 1 && (env->cp15.hcr_el2 & HCR_TGE) - && !arm_is_secure_below_el3(env)) { + if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } =20 --=20 2.17.2