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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8zBIr54yy4Wx+NC0wja/S07a0aK29AJFkz7XU3SN6ps=; b=TavhSzEls7W/F6E/cQ4bpa5mim0XK5pQdcFn9iCKcNqTdsDR0h5h0f6gbox7E71PYT 2DhvAVF4YHEpsjFZyC8x4th2D33uXczHcde5qj2BTNIswOWkViX5K0vwo8KsYtfr2llr bv+z1a341YclE0dldmFdyYBFx+4OqZEu8/yaY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8zBIr54yy4Wx+NC0wja/S07a0aK29AJFkz7XU3SN6ps=; b=svoBmi0sfr0+NIGrJ2FhhqQZe1ez2Ai1HzI/v3e7rC/ZO6K+fsz7xsINIRn1j9m5lV ANcewt0kP/klz8VZ5i/fv/AQrZWgRaf4IU68L6YKGhpcCTJAKuxzjIYo0re00esifJIs HtJRHjI1IiNUHccFv7x69LtGrAgjZWjx+2NwKpEAdYOeIEO0UL0HdAQzMxW6MdZz7uzU JB4CVwmYca5Jb0oviAZn9wtBH6u1i4gRUQk6Oh+jg/RLjH+mOh/LWARRO7nBdFdDmSLo 65zPFFIh+QgNiUnm4TewGSt35Gj1K4mLb3iAdXtPhETsA3EAgz7sxj2NIuZ99fK/IWVf 2cpw== X-Gm-Message-State: AA+aEWbv3uJjCSswhDt8XfGKiLKZSAqgtA+UOou0eXJzd3OcElnT5Acd WKtUZovcZ9BU/uMWHEjpXZpncl8yTT4= X-Google-Smtp-Source: AFSGD/UfEDNyvAjnPCzxGm7In7jfNjPseMZRlWMG6PGBqpt18pVtEQ79xXeYY+2W9/oUA7oD88wEyg== X-Received: by 2002:aca:5a06:: with SMTP id o6mr11158118oib.341.1543869538514; Mon, 03 Dec 2018 12:38:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:39 -0600 Message-Id: <20181203203839.757-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 10/10] target/arm: Implement the ARMv8.2-AA32HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The bulk of the work here, beyond base HPD, is defining the TTBCR2 register. In addition we must check TTBCR.T2E, which is not present (RES0) for AArch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 9 +++++++++ target/arm/cpu.c | 4 ++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++-------- 3 files changed, 42 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba0c368292..15daa2c050 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1548,6 +1548,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) +FIELD(ID_MMFR4, EVT, 28, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..0b185f8d30 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1932,6 +1932,10 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D t; + + t =3D cpu->id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + cpu->id_mmfr4 =3D t; } #endif } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9bb3e364d4..5df7a9e637 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2733,6 +2733,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D arm_env_get_cpu(env); + TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID @@ -2740,6 +2741,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, */ tlb_flush(CPU(cpu)); } + /* Preserve the high half of TCR_EL1, set via TTBCR2. */ + value =3D deposit64(tcr->raw_tcr, 0, 32, value); vmsa_ttbcr_raw_write(env, ri, value); } =20 @@ -2842,6 +2845,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing + * qemu tlbs nor adjusting cached masks. + */ +static const ARMCPRegInfo ttbcr2_reginfo =3D { + .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, +}; + static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5540,6 +5553,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); + /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ + if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); + } } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); @@ -9891,12 +9908,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, if (tg =3D=3D 2) { /* 16KB pages */ stride =3D 11; } - if (aarch64) { - if (el > 1) { - hpd =3D extract64(tcr->raw_tcr, 24, 1); - } else { - hpd =3D extract64(tcr->raw_tcr, 41, 1); - } + if (aarch64 && el > 1) { + hpd =3D extract64(tcr->raw_tcr, 24, 1); + } else { + hpd =3D extract64(tcr->raw_tcr, 41, 1); + } + if (!aarch64) { + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &=3D extract64(tcr->raw_tcr, 6, 1); } } else { /* We should only be here if TTBR1 is valid */ @@ -9913,8 +9932,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, if (tg =3D=3D 1) { /* 16KB pages */ stride =3D 11; } - if (aarch64) { - hpd =3D extract64(tcr->raw_tcr, 42, 1); + hpd =3D extract64(tcr->raw_tcr, 42, 1); + if (!aarch64) { + /* For aarch32, hpd1 is not enabled without t2e as well. */ + hpd &=3D extract64(tcr->raw_tcr, 6, 1); } } =20 --=20 2.17.2