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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K0xlyMQ/dOYdblPn1aCAZbPODNQLh5ktdiFooUbCPzE=; b=S1h6BbL1bWOjEfCgXkfg3j+hkmuxPoh8no1qIVDDwnLP8u8h9QbYYj4oAvILbylNfE VY4TROiwlIuWgiQNh/ZBpTkVPS/PjjFPeHEo7j3jsM4D7lWmf4oFoaWnV9DivKCCRot/ 7jHZ6GSTVpTvIhbl3385IPpz03PMAqPXRpUrM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K0xlyMQ/dOYdblPn1aCAZbPODNQLh5ktdiFooUbCPzE=; b=rXJPOV8fAy5G5xfbhKLCTUVuwSzEfI1fB6RwP34PfP4ARJ/R4aJsTpYvbSUo7aRRYc LStUgyzozrY4b0B4dLkYjazYS9sJgvg6aWk0DE3zFRdumBn21/aOR6HLAsRf5GZVyjCs lfPWeAsTpK7exixkYAf4P7oPHm1wiz6EIG47Rg+gM+W08G9cdCIIpApQEGkcXGnmZZAv oOszgUm5KwJ5fVqQFvBR8BMKQkY9sjwduxRTQo6vMTVKGBiqOg7iKRMgHZG2mP0tkNb4 ic1ivTgxL3wUXxAE+slZemlRVfCcdbU1C1YNpN2dctut7eypIs3VpacDZMyRV419sEWQ 10lg== X-Gm-Message-State: AA+aEWZK5fanHj/CK1JhsoQ3CpHSROU2R3vBm7cqyVJmMnVRrOuxyK/H ugvmcqP9ySQMBx6xEZn4ghksHtv3cHQ= X-Google-Smtp-Source: AFSGD/XH0m3/cwCWRa/sKTdTwqL+WoWb4SGNw0+HgwNyJRfnKDWndydgxKDgg1F/2HHZWVz+k5s9Og== X-Received: by 2002:a54:4698:: with SMTP id k24mr10202927oic.37.1543869537071; Mon, 03 Dec 2018 12:38:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:38 -0600 Message-Id: <20181203203839.757-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 09/10] target/arm: Implement the ARMv8.1-HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply interpret the bits as if ARMv8.1-HPD is present without checking. We will need a slightly different check for hpd for aarch32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + target/arm/helper.c | 27 ++++++++++++++++++++------- 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index aac6283018..1d57be0c91 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -325,6 +325,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index a0ee1fbc5a..9bb3e364d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9776,6 +9776,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, bool ttbr1_valid =3D true; uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); + bool hpd =3D false; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9890,6 +9891,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, if (tg =3D=3D 2) { /* 16KB pages */ stride =3D 11; } + if (aarch64) { + if (el > 1) { + hpd =3D extract64(tcr->raw_tcr, 24, 1); + } else { + hpd =3D extract64(tcr->raw_tcr, 41, 1); + } + } } else { /* We should only be here if TTBR1 is valid */ assert(ttbr1_valid); @@ -9905,6 +9913,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, if (tg =3D=3D 1) { /* 16KB pages */ stride =3D 11; } + if (aarch64) { + hpd =3D extract64(tcr->raw_tcr, 42, 1); + } } =20 /* Here we should have set up all the parameters for the translation: @@ -9998,7 +10009,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, descaddr =3D descriptor & descaddrmask; =20 if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may + /* Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). @@ -10023,15 +10034,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, break; } /* Merge in attributes from table descriptors */ - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APTable[1] =3D> AP= [2] */ + attrs |=3D nstable << 3; /* NS */ + if (hpd) { + /* HPD disables all the table attributes except NSTable. */ + break; + } + attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - if (extract32(tableattrs, 2, 1)) { - attrs &=3D ~(1 << 4); - } - attrs |=3D nstable << 3; /* NS */ + attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ + attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ break; } /* Here descaddr is the final physical address, and attributes --=20 2.17.2