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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a2J3CQI2OQ70TK1sm7OIeOp1575wsiXhLstcSeE4Wk8=; b=RRRN/YhDO3xLLAirlaFPndlR69RzIpsD5BDuzQk3U2kS7xpkuK3E5WWrmuuoaWG3Vr 7xBT3uZXT+5Owxs8xMFGe1bsmngSWJ/lyV5QipPF9ksoo6rn4FdVH6c3wrqm0nh72mUC rlyH7hqBVFh1giJfXKXlg7aqhG0EM0wwz50sA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a2J3CQI2OQ70TK1sm7OIeOp1575wsiXhLstcSeE4Wk8=; b=X9Hy6zsmhJ0Ef0zUA+Blr6aYHmKqbpfMEulhVAhC1Lsy4wnvx+pPzjStbudt/448WA aOVFNAJUJTMiw1LHTJasKYjs8zuahh/mdsBLQzC5clfXBGFaGMieJsdHBmZl+dsQMYxt th21Y7Eq7YwIF/xLgXeqjpTI558KrrtFOq0CxmaTnfRosDjqonVm2/V/kjHxevxeK/Wb z0YfEkWH3IAmN4USXeQDxtPhDtxGYzNRpgZE3RwIG+dMTkDdtOhHX6CBjpx3CJ6XXWhu LDIzJmTP+MbMSmVYqq1ivf0Msf/QLiUAM+QLNyMm1DQ/tkGW33wjxViv11AlSb9VPFSv BSZg== X-Gm-Message-State: AA+aEWaDPPZh4m9MIuypEY3R31BA6UhCYtWSIqBxzSJkMb8BAQb7n4Zl r/RFspZhPskRJms4yPEgM2BxP4GC/no0AQ== X-Google-Smtp-Source: AFSGD/Upb+/cd1Q09U6di5MHTSSlYadj9VeNXLrQC+9/Svf25idy3fUKoS/UCvYmdCq7Rj/UXO27FQ== X-Received: by 2002:a54:440d:: with SMTP id k13mr8125592oiw.263.1543853330109; Mon, 03 Dec 2018 08:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:39 -0600 Message-Id: <20181203160840.15115-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH for-4.0 4/5] tcg/i386: Precompute all guest_base parameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These values are constant between all qemu_ld/st invocations; there is no need to figure this out each time. If we cannot use a segment or an offset directly for guest_base, load the value into a register in the prologue. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 101 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 853c3c8465..b8d2dd5ba3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1854,22 +1854,31 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_out_push(s, retaddr); tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); } -#elif defined(__x86_64__) && defined(__linux__) -# include -# include - +#elif TCG_TARGET_REG_BITS =3D=3D 32 +# define x86_guest_base_seg 0 +# define x86_guest_base_index -1 +# define x86_guest_base_offset guest_base +#else +static int x86_guest_base_seg; +static int x86_guest_base_index =3D -1; +static int32_t x86_guest_base_offset; +# if defined(__x86_64__) && defined(__linux__) +# include +# include int arch_prctl(int code, unsigned long addr); - -static int guest_base_flags; -static inline void setup_guest_base_seg(void) +static inline int setup_guest_base_seg(void) { if (arch_prctl(ARCH_SET_GS, guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + return P_GS; } + return 0; } -#else -# define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +# else +static inline int setup_guest_base_seg(void) +{ + return 0; +} +# endif #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2008,27 +2017,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset =3D guest_base; - int index =3D -1; - int seg =3D 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base =3D=3D 0 || guest_base_flags) { - seg =3D guest_base_flags; - offset =3D 0; - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } - - tcg_out_qemu_ld_direct(s, datalo, datahi, - addrlo, index, offset, seg, is64, opc); - } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, + is64, opc); #endif } =20 @@ -2144,28 +2135,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset =3D guest_base; - int index =3D -1; - int seg =3D 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base =3D=3D 0 || guest_base_flags) { - seg =3D guest_base_flags; - offset =3D 0; - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { - /* ??? Note that we require L0 free for bswap. */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } - - tcg_out_qemu_st_direct(s, datalo, datahi, - addrlo, index, offset, seg, opc); - } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, opc); #endif } =20 @@ -3412,6 +3383,21 @@ static void tcg_target_qemu_prologue(TCGContext *s) (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else +# ifndef CONFIG_SOFTMMU + if (guest_base) { + int seg =3D setup_guest_base_seg(); + if (seg !=3D 0) { + x86_guest_base_seg =3D seg; + } else if (guest_base =3D=3D (int32_t)guest_base) { + x86_guest_base_offset =3D guest_base; + } else { + /* Choose R12 because, as a base, it requires a SIB byte. */ + x86_guest_base_index =3D TCG_REG_R12; + tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + } + } +# endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ @@ -3437,13 +3423,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_pop(s, tcg_target_callee_save_regs[i]); } tcg_out_opc(s, OPC_RET, 0, 0, 0); - -#if !defined(CONFIG_SOFTMMU) - /* Try to set up a segment register to point to guest_base. */ - if (guest_base) { - setup_guest_base_seg(); - } -#endif } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.17.2