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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OX2SVM+SGv9AntTuQIyBfb8LvK9XD54FYkUpBz/1FwI=; b=UZwmU/VsDTAHnQakdVj/S0ZavA2NyBJpuv1S8MLSkm/EifO7FZngI8cptMkNEv1xv9 5/dy08FViTHw6vJ4keNSIltAHKZUgKEqdk9FuBEaNJPLEi/mbZypIEpGCeEiJ8IlO6Xj fI0utNLIZSvptcmgbUYBTxP0k2ZE+DjXTXEyo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OX2SVM+SGv9AntTuQIyBfb8LvK9XD54FYkUpBz/1FwI=; b=ZQq25B5OfDRegk70feJPiGrq2A9N73L623ODSAGQgVM9KZ/byKKUng/NXgrPxYILhC Ru/OhsUP+NVoZ7XHBZP/f9OxJECJeJMSGO8MVSaIN24VnoWiWnagfARW8nSSWw/dgGNj aJD6L5ZpPeQAY4cNMOWyx+nPVi+ytq1TKp07CTXodwWx9mZ4KgIynpvQWKHddQt2w5Za sjfeiAm9J37TJtBMTM0XDiHa2/siXhhZlnHK804GQavWHEKZB5lhHMBFu2V2RyCVD9pC uF2kQddYW16oWSZ697tVZROllRzV/juj+D0tPhnCbNWbxGeXaUG4RQ7G+Miqpo5HdOGi En4g== X-Gm-Message-State: AA+aEWbcnnpc2fwVFydK95EKbBP8i/E43n30hdXlyw6y75sY8t0s9YGb OiAo+HuA8AaDnJCsF/lXTsh+ZLOBR69K2A== X-Google-Smtp-Source: AFSGD/WunM0U70zxyEJAJfF5vqn6pZh2KVSgYjNBZdGpQXO/DVvqNGTaUIk/bjM7EdCq0Sr+h/ajSA== X-Received: by 2002:a9d:6a50:: with SMTP id h16mr9740617otn.95.1543853328544; Mon, 03 Dec 2018 08:08:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:38 -0600 Message-Id: <20181203160840.15115-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 3/5] tcg/i386: Assume 32-bit values are zero-extended X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We now have an invariant that all TCG_TYPE_I32 values are zero-extended, which means that we do not need to extend them again during qemu_ld/st, either explicitly via a separate tcg_out_ext32u or implicitly via P_ADDR32. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 103 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 63 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ab31dfa66d..853c3c8465 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -309,13 +309,11 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define P_ADDR32 0x800 /* 0x67 opcode prefix */ # define P_REXW 0x1000 /* Set REX.W =3D 1 */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ #else -# define P_ADDR32 0 # define P_REXW 0 # define P_REXB_R 0 # define P_REXB_RM 0 @@ -528,9 +526,6 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, = int rm, int x) tcg_debug_assert((opc & P_REXW) =3D=3D 0); tcg_out8(s, 0x66); } - if (opc & P_ADDR32) { - tcg_out8(s, 0x67); - } if (opc & P_SIMDF3) { tcg_out8(s, 0xf3); } else if (opc & P_SIMDF2) { @@ -1659,11 +1654,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, T= CGReg addrlo, TCGReg addrhi, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0); =20 /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. There are two cases worth note: - For 32-bit guest and x86_64 host, MOVL zero-extends the guest addre= ss - before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ - copies the entire guest address for the slow path, while truncation - for the 32-bit host happens with the fastpath ADDL below. */ + path function argument setup. */ tcg_out_mov(s, ttype, r1, addrlo); =20 /* jne slow_path */ @@ -2019,41 +2010,31 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) #else { int32_t offset =3D guest_base; - TCGReg base =3D addrlo; int index =3D -1; int seg =3D 0; =20 - /* For a 32-bit guest, the high 32 bits may contain garbage. - We can do this with the ADDR32 prefix if we're not using - a guest base, or when using segmentation. Otherwise we - need to zero-extend manually. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base =3D=3D 0 || guest_base_flags) { seg =3D guest_base_flags; offset =3D 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |=3D P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - if (offset !=3D guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } + } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index =3D TCG_REG_L1; + offset =3D 0; } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, is64, opc); + addrlo, index, offset, seg, is64, opc); } #endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, intptr_t ofs, int seg, - TCGMemOp memop) + TCGReg base, int index, intptr_t ofs, + int seg, TCGMemOp memop) { /* ??? Ideally we wouldn't need a scratch register. For user-only, we could perform the bswap twice to restore the original value @@ -2077,8 +2058,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo =3D scratch; } - tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, + datalo, base, index, 0, ofs); break; case MO_16: if (bswap) { @@ -2086,7 +2067,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_rolw_8(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, + base, index, 0, ofs); break; case MO_32: if (bswap) { @@ -2094,7 +2076,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_bswap32(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { @@ -2103,22 +2085,27 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, tcg_out_bswap64(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, of= s); + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, + base, index, 0, ofs); } else if (bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs); tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s+4); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs + 4); } else { if (real_bswap) { int t =3D datalo; datalo =3D datahi; datahi =3D t; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); - tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs+4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); } break; default: @@ -2151,7 +2138,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, @@ -2159,35 +2146,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) #else { int32_t offset =3D guest_base; - TCGReg base =3D addrlo; + int index =3D -1; int seg =3D 0; =20 - /* See comment in tcg_out_qemu_ld re zero-extension of addrlo. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base =3D=3D 0 || guest_base_flags) { seg =3D guest_base_flags; offset =3D 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |=3D P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset !=3D guest_base) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base =3D TCG_REG_L1; - offset =3D 0; - } else if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base =3D TCG_REG_L1; - } + } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { + /* ??? Note that we require L0 free for bswap. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index =3D TCG_REG_L1; + offset =3D 0; } =20 - tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, + addrlo, index, offset, seg, opc); } #endif } --=20 2.17.2