From nobody Wed Jun 26 05:45:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154385680418816.622143039534876; Mon, 3 Dec 2018 09:06:44 -0800 (PST) Received: from localhost ([::1]:50703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrg8-0007Ro-BR for importer@patchew.org; Mon, 03 Dec 2018 12:06:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTqm8-0001ZO-CN for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTqm6-0003Ni-QE for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:48 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:46648) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTqm6-0003NT-Lq for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:46 -0500 Received: by mail-oi1-x244.google.com with SMTP id x202so11327176oif.13 for ; Mon, 03 Dec 2018 08:08:46 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bcz+HCUhPqRxfn13yNCbaWu/SKDHzkxNnSaGXMB7UVk=; b=WUueTVhm+r984tBpA1SoBA8wsMj2uCBM+iy/dDkB+AnYPk+mK0iduwjQcr7+MHMBE1 WneGinymIQhRgiaXeKy1NF1tehjRkJ1UFKb8Y4pVFRc/1dMZSWw853E2RoFfh3GCt4mD IaRrbNoEG8sQQts4uGcdHmjJ1UMSbgFGPkkHs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bcz+HCUhPqRxfn13yNCbaWu/SKDHzkxNnSaGXMB7UVk=; b=uBgQVvN6ZjSVg+WBZtOzYrUzlgsg3KtWN+j75O6IT6H3qYnxksYAz3r4l7WcNLAciy dN3Bx/8/6fopiViyEUuBzHSbIFXCeflKtPevKfEab2RH0bb0LZSKRCs9olXck7lzC39P WMosxCYarh18bKa/WdXEfAtXqsBtoruDCFiQCU7QeIc9LnoxruMezKe3XsjhpYsJmlSM xUaYJo2bapazys4y2X4Ipl3EF9sA7ePORKJSXOjQ2g+/7A6q6OatSNyolzU4TNj0o+mL 9j4BvwqVWOOd5bK2XjkKncZ5ZWlhhhDHt8nmB5kIHLERGL4bChUd4tIVztl49ysd15ve ia3Q== X-Gm-Message-State: AA+aEWZupLAdNf0Dngmy/xerrSDyh3M739/X3z3JwXOqJIxHZiCAYc5Q nPP0PORHyZWS9sinhnVTAKSbJrUzrmO7Lg== X-Google-Smtp-Source: AFSGD/U9MtoWcjtKqBawZcVMHPfFBLIwUxRRES1bpXlu7eF4IxZE4/QcVgGaKNGyYaKYJcC0YuoAPg== X-Received: by 2002:aca:b7c2:: with SMTP id h185mr10592314oif.298.1543853325578; Mon, 03 Dec 2018 08:08:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:36 -0600 Message-Id: <20181203160840.15115-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH for-4.0 1/5] tcg/i386: Propagate is64 to tcg_out_qemu_ld_direct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This helps preserve the invariant that all TCG_TYPE_I32 values are stored zero-extended in the 64-bit host registers. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 28192f4608..6bf4f84b20 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1883,10 +1883,11 @@ static inline void setup_guest_base_seg(void) { } =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) + int seg, bool is64, TCGMemOp memop) { const TCGMemOp real_bswap =3D memop & MO_BSWAP; TCGMemOp bswap =3D real_bswap; + int rexw =3D is64 * P_REXW; int movop =3D OPC_MOVL_GvEv; =20 if (have_movbe && real_bswap) { @@ -1900,7 +1901,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, base, index, 0, ofs); break; case MO_UW: @@ -1920,9 +1921,9 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, base, index, 0, ofs); tcg_out_rolw_8(s, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo); + tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); } break; @@ -2010,7 +2011,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, = opc); =20 /* Record the current context of a load into ldst label */ add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, @@ -2045,7 +2046,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, opc); + base, index, offset, seg, is64, opc); } #endif } --=20 2.17.2 From nobody Wed Jun 26 05:45:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543855887420632.8761143227741; Mon, 3 Dec 2018 08:51:27 -0800 (PST) Received: from localhost ([::1]:50608 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrRH-0006je-9U for importer@patchew.org; Mon, 03 Dec 2018 11:51:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTqm9-0001Zz-0Y for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTqm8-0003Os-9U for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:48 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:38576) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTqm8-0003OY-4m for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:48 -0500 Received: by mail-oi1-x243.google.com with SMTP id a77so11361978oii.5 for ; Mon, 03 Dec 2018 08:08:48 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VGbbvWUE6rnQSaltbq2Rb0A4jW/k/dy2fVEq4xZiX2I=; b=QC0MTw72j4UIvJOPKZdj2SARIJHQFMUC/Dtl6bcFQa4kHCx3TTOHLGQnSPgwxmvpFV SJp5+fT1V3NF44WY84bivWNLm0ldVVxpOgfrMzZ1LhDPUYRf79LK36/1jSWpimswmwv+ kwxr9THiJIPnBxlwv/D4IQFCOdd+stjQJ/Og8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VGbbvWUE6rnQSaltbq2Rb0A4jW/k/dy2fVEq4xZiX2I=; b=pDWH49F87bSgySfOToJuGnWGrRqD/MD0tJWteRT8lbyKHxnu4BfYLuOiVx0mQ8xErx XqQwDnkvxbLSzV0wq1+y/S/UVXwrtosMP+uXsjk2+oNRoln6jdN2mS8/v0pCEwDEeAFb DeS6J/KSBjQihrb1Iry+t3Kam7Z+/YCw4nWoi/Ykla1VHyZEYYT+M4tQUyhjUN0BDFNm ++fn43UROvtbGZBIfWhASINCDq82qipxMuqLI4dsW+TPNDNb1CxUwZ2n4T3oxHqniJok Aeagl8pBt3OVkNIq/YjoZPtkYP1k3IM7FkPVOUwx4pxY61YPTc49PKsQCLqnvYkv+n05 Hsig== X-Gm-Message-State: AA+aEWZkXPk8Has0l1iJhU2KcJzA46qf8TZQ9pi4uRAoi1TNc3BkmK8k HuoIJfyXbrTVLM7jkIODOojyYSxgxGnCFA== X-Google-Smtp-Source: AFSGD/VfNw6ID0yN9ZzIFVQpp2YHliMWPZFfIDpnxpkSm+STA4HHyyrDNScRZRgJqJkLCOmM5vbaUw== X-Received: by 2002:aca:4ace:: with SMTP id x197mr10677583oia.129.1543853327133; Mon, 03 Dec 2018 08:08:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:37 -0600 Message-Id: <20181203160840.15115-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH for-4.0 2/5] tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This preserves the invariant that all TCG_TYPE_I32 values are zero-extended in the 64-bit host register. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.h | 5 +++-- tcg/i386/tcg-target.inc.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..c523d5f5e1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -135,8 +135,9 @@ extern bool have_avx2; #define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -#define TCG_TARGET_HAS_extrl_i64_i32 0 -#define TCG_TARGET_HAS_extrh_i64_i32 0 +/* Keep target addresses zero-extended in a register. */ +#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS =3D=3D 32) +#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS =3D=3D 32) #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6bf4f84b20..ab31dfa66d 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2546,12 +2546,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: + case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_ext32s(s, a0, a1); break; + case INDEX_op_extrh_i64_i32: + tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); + break; #endif =20 OP_32_64(deposit): @@ -2915,6 +2919,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_neg_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extrh_i64_i32: return &r_0; =20 case INDEX_op_ext8s_i32: @@ -2930,6 +2935,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: case INDEX_op_extract_i32: case INDEX_op_extract_i64: case INDEX_op_sextract_i32: --=20 2.17.2 From nobody Wed Jun 26 05:45:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543855984949763.2223622581982; Mon, 3 Dec 2018 08:53:04 -0800 (PST) Received: from localhost ([::1]:50614 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrSx-00012u-Pg for importer@patchew.org; Mon, 03 Dec 2018 11:53:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTqmB-0001cJ-Dz for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTqmA-0003QR-25 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:51 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:37643) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTqm9-0003Py-SA for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:50 -0500 Received: by mail-ot1-x344.google.com with SMTP id 40so12081959oth.4 for ; Mon, 03 Dec 2018 08:08:49 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OX2SVM+SGv9AntTuQIyBfb8LvK9XD54FYkUpBz/1FwI=; b=UZwmU/VsDTAHnQakdVj/S0ZavA2NyBJpuv1S8MLSkm/EifO7FZngI8cptMkNEv1xv9 5/dy08FViTHw6vJ4keNSIltAHKZUgKEqdk9FuBEaNJPLEi/mbZypIEpGCeEiJ8IlO6Xj fI0utNLIZSvptcmgbUYBTxP0k2ZE+DjXTXEyo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OX2SVM+SGv9AntTuQIyBfb8LvK9XD54FYkUpBz/1FwI=; b=ZQq25B5OfDRegk70feJPiGrq2A9N73L623ODSAGQgVM9KZ/byKKUng/NXgrPxYILhC Ru/OhsUP+NVoZ7XHBZP/f9OxJECJeJMSGO8MVSaIN24VnoWiWnagfARW8nSSWw/dgGNj aJD6L5ZpPeQAY4cNMOWyx+nPVi+ytq1TKp07CTXodwWx9mZ4KgIynpvQWKHddQt2w5Za sjfeiAm9J37TJtBMTM0XDiHa2/siXhhZlnHK804GQavWHEKZB5lhHMBFu2V2RyCVD9pC uF2kQddYW16oWSZ697tVZROllRzV/juj+D0tPhnCbNWbxGeXaUG4RQ7G+Miqpo5HdOGi En4g== X-Gm-Message-State: AA+aEWbcnnpc2fwVFydK95EKbBP8i/E43n30hdXlyw6y75sY8t0s9YGb OiAo+HuA8AaDnJCsF/lXTsh+ZLOBR69K2A== X-Google-Smtp-Source: AFSGD/WunM0U70zxyEJAJfF5vqn6pZh2KVSgYjNBZdGpQXO/DVvqNGTaUIk/bjM7EdCq0Sr+h/ajSA== X-Received: by 2002:a9d:6a50:: with SMTP id h16mr9740617otn.95.1543853328544; Mon, 03 Dec 2018 08:08:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:38 -0600 Message-Id: <20181203160840.15115-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 3/5] tcg/i386: Assume 32-bit values are zero-extended X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We now have an invariant that all TCG_TYPE_I32 values are zero-extended, which means that we do not need to extend them again during qemu_ld/st, either explicitly via a separate tcg_out_ext32u or implicitly via P_ADDR32. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 103 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 63 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ab31dfa66d..853c3c8465 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -309,13 +309,11 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define P_ADDR32 0x800 /* 0x67 opcode prefix */ # define P_REXW 0x1000 /* Set REX.W =3D 1 */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ #else -# define P_ADDR32 0 # define P_REXW 0 # define P_REXB_R 0 # define P_REXB_RM 0 @@ -528,9 +526,6 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, = int rm, int x) tcg_debug_assert((opc & P_REXW) =3D=3D 0); tcg_out8(s, 0x66); } - if (opc & P_ADDR32) { - tcg_out8(s, 0x67); - } if (opc & P_SIMDF3) { tcg_out8(s, 0xf3); } else if (opc & P_SIMDF2) { @@ -1659,11 +1654,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, T= CGReg addrlo, TCGReg addrhi, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0); =20 /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. There are two cases worth note: - For 32-bit guest and x86_64 host, MOVL zero-extends the guest addre= ss - before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ - copies the entire guest address for the slow path, while truncation - for the 32-bit host happens with the fastpath ADDL below. */ + path function argument setup. */ tcg_out_mov(s, ttype, r1, addrlo); =20 /* jne slow_path */ @@ -2019,41 +2010,31 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) #else { int32_t offset =3D guest_base; - TCGReg base =3D addrlo; int index =3D -1; int seg =3D 0; =20 - /* For a 32-bit guest, the high 32 bits may contain garbage. - We can do this with the ADDR32 prefix if we're not using - a guest base, or when using segmentation. Otherwise we - need to zero-extend manually. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base =3D=3D 0 || guest_base_flags) { seg =3D guest_base_flags; offset =3D 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |=3D P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - if (offset !=3D guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } + } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index =3D TCG_REG_L1; + offset =3D 0; } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, is64, opc); + addrlo, index, offset, seg, is64, opc); } #endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, intptr_t ofs, int seg, - TCGMemOp memop) + TCGReg base, int index, intptr_t ofs, + int seg, TCGMemOp memop) { /* ??? Ideally we wouldn't need a scratch register. For user-only, we could perform the bswap twice to restore the original value @@ -2077,8 +2058,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo =3D scratch; } - tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, + datalo, base, index, 0, ofs); break; case MO_16: if (bswap) { @@ -2086,7 +2067,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_rolw_8(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, + base, index, 0, ofs); break; case MO_32: if (bswap) { @@ -2094,7 +2076,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_bswap32(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { @@ -2103,22 +2085,27 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, tcg_out_bswap64(s, scratch); datalo =3D scratch; } - tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, of= s); + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, + base, index, 0, ofs); } else if (bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs); tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s+4); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs + 4); } else { if (real_bswap) { int t =3D datalo; datalo =3D datahi; datahi =3D t; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); - tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs+4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); } break; default: @@ -2151,7 +2138,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, @@ -2159,35 +2146,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) #else { int32_t offset =3D guest_base; - TCGReg base =3D addrlo; + int index =3D -1; int seg =3D 0; =20 - /* See comment in tcg_out_qemu_ld re zero-extension of addrlo. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base =3D=3D 0 || guest_base_flags) { seg =3D guest_base_flags; offset =3D 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |=3D P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset !=3D guest_base) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base =3D TCG_REG_L1; - offset =3D 0; - } else if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base =3D TCG_REG_L1; - } + } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { + /* ??? Note that we require L0 free for bswap. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index =3D TCG_REG_L1; + offset =3D 0; } =20 - tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, + addrlo, index, offset, seg, opc); } #endif } --=20 2.17.2 From nobody Wed Jun 26 05:45:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 154385699021012.60726297841336; Mon, 3 Dec 2018 09:09:50 -0800 (PST) Received: from localhost ([::1]:50715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrj5-0003hN-Pj for importer@patchew.org; Mon, 03 Dec 2018 12:09:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTqmD-0001ej-Hl for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTqmB-0003RO-9o for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:53 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:37521) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTqmB-0003R6-5Q for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:51 -0500 Received: by mail-oi1-x242.google.com with SMTP id y23so11385676oia.4 for ; Mon, 03 Dec 2018 08:08:51 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a2J3CQI2OQ70TK1sm7OIeOp1575wsiXhLstcSeE4Wk8=; b=RRRN/YhDO3xLLAirlaFPndlR69RzIpsD5BDuzQk3U2kS7xpkuK3E5WWrmuuoaWG3Vr 7xBT3uZXT+5Owxs8xMFGe1bsmngSWJ/lyV5QipPF9ksoo6rn4FdVH6c3wrqm0nh72mUC rlyH7hqBVFh1giJfXKXlg7aqhG0EM0wwz50sA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a2J3CQI2OQ70TK1sm7OIeOp1575wsiXhLstcSeE4Wk8=; b=X9Hy6zsmhJ0Ef0zUA+Blr6aYHmKqbpfMEulhVAhC1Lsy4wnvx+pPzjStbudt/448WA aOVFNAJUJTMiw1LHTJasKYjs8zuahh/mdsBLQzC5clfXBGFaGMieJsdHBmZl+dsQMYxt th21Y7Eq7YwIF/xLgXeqjpTI558KrrtFOq0CxmaTnfRosDjqonVm2/V/kjHxevxeK/Wb z0YfEkWH3IAmN4USXeQDxtPhDtxGYzNRpgZE3RwIG+dMTkDdtOhHX6CBjpx3CJ6XXWhu LDIzJmTP+MbMSmVYqq1ivf0Msf/QLiUAM+QLNyMm1DQ/tkGW33wjxViv11AlSb9VPFSv BSZg== X-Gm-Message-State: AA+aEWaDPPZh4m9MIuypEY3R31BA6UhCYtWSIqBxzSJkMb8BAQb7n4Zl r/RFspZhPskRJms4yPEgM2BxP4GC/no0AQ== X-Google-Smtp-Source: AFSGD/Upb+/cd1Q09U6di5MHTSSlYadj9VeNXLrQC+9/Svf25idy3fUKoS/UCvYmdCq7Rj/UXO27FQ== X-Received: by 2002:a54:440d:: with SMTP id k13mr8125592oiw.263.1543853330109; Mon, 03 Dec 2018 08:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:39 -0600 Message-Id: <20181203160840.15115-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH for-4.0 4/5] tcg/i386: Precompute all guest_base parameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These values are constant between all qemu_ld/st invocations; there is no need to figure this out each time. If we cannot use a segment or an offset directly for guest_base, load the value into a register in the prologue. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 101 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 853c3c8465..b8d2dd5ba3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1854,22 +1854,31 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_out_push(s, retaddr); tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); } -#elif defined(__x86_64__) && defined(__linux__) -# include -# include - +#elif TCG_TARGET_REG_BITS =3D=3D 32 +# define x86_guest_base_seg 0 +# define x86_guest_base_index -1 +# define x86_guest_base_offset guest_base +#else +static int x86_guest_base_seg; +static int x86_guest_base_index =3D -1; +static int32_t x86_guest_base_offset; +# if defined(__x86_64__) && defined(__linux__) +# include +# include int arch_prctl(int code, unsigned long addr); - -static int guest_base_flags; -static inline void setup_guest_base_seg(void) +static inline int setup_guest_base_seg(void) { if (arch_prctl(ARCH_SET_GS, guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + return P_GS; } + return 0; } -#else -# define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +# else +static inline int setup_guest_base_seg(void) +{ + return 0; +} +# endif #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2008,27 +2017,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset =3D guest_base; - int index =3D -1; - int seg =3D 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base =3D=3D 0 || guest_base_flags) { - seg =3D guest_base_flags; - offset =3D 0; - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } - - tcg_out_qemu_ld_direct(s, datalo, datahi, - addrlo, index, offset, seg, is64, opc); - } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, + is64, opc); #endif } =20 @@ -2144,28 +2135,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset =3D guest_base; - int index =3D -1; - int seg =3D 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base =3D=3D 0 || guest_base_flags) { - seg =3D guest_base_flags; - offset =3D 0; - } else if (TCG_TARGET_REG_BITS =3D=3D 64 && offset !=3D guest_base= ) { - /* ??? Note that we require L0 free for bswap. */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } - - tcg_out_qemu_st_direct(s, datalo, datahi, - addrlo, index, offset, seg, opc); - } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, opc); #endif } =20 @@ -3412,6 +3383,21 @@ static void tcg_target_qemu_prologue(TCGContext *s) (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else +# ifndef CONFIG_SOFTMMU + if (guest_base) { + int seg =3D setup_guest_base_seg(); + if (seg !=3D 0) { + x86_guest_base_seg =3D seg; + } else if (guest_base =3D=3D (int32_t)guest_base) { + x86_guest_base_offset =3D guest_base; + } else { + /* Choose R12 because, as a base, it requires a SIB byte. */ + x86_guest_base_index =3D TCG_REG_R12; + tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + } + } +# endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ @@ -3437,13 +3423,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_pop(s, tcg_target_callee_save_regs[i]); } tcg_out_opc(s, OPC_RET, 0, 0, 0); - -#if !defined(CONFIG_SOFTMMU) - /* Try to set up a segment register to point to guest_base. */ - if (guest_base) { - setup_guest_base_seg(); - } -#endif } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.17.2 From nobody Wed Jun 26 05:45:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543856162597586.0538427922951; Mon, 3 Dec 2018 08:56:02 -0800 (PST) Received: from localhost ([::1]:50633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTrVp-00054a-Dr for importer@patchew.org; Mon, 03 Dec 2018 11:56:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTqmJ-0001hG-7S for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTqmF-0003U8-9P for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:58 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:46649) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTqmD-0003S7-Gg for qemu-devel@nongnu.org; Mon, 03 Dec 2018 11:08:53 -0500 Received: by mail-oi1-x243.google.com with SMTP id x202so11327537oif.13 for ; Mon, 03 Dec 2018 08:08:52 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F6DluLGLSO9afKjowSYnD+gDl6Isk/WNzD0i4/fr9zg=; b=dHOypX6v7HLh5osTjABQXz0ozWSV27looFOFXIJM9lfOmtQ4f5a5OmuLHLOnTcSRlM HznA8tc1QnClhR71kSUGKsnpGgPZkCVeR/nJmDBynrOmV06GObsrVII73wVpXhgdV7ra YDKuP3CibWrR8BpG/zhg1AfnftwdEDsT+AqkA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F6DluLGLSO9afKjowSYnD+gDl6Isk/WNzD0i4/fr9zg=; b=eId4IBbolMdDLMftA33XplAQSakXd+6RkizF0OHilNqCt7XAffzWcoQUHtNwT5VhH1 jpdDcguz+95yz5KDWcm5sHl/GTRNNlYPnJYwF3ka2yeIXwWuKTsa/lppmKoldBk4oGGv zY3drQ7XuSGptQOzOWulWSdkmak8/OeR1UJLrb9ehOiA+VwBtlzjpoL0gR/4BJfpu9xQ l3wVH/JSP85tvmYr+p93nNhLDUYa2xa2SFj2qNjwu/dNZSbYDVvlJU3p23QZ13HgIyFm b2hm9WGwXoo5Ey7VlMKkQtl2iT1v33lqMrCvYElGt/5A3AJbH9t7gQ8fFTyC8/ryqpAc a9vQ== X-Gm-Message-State: AA+aEWY2UJ66sTI+T117ikmncNSRdZVdPPHZNA1JcN9r59OrFlc5usMm 1JYSTWGOAkbZ528PX+0lzVmGjonbX24L5A== X-Google-Smtp-Source: AFSGD/WfwQy4tUIEfKFGlja9/jVLkbGCxHOlQRxRrJRj8DtlpQ8FdGPhcqNhJfAMq5+uWUrGANCRUQ== X-Received: by 2002:aca:48d1:: with SMTP id v200mr10616280oia.69.1543853331583; Mon, 03 Dec 2018 08:08:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:40 -0600 Message-Id: <20181203160840.15115-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH for-4.0 5/5] tcg/i386: Add setup_guest_base_seg for FreeBSD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index b8d2dd5ba3..3a39b51685 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1873,6 +1873,15 @@ static inline int setup_guest_base_seg(void) } return 0; } +# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) +# include +static inline int setup_guest_base_seg(void) +{ + if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { + return P_GS; + } + return 0; +} # else static inline int setup_guest_base_seg(void) { --=20 2.17.2