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[97.113.170.180]) by smtp.gmail.com with ESMTPSA id 19sm8569336pfs.108.2018.11.27.21.38.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Nov 2018 21:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IP0lLIkXSgPKwsDsoLUp8fVauLPqwdeD0c88AkY4Qpw=; b=ji/hY/kOjrrTE8vBuCS3aTph+n89QXAdvHZzkCdK5zv0vVA8E79VXk1UaCNjWcJTrs 47vJnjv+OPXIEBAY9/sK5NHX+0JwL6B88wUH/t38G/GJUG9P1a+L8svl33ljZdy7ZbCZ 0T1Y96ZxeXeaX58tPrQg+YRq+aP1LEvpSUbw4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IP0lLIkXSgPKwsDsoLUp8fVauLPqwdeD0c88AkY4Qpw=; b=rwI0PhoS6q4MJNIPJ1keFBSnLD5GlRGCKy1kkvmZ/TRG7Tv/cIthGD5/dWe0kTlGgM WXAKn4YrQD5XmuigT3h4fpcJWUaNKPcUIST3Iq/4sEVVi5gqBgDGGr1wwe6T/jtYHNQE NtZZBqTDYK/0GnWzYBLS103afFxnDISJ51iZMgE7MCkXN3g82BM7HT1De+uKQW8jh9ba 31Nd3c02zAnjSaAfRV7qBxIosXzjoquzyMVjxmE0PqPdx2t7NBBXWKw/kf2uT78EbLDM aLTs9rS5HUnzP3VUbvE4RQtSiTRJ2GC3Qt2BaRpzkHuV6HwIvv9bQB+jbx0ksyV8M82a R//Q== X-Gm-Message-State: AA+aEWYs8csB7a1qGFp3f4kw8yN2X174mhwsYlVHuWXdSPMBZLb8V/v8 iwqkzqdfLgDamG5RE+yS7iDPXemdKB4= X-Google-Smtp-Source: AFSGD/WyxuEjN1e0Rb9lx6p7J5vhrZD1lm70Axn0VheFjO9s6QrmYBmuip2mA/dCNV8iPZB2XFomwA== X-Received: by 2002:a63:88c7:: with SMTP id l190mr31308104pgd.110.1543383523760; Tue, 27 Nov 2018 21:38:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 27 Nov 2018 21:38:28 -0800 Message-Id: <20181128053834.10861-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181128053834.10861-1-richard.henderson@linaro.org> References: <20181128053834.10861-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 06/12] tcg: Improve register allocation for matching constraints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Try harder to honor the output_pref. When we're forced to allocate a second register for the input, it does not need to use the input constraint; that will be honored by the register we allocate for the output and a move is already required. Signed-off-by: Richard Henderson --- tcg/tcg.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f86415ce29..adf6570c36 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3235,6 +3235,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) =20 /* satisfy input constraints */=20 for (k =3D 0; k < nb_iargs; k++) { + TCGRegSet i_preferred_regs, o_preferred_regs; + i =3D def->sorted_args[nb_oargs + k]; arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; @@ -3245,17 +3247,18 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) /* constant is OK for instruction */ const_args[i] =3D 1; new_args[i] =3D ts->val; - goto iarg_end; + continue; } =20 - temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, 0); - + i_preferred_regs =3D o_preferred_regs =3D 0; if (arg_ct->ct & TCG_CT_IALIAS) { + o_preferred_regs =3D op->output_pref[arg_ct->alias_index]; if (ts->fixed_reg) { /* if fixed register, we must allocate a new register if the alias is not the same register */ - if (arg !=3D op->args[arg_ct->alias_index]) + if (arg !=3D op->args[arg_ct->alias_index]) { goto allocate_in_reg; + } } else { /* if the input is aliased to an output and if it is not dead after the instruction, we must allocate @@ -3263,33 +3266,42 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) if (!IS_DEAD_ARG(i)) { goto allocate_in_reg; } + /* check if the current register has already been allocated for another input aliased to an output */ - int k2, i2; - for (k2 =3D 0 ; k2 < k ; k2++) { - i2 =3D def->sorted_args[nb_oargs + k2]; - if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && - (new_args[i2] =3D=3D ts->reg)) { - goto allocate_in_reg; + if (ts->val_type =3D=3D TEMP_VAL_REG) { + int k2, i2; + reg =3D ts->reg; + for (k2 =3D 0 ; k2 < k ; k2++) { + i2 =3D def->sorted_args[nb_oargs + k2]; + if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && + reg =3D=3D new_args[i2]) { + goto allocate_in_reg; + } } } + i_preferred_regs =3D o_preferred_regs; } } + + temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_reg= s); reg =3D ts->reg; + if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { /* nothing to do : the constraint is satisfied */ } else { allocate_in_reg: /* allocate a new register matching the constraint=20 and move the temporary register into it */ + temp_load(s, ts, tcg_target_available_regs[ts->type], + i_allocated_regs, 0); reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, - 0, ts->indirect_base); + o_preferred_regs, ts->indirect_base); tcg_out_mov(s, ts->type, reg, ts->reg); } new_args[i] =3D reg; const_args[i] =3D 0; tcg_regset_set_reg(i_allocated_regs, reg); - iarg_end: ; } =20 /* mark dead temporaries and free the associated registers */ --=20 2.17.2