From nobody Mon Feb 9 21:20:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543104407776207.55248766300667; Sat, 24 Nov 2018 16:06:47 -0800 (PST) Received: from localhost ([::1]:58197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQhwa-0003yy-TJ for importer@patchew.org; Sat, 24 Nov 2018 19:06:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQhmj-0003R1-Ay for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQhme-0006e7-AO for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:25 -0500 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]:41825) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gQhme-0005Fk-2M for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:20 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id D5D52D07; Sat, 24 Nov 2018 18:56:02 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 24 Nov 2018 18:56:03 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 24348102F6; Sat, 24 Nov 2018 18:56:02 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=T4FwrcWf3Wmcy54O5ul5f0vvX2rbgYUG90TdgAQvhrk=; b=OsWD2 Rf8IAwS6DWw+6qwMvZhoLcbZQttRrFeD7YqzczY49pb8JXho9bZEG26W6aFvICPi zG5e6ck+RdbadUw0QknsbdxRMrjk9UsLA8n+drqae2ylPAVFTfHL16vzR6J+YDRa 7SQyCbmBIxFipg9+MlSo58rmIvZU2hap2/2EcA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=T4FwrcWf3Wmcy54O5ul5f0vvX2rbg YUG90TdgAQvhrk=; b=V+1bTqRYnamXQ9alA+/ur0fIflYQwYWbJatN8F8Yu0hBI l36u/CHVB2jIDboAZDgdjhqg7phT3vJFz8r27L1XUfAW0924X6njdldOjz8iCPRw fA2PrtXI3YnRpfe02baABYB6J0K++8Zd+Z35t53xAq4LFEouhOLxlz5qP5xRtBAv VWIvZ+ggH6MaKdcl2bxEajYQTthX5BjUlXL716dIGoKuki72bZKwad87zXkbBwfU +o8WwnW1X33n8pVXULnAp50M0vdq8Jfrf/S79pvu/Qfc4Q4Aod49G9pENlGNSTdj xDCcZb+1Gx5J3MlGCRyzhpxJDapzlotBYC7Yu47RA== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 24 Nov 2018 18:55:48 -0500 Message-Id: <20181124235553.17371-9-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181124235553.17371-1-cota@braap.org> References: <20181124235553.17371-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.25 Subject: [Qemu-devel] [PATCH v6 08/13] hardfloat: implement float32/64 addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Performance results (single and double precision) for fp-bench: 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz - before: add-single: 135.07 MFlops add-double: 131.60 MFlops sub-single: 130.04 MFlops sub-double: 133.01 MFlops - after: add-single: 443.04 MFlops add-double: 301.95 MFlops sub-single: 411.36 MFlops sub-double: 293.15 MFlops 2. ARM Aarch64 A57 @ 2.4GHz - before: add-single: 44.79 MFlops add-double: 49.20 MFlops sub-single: 44.55 MFlops sub-double: 49.06 MFlops - after: add-single: 93.28 MFlops add-double: 88.27 MFlops sub-single: 91.47 MFlops sub-double: 88.27 MFlops 3. IBM POWER8E @ 2.1 GHz - before: add-single: 72.59 MFlops add-double: 72.27 MFlops sub-single: 75.33 MFlops sub-double: 70.54 MFlops - after: add-single: 112.95 MFlops add-double: 201.11 MFlops sub-single: 116.80 MFlops sub-double: 188.72 MFlops Note that the IBM and ARM machines benefit from having HARDFLOAT_2F{32,64}_USE_FP set to 0. Otherwise their performance can suffer significantly: - IBM Power8: add-single: [1] 54.94 vs [0] 116.37 MFlops add-double: [1] 58.92 vs [0] 201.44 MFlops - Aarch64 A57: add-single: [1] 80.72 vs [0] 93.24 MFlops add-double: [1] 82.10 vs [0] 88.18 MFlops On the Intel machine, having 2F64 set to 1 pays off, but it doesn't for 2F32: - Intel i7-6700K: add-single: [1] 285.79 vs [0] 426.70 MFlops add-double: [1] 302.15 vs [0] 278.82 MFlops Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 117 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 98 insertions(+), 19 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 306a12fa8d..cc500b1618 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1050,49 +1050,128 @@ float16 QEMU_FLATTEN float16_add(float16 a, float1= 6 b, float_status *status) return float16_round_pack_canonical(pr, status); } =20 -float32 QEMU_FLATTEN float32_add(float32 a, float32 b, float_status *statu= s) +float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) +{ + FloatParts pa =3D float16_unpack_canonical(a, status); + FloatParts pb =3D float16_unpack_canonical(b, status); + FloatParts pr =3D addsub_floats(pa, pb, true, status); + + return float16_round_pack_canonical(pr, status); +} + +static float32 QEMU_SOFTFLOAT_ATTR +soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) { FloatParts pa =3D float32_unpack_canonical(a, status); FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, false, status); + FloatParts pr =3D addsub_floats(pa, pb, subtract, status); =20 return float32_round_pack_canonical(pr, status); } =20 -float64 QEMU_FLATTEN float64_add(float64 a, float64 b, float_status *statu= s) +static inline float32 soft_f32_add(float32 a, float32 b, float_status *sta= tus) +{ + return soft_f32_addsub(a, b, false, status); +} + +static inline float32 soft_f32_sub(float32 a, float32 b, float_status *sta= tus) +{ + return soft_f32_addsub(a, b, true, status); +} + +static float64 QEMU_SOFTFLOAT_ATTR +soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) { FloatParts pa =3D float64_unpack_canonical(a, status); FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, false, status); + FloatParts pr =3D addsub_floats(pa, pb, subtract, status); =20 return float64_round_pack_canonical(pr, status); } =20 -float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) +static inline float64 soft_f64_add(float64 a, float64 b, float_status *sta= tus) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, true, status); + return soft_f64_addsub(a, b, false, status); +} =20 - return float16_round_pack_canonical(pr, status); +static inline float64 soft_f64_sub(float64 a, float64 b, float_status *sta= tus) +{ + return soft_f64_addsub(a, b, true, status); } =20 -float32 QEMU_FLATTEN float32_sub(float32 a, float32 b, float_status *statu= s) +static float hard_f32_add(float a, float b) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, true, status); + return a + b; +} =20 - return float32_round_pack_canonical(pr, status); +static float hard_f32_sub(float a, float b) +{ + return a - b; } =20 -float64 QEMU_FLATTEN float64_sub(float64 a, float64 b, float_status *statu= s) +static double hard_f64_add(double a, double b) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, true, status); + return a + b; +} =20 - return float64_round_pack_canonical(pr, status); +static double hard_f64_sub(double a, double b) +{ + return a - b; +} + +static bool f32_addsub_post(union_float32 a, union_float32 b) +{ + if (QEMU_HARDFLOAT_2F32_USE_FP) { + return !(fpclassify(a.h) =3D=3D FP_ZERO && fpclassify(b.h) =3D=3D = FP_ZERO); + } + return !(float32_is_zero(a.s) && float32_is_zero(b.s)); +} + +static bool f64_addsub_post(union_float64 a, union_float64 b) +{ + if (QEMU_HARDFLOAT_2F64_USE_FP) { + return !(fpclassify(a.h) =3D=3D FP_ZERO && fpclassify(b.h) =3D=3D = FP_ZERO); + } else { + return !(float64_is_zero(a.s) && float64_is_zero(b.s)); + } +} + +static float32 float32_addsub(float32 a, float32 b, float_status *s, + hard_f32_op2_fn hard, soft_f32_op2_fn soft) +{ + return float32_gen2(a, b, s, hard, soft, + f32_is_zon2, f32_addsub_post, NULL, NULL); +} + +static float64 float64_addsub(float64 a, float64 b, float_status *s, + hard_f64_op2_fn hard, soft_f64_op2_fn soft) +{ + return float64_gen2(a, b, s, hard, soft, + f64_is_zon2, f64_addsub_post, NULL, NULL); +} + +float32 QEMU_FLATTEN +float32_add(float32 a, float32 b, float_status *s) +{ + return float32_addsub(a, b, s, hard_f32_add, soft_f32_add); +} + +float32 QEMU_FLATTEN +float32_sub(float32 a, float32 b, float_status *s) +{ + return float32_addsub(a, b, s, hard_f32_sub, soft_f32_sub); +} + +float64 QEMU_FLATTEN +float64_add(float64 a, float64 b, float_status *s) +{ + return float64_addsub(a, b, s, hard_f64_add, soft_f64_add); +} + +float64 QEMU_FLATTEN +float64_sub(float64 a, float64 b, float_status *s) +{ + return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub); } =20 /* --=20 2.17.1