From nobody Mon Feb 9 01:11:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1543104290558865.3770739521954; Sat, 24 Nov 2018 16:04:50 -0800 (PST) Received: from localhost ([::1]:58183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQhuh-0002bz-FE for importer@patchew.org; Sat, 24 Nov 2018 19:04:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQhmX-0003GN-9Z for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQhmV-0005de-Px for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:13 -0500 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]:34511) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gQhmU-0005Gt-31 for qemu-devel@nongnu.org; Sat, 24 Nov 2018 18:56:10 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 6C1EAD0C; Sat, 24 Nov 2018 18:56:03 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 24 Nov 2018 18:56:03 -0500 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B1D18102F8; Sat, 24 Nov 2018 18:56:02 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=d4KehaM7YczzpZbgJzKCWqI1nLuiRrWM6mXkGgT24LM=; b=MgTEk 1ljR0R9mRRO3wG4m+WOkFzTroflUnqGKUgHtFCtsW+k80Q0ra6TObnZy/xFjGEv/ XqLpDgEazve2f/805WwfqDwDhCCTgc3TcFdqEbQbiWFu7Q6lL9K70U0TAha6eVMQ 4wvJvPP4Gi5QFZdIDtDjmeiwgchDDfg11ujUuo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=d4KehaM7YczzpZbgJzKCWqI1nLuiR rWM6mXkGgT24LM=; b=p+R3jeDqUYSl59DasVxXT87gwK3AZxZEmsF4dsQXfeGEJ F1dnzSFPfv4qX6FASDGySYyMpCwkemU0aurJgKxHu2QvypwRYGIXuChzzDt2KkTM yfRGJgOwmUFkRkT55yE/5dWq3NlbFlKvbkxT9hh4V+PJYmeH/oGwdoHpm731UXuI nCNfcxVTEj4TTflVbPexXKZTBrmOAIUKZ1IqO1GB85EWTsxBx9yNqegt0Tz1j9C7 OxvB2sywnkFHoK9Njwlg1aE9GRzWUQtfV9AGneiM9Vzy8L3g2RV0rddj9b06JCGQ GSZIRGINLAV7LavwIsv2ati5JzpcpLAyRNzcuZhag== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 24 Nov 2018 18:55:51 -0500 Message-Id: <20181124235553.17371-12-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181124235553.17371-1-cota@braap.org> References: <20181124235553.17371-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.25 Subject: [Qemu-devel] [PATCH v6 11/13] hardfloat: implement float32/64 fused multiply-add X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Performance results for fp-bench: 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz - before: fma-single: 74.73 MFlops fma-double: 74.54 MFlops - after: fma-single: 203.37 MFlops fma-double: 169.37 MFlops 2. ARM Aarch64 A57 @ 2.4GHz - before: fma-single: 23.24 MFlops fma-double: 23.70 MFlops - after: fma-single: 66.14 MFlops fma-double: 63.10 MFlops 3. IBM POWER8E @ 2.1 GHz - before: fma-single: 37.26 MFlops fma-double: 37.29 MFlops - after: fma-single: 48.90 MFlops fma-double: 59.51 MFlops Here having 3FP64 set to 1 pays off for x86_64: [1] 170.15 vs [0] 153.12 MFlops Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 128 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e35ebfaae7..e03feafb6f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1514,8 +1514,9 @@ float16 QEMU_FLATTEN float16_muladd(float16 a, float1= 6 b, float16 c, return float16_round_pack_canonical(pr, status); } =20 -float32 QEMU_FLATTEN float32_muladd(float32 a, float32 b, float32 c, - int flags, float_status *s= tatus) +static float32 QEMU_SOFTFLOAT_ATTR +soft_f32_muladd(float32 a, float32 b, float32 c, int flags, + float_status *status) { FloatParts pa =3D float32_unpack_canonical(a, status); FloatParts pb =3D float32_unpack_canonical(b, status); @@ -1525,8 +1526,9 @@ float32 QEMU_FLATTEN float32_muladd(float32 a, float3= 2 b, float32 c, return float32_round_pack_canonical(pr, status); } =20 -float64 QEMU_FLATTEN float64_muladd(float64 a, float64 b, float64 c, - int flags, float_status *s= tatus) +static float64 QEMU_SOFTFLOAT_ATTR +soft_f64_muladd(float64 a, float64 b, float64 c, int flags, + float_status *status) { FloatParts pa =3D float64_unpack_canonical(a, status); FloatParts pb =3D float64_unpack_canonical(b, status); @@ -1536,6 +1538,128 @@ float64 QEMU_FLATTEN float64_muladd(float64 a, floa= t64 b, float64 c, return float64_round_pack_canonical(pr, status); } =20 +float32 QEMU_FLATTEN +float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status= *s) +{ + union_float32 ua, ub, uc, ur; + + ua.s =3D xa; + ub.s =3D xb; + uc.s =3D xc; + + if (unlikely(!can_use_fpu(s))) { + goto soft; + } + if (unlikely(flags & float_muladd_halve_result)) { + goto soft; + } + + float32_input_flush3(&ua.s, &ub.s, &uc.s, s); + if (unlikely(!f32_is_zon3(ua, ub, uc))) { + goto soft; + } + /* + * When (a || b) =3D=3D 0, there's no need to check for under/over flo= w, + * since we know the addend is (normal || 0) and the product is 0. + */ + if (float32_is_zero(ua.s) || float32_is_zero(ub.s)) { + union_float32 up; + bool prod_sign; + + prod_sign =3D float32_is_neg(ua.s) ^ float32_is_neg(ub.s); + prod_sign ^=3D !!(flags & float_muladd_negate_product); + up.s =3D float32_set_sign(float32_zero, prod_sign); + + if (flags & float_muladd_negate_c) { + uc.h =3D -uc.h; + } + ur.h =3D up.h + uc.h; + } else { + if (flags & float_muladd_negate_product) { + ua.h =3D -ua.h; + } + if (flags & float_muladd_negate_c) { + uc.h =3D -uc.h; + } + + ur.h =3D fmaf(ua.h, ub.h, uc.h); + + if (unlikely(f32_is_inf(ur))) { + s->float_exception_flags |=3D float_flag_overflow; + } else if (unlikely(fabsf(ur.h) <=3D FLT_MIN)) { + goto soft; + } + } + if (flags & float_muladd_negate_result) { + return float32_chs(ur.s); + } + return ur.s; + + soft: + return soft_f32_muladd(ua.s, ub.s, uc.s, flags, s); +} + +float64 QEMU_FLATTEN +float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status= *s) +{ + union_float64 ua, ub, uc, ur; + + ua.s =3D xa; + ub.s =3D xb; + uc.s =3D xc; + + if (unlikely(!can_use_fpu(s))) { + goto soft; + } + if (unlikely(flags & float_muladd_halve_result)) { + goto soft; + } + + float64_input_flush3(&ua.s, &ub.s, &uc.s, s); + if (unlikely(!f64_is_zon3(ua, ub, uc))) { + goto soft; + } + /* + * When (a || b) =3D=3D 0, there's no need to check for under/over flo= w, + * since we know the addend is (normal || 0) and the product is 0. + */ + if (float64_is_zero(ua.s) || float64_is_zero(ub.s)) { + union_float64 up; + bool prod_sign; + + prod_sign =3D float64_is_neg(ua.s) ^ float64_is_neg(ub.s); + prod_sign ^=3D !!(flags & float_muladd_negate_product); + up.s =3D float64_set_sign(float64_zero, prod_sign); + + if (flags & float_muladd_negate_c) { + uc.h =3D -uc.h; + } + ur.h =3D up.h + uc.h; + } else { + if (flags & float_muladd_negate_product) { + ua.h =3D -ua.h; + } + if (flags & float_muladd_negate_c) { + uc.h =3D -uc.h; + } + + ur.h =3D fma(ua.h, ub.h, uc.h); + + if (unlikely(f64_is_inf(ur))) { + s->float_exception_flags |=3D float_flag_overflow; + } else if (unlikely(fabs(ur.h) <=3D FLT_MIN)) { + goto soft; + } + } + if (flags & float_muladd_negate_result) { + return float64_chs(ur.s); + } + return ur.s; + + soft: + return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); +} + /* * Returns the result of dividing the floating-point value `a' by the * corresponding value `b'. The operation is performed according to --=20 2.17.1