From nobody Tue Feb 10 13:17:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984874206953.1504494595638; Fri, 23 Nov 2018 06:54:34 -0800 (PST) Received: from localhost ([::1]:52795 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCqm-0008Kn-T4 for importer@patchew.org; Fri, 23 Nov 2018 09:54:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCih-0007yd-4z for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCif-0003Ab-Q7 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38777) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCif-000384-II for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: by mail-wm1-x341.google.com with SMTP id k198so12261530wmd.3 for ; Fri, 23 Nov 2018 06:46:08 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=g9xQMxzVkTkCohHfoZiNmGPHNlO1kA/TboWANDMJOWl5rHIX8J5lqJUc1MThPmf3OK YoNe6dWyXTxQE/YNWtaaiB3tXcwUC5l8J+ksl+bj6V8rtXJyREEF5VxAxJf0gbvVr2m6 /XdYCYb+yd4zRSjC4D0ioMuxljxlmY+KOz86Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=QfHo55WJklCkQ0hAAkVg25OuQAhpIplrcPVpodR77pgG+I/fLWuyFOV1QtRIUEA7nK +LOhmVXlqnapdmG9VSWvP/PVe/UXbk7d5Olyy/Qacsxlg1HBA+5Hu3t3uEEVgosVRUGA tUXZTkRW63skCuFedXzWp1aUOZj2C8ly6hyvlo/KRBsx0evLILQDowK3QV5ds7jEfiIf iy7h4QxQSWfnik5FECk//JhN25Yyxzqngx8IwtnZ9LtsQfhwN4hkxUpeRUKcC5YuAJ0t YMvzxjkiF/K9+ltNfvHiO6tf3J7uKLnmc0I/Xk8jrsfNEw3gFxuHjg75NlCJY40mpFzR +xow== X-Gm-Message-State: AGRZ1gKcFcowgnwuyUZGcm2dPMSSovk8exuanBNMq7s5e9+ZpgipxD+t NNbbyFbAwLKd7hXNLzS7dj5OFClOALba5A== X-Google-Smtp-Source: AJdET5ctc3TD2uCxyhHRM1zBUHWe6Yvjo3wT8K7OIRb9aSN8J8IL965sB7cWXNeeemRMADO42cPD1g== X-Received: by 2002:a1c:9f8f:: with SMTP id i137mr13672918wme.30.1542984366699; Fri, 23 Nov 2018 06:46:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:27 +0100 Message-Id: <20181123144558.5048-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 06/37] tcg/i386: Return a base register from tcg_out_tlb_load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will shortly be asking the hot path not to assume TCG_REG_L1 for the host base address. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.inc.c | 56 ++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8aef66e430..3234a8d8bf 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1614,9 +1614,9 @@ static void * const qemu_st_helpers[16] =3D { =20 First argument register is clobbered. */ =20 -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, TCGMemOp opc, - tcg_insn_unit **label_ptr, int which) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, TCGMemOp opc, + tcg_insn_unit **label_ptr, int which) { const TCGReg r0 =3D TCG_REG_L0; const TCGReg r1 =3D TCG_REG_L1; @@ -1696,6 +1696,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, /* add addend(r0), r1 */ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, offsetof(CPUTLBEntry, addend) - which); + + return r1; } =20 /* @@ -2001,10 +2003,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif =20 datalo =3D *args++; datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); @@ -2014,17 +2012,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); + { + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; =20 - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_read= )); =20 - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); =20 - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset =3D guest_base; @@ -2141,10 +2143,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif =20 datalo =3D *args++; datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); @@ -2154,17 +2152,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); + { + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; =20 - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_writ= e)); =20 - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); =20 - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset =3D guest_base; --=20 2.17.2