From nobody Tue Feb 10 12:59:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542986116870556.8139063191821; Fri, 23 Nov 2018 07:15:16 -0800 (PST) Received: from localhost ([::1]:52923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDAi-0002WE-Hh for importer@patchew.org; Fri, 23 Nov 2018 10:15:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LT-Cq for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj6-0003pH-MU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj6-0003nu-GY for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:36 -0500 Received: by mail-wm1-x341.google.com with SMTP id 125so12200616wmh.0 for ; Fri, 23 Nov 2018 06:46:36 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=hP4OZGZei8NzZOZZq4OPeDcY7xKz+fnV+V8ZUI2IFJgMMxQFCl4aFt9+Pnk1jN+5MM 9edwPiTSgUfUZGbPjy2UrxpDXuvsaePSOoN0zWCOUD6jRBEWBqg1qB//ha+8tw3KlxJ2 sfaaf91mDBLV1b6+1maMx1N1hIObKag3EF/3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=J0VTvWygSs60QWMc8E6WKNqTvoNEX0tQuhDRghUyWgRfP/FvO53JdZv1PQFeRx2Gtl fb43jd9XkgpZb+R2S3KfeuRGSOJzWPbTyM3kF0kbgGp8PueCPJLkSzLyczbV5V7ipET9 3vUBRk5d3c8xNdgnITmXXRVrjvsOw8nE8cHuPG6MZqF83zHac/4okp4YdF9Di7ebfSvC f6PysLl3K3IljhUhX0lqEyMHPVZny/U7dMqhwilr/xuzFlchGry1wVDRa41U0+r45mby lkv3DIT8HX4p69JtDKn78O+UHlJEOAi9N5AsDcxWDpEoV3iHhJntY0Z/QL0UsSuRj3Wa Uc1g== X-Gm-Message-State: AGRZ1gLNVYAUvGzFFB5mpKvue/AsyGXkcHCqiBeUUR/z9dAWk82Cnsyp jvmwGoxK9eSnC6ucsDIht05B1O2tBnp/lg== X-Google-Smtp-Source: AJdET5d19jgvg6HyHKMTk1pQ22Yr4SFKQP2vVY5L0hUTZJj64vucTz7pPVFG0RZvgNkoaE8CRQeyWQ== X-Received: by 2002:a1c:a754:: with SMTP id q81mr13200585wme.132.1542984395154; Fri, 23 Nov 2018 06:46:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:57 +0100 Message-Id: <20181123144558.5048-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 36/37] tcg/i386: Require segment syscalls to succeed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There ought be no reason they should ever fail. If we don't know how to set a segment base register for user-only (NetBSD, OpenBSD?), then error out if we cannot proceed. This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 54 +++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 55c5a8516c..19a0fa8a03 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1814,9 +1814,12 @@ int arch_prctl(int code, unsigned long addr); static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (arch_prctl(ARCH_SET_GS, guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + /* There is no reason this syscall should fail. */ + if (arch_prctl(ARCH_SET_GS, guest_base) < 0) { + perror("arch_prctl(ARCH_SET_GS)"); + exit(1); } + guest_base_flags =3D P_GS; } #elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) # include @@ -1824,13 +1827,28 @@ static inline void setup_guest_base_seg(void) static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + /* There is no reason this syscall should fail. */ + if (sysarch(AMD64_SET_GSBASE, &guest_base) < 0) { + perror("sysarch(AMD64_SET_GSBASE)"); + exit(1); } + guest_base_flags =3D P_GS; } #else # define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +static inline void setup_guest_base_seg(void) +{ + /* + * Verify we can proceed without scratch registers. + * If guest_base > INT32_MAX, then it would need to be loaded. + * If 32-bit guest, the address would need to be zero-extended. + */ + if (TCG_TARGET_REG_BITS =3D=3D 64 + && (TARGET_LONG_BITS =3D=3D 32 || guest_base > INT32_MAX)) { + error_report("Segment base register not supported on this OS"); + exit(1); + } +} #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2013,16 +2031,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |=3D P_ADDR32; } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - if (offset !=3D guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, @@ -2156,22 +2164,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |=3D P_ADDR32; } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset !=3D guest_base) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base =3D TCG_REG_L1; - offset =3D 0; - } else if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base =3D TCG_REG_L1; - } } =20 tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); --=20 2.17.2