From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984514455878.0820612165378; Fri, 23 Nov 2018 06:48:34 -0800 (PST) Received: from localhost ([::1]:52759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCkr-0001v6-1u for importer@patchew.org; Fri, 23 Nov 2018 09:48:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yS-Qu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCia-00036F-Pu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:39293) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCia-00035H-35 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:04 -0500 Received: by mail-wm1-x344.google.com with SMTP id u13-v6so12247957wmc.4 for ; Fri, 23 Nov 2018 06:46:03 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fux7GoiV8l3FnF1Vyj9P8uU4timqrhfpmRWnGlzFzqM=; b=CESSUrP+KRFaLAPVT6X/RRGzPEY8pFM3Q53qJELQ9eIQkSg2FgI/zpc5c9bH1+VjFa kTxkm5O7Mh8xBOF1sskFOqJf1jJGu1K7exMd8+ptMHrZY1ff6z6OzbbcAtYTMSJmddgc P4WGhwPbr0Hf1LnFA2Hq1jxcgP8jbQ9hb3HMc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fux7GoiV8l3FnF1Vyj9P8uU4timqrhfpmRWnGlzFzqM=; b=tEaqmWGBG1cKWrKz2C7vTRIksZshfmCx3gHc5LnHAGUmT/YU6lLRRpWYknAi3Mj3IQ afGI6M48S/GEnCGv9qlxfvxcXthTo/g6i8eQBXInToFhGxrak6bVWsufT+gQsViW4ZcM XH3T1XrZnQobSzrMMy910qw/Whtolc0IlIqtv1ifvpThLHbpZcJzWaePIbRUT6NMBuM1 eJzFHDZFqt9YM6S5BC7GXdO4b8xyb34nJenRuvbfxFW10cbB7md3RytRyKT36v6hblw+ meljtUPVwXLILE1iwG6r5q+Giri9w/Jnve5I+Amigk3pvNUS5w2NVLiDtKRmra40ML+E XmlQ== X-Gm-Message-State: AGRZ1gIP92F9pOtUmcfEzbcbUYJMIq3DqUmtzMllIRvx5mHSbbOQ0/Nv /gsTlm0MJ4h/jAfvaBnZmUgKFVHb4heaiw== X-Google-Smtp-Source: AJdET5dSFdnVnR1BesQpeXRPBUi2v24SdZkNgHtP7I8vpUdgFbTdYjAB+ErIRMS9HpbGqyGZm/ySXg== X-Received: by 2002:a1c:af89:: with SMTP id y131mr13884953wme.137.1542984361904; Fri, 23 Nov 2018 06:46:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:22 +0100 Message-Id: <20181123144558.5048-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 01/37] tcg/i386: Always use %ebp for TCG_AREG0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For x86_64, this can result in smaller code when manipulating TCG_TYPE_I32, as we can omit a REX prefix. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 9fdf37f23c..7488c3d869 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -84,6 +84,8 @@ typedef enum { TCG_REG_RBP =3D TCG_REG_EBP, TCG_REG_RSI =3D TCG_REG_ESI, TCG_REG_RDI =3D TCG_REG_EDI, + + TCG_AREG0 =3D TCG_REG_EBP, } TCGReg; =20 /* used for function call generation */ @@ -194,12 +196,6 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_AREG0 TCG_REG_R14 -#else -# define TCG_AREG0 TCG_REG_EBP -#endif - static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984513247417.44774815519145; Fri, 23 Nov 2018 06:48:33 -0800 (PST) Received: from localhost ([::1]:52760 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCkq-0001xN-WC for importer@patchew.org; Fri, 23 Nov 2018 09:48:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43765) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yQ-Qt for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCia-00036Z-SU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:38430) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCia-00035e-Mh for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:04 -0500 Received: by mail-wr1-x442.google.com with SMTP id v13so9116944wrw.5 for ; Fri, 23 Nov 2018 06:46:04 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yNQmwVUAvqPZBQpEvZxNr8bwL4aHF0jtNAxTMDvMNMk=; b=auygdKAIWnmgSzUQxRW14q/DaERmdN8xaFhEJFbTb/MqOJdNS1f0RUyk6vQLBq8/sv 8qSVGhydwEL6GweqBnf0Ey93nrr2BXCSsKX0ApmnzDYfNA2XzQT0iCitnN/WX0KV83nG SGpVNRqpVMQ8RRm8qVb3oQscuWfpCTV6s5hro= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yNQmwVUAvqPZBQpEvZxNr8bwL4aHF0jtNAxTMDvMNMk=; b=R7kapbzfYqeto3g73e1C8KIsE7gLILOmaJtBv9g/tPvd2HYiVWU2wiIuZfrj0zkLn4 7h6jmhwijQWfaKk2jGfiexWNs5vY8RJvAFT3afwMIvpgVmHiTkHzD4grUWebPzET/gV1 O2qTfCewuC2nKKRi+P0MLBAiqrRDOqgIjw8hKnK3LshboGWjFDbgHLJGcdYfjeDqgdK9 PqPZ9H8cHi1M4lSNUxYLsza/RBMJJHXkX9c2eDnMNcEHKEddIQ/GiKLj1zFl96kWr8iP 3xRcoTfqqJ5gy68t95NFVIAYSle8Sclp+2y4KdX7b4yMgR8Zy6FfBMZnAKMRAoq7rDJF /qVQ== X-Gm-Message-State: AA+aEWbMczpzwQm0WGddy8GH22asfy3Qo7uGkCh04XsAOuI6g73B4O9j bwP0x+IJXAE3TLQ3C18tdPXjvWcjh7QAsA== X-Google-Smtp-Source: AFSGD/V04WX7qobygE9QGt6YSfP6HjZMTrJ3wntaU3Sc1rBYdf923r0Ed12neggHW3iAabK0jKL0Gw== X-Received: by 2002:a5d:46c2:: with SMTP id g2mr14794455wrs.49.1542984362856; Fri, 23 Nov 2018 06:46:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:23 +0100 Message-Id: <20181123144558.5048-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 02/37] tcg/i386: Move TCG_REG_CALL_STACK from define to enum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7488c3d869..2441658865 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -86,10 +86,10 @@ typedef enum { TCG_REG_RDI =3D TCG_REG_EDI, =20 TCG_AREG0 =3D TCG_REG_EBP, + TCG_REG_CALL_STACK =3D TCG_REG_ESP } TCGReg; =20 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_ESP=20 #define TCG_TARGET_STACK_ALIGN 16 #if defined(_WIN64) #define TCG_TARGET_CALL_STACK_OFFSET 32 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985053924662.2713492543204; Fri, 23 Nov 2018 06:57:33 -0800 (PST) Received: from localhost ([::1]:52815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCtg-0002Js-J1 for importer@patchew.org; Fri, 23 Nov 2018 09:57:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yV-Qw for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCid-000380-KD for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53662) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCib-00036V-Me for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:06 -0500 Received: by mail-wm1-x344.google.com with SMTP id y1so8891142wmi.3 for ; Fri, 23 Nov 2018 06:46:05 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U79fIgS0hejBQL/zjUbT562kgbBz2dY+Sn5LbZq038M=; b=YTpMFc+ruzdf1pbmcjqmF9PsWIqXN9Q5Nslourorea9PuXkarxGCOpJafivp6VcAFV 2TJoF/tBUPQLJykb4pipXaAqLabwpBAxY5txx0PUTFhSHLIXADg+gA0Pb2GVOW2oJUcG JkouZYqOt7zB+mgi0p8fJe5nBJTuNMnqqNIos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U79fIgS0hejBQL/zjUbT562kgbBz2dY+Sn5LbZq038M=; b=jmQX8KsvCUNmvm+PrjnSluSF85tIPDS8HfjhoZHNkf7nQcUg5oxmdyDXCb9F23MlFL Nzpz61GkRoJzk1Zx0p+9DhDmn7V/cjk2eZFubCi+nF/LFDbDaj5x90Idqv9OzyocwIhT 8MFxIN4lukEpa9yBHZ4qksM7f6HdmEeJ+E8vvo3zuueIyv4btgR7MUacQdBjJBWWN55x jWv2JWj4hTNcG2/IuDdmkM/Nq4H84MJoGO7CzNsDPW9vbp/hJxpHQsNxFWNSpZEMkLVO eOajmzhP9ydM/wQIf4ZPOIM7QfN8gWTmks+gciwng1UcBB++pi3veJuOirQrazlNN1cE YTDw== X-Gm-Message-State: AA+aEWb2aodDjFa5adD4gE8AjTt3aTOKrEPnlfUBrTfaZr+RYWiapvPy W52WBnZGxPbNP9ZOSaNo6PkZCK/YcI7j6A== X-Google-Smtp-Source: AFSGD/WB/QPyHcXHZPvmcoIVfFnTpoRzmTL6Gf37gAAvkw8xb3yWqxMFniDJXnDGmLnAzvpiuGVLEg== X-Received: by 2002:a1c:5892:: with SMTP id m140mr14037065wmb.60.1542984363857; Fri, 23 Nov 2018 06:46:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:24 +0100 Message-Id: <20181123144558.5048-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 03/37] tcg: Return success from patch_reloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This moves the assert for success from inside patch_reloc to outside patch_reloc. This touches all tcg backends. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.inc.c | 44 ++++++++++++++------------------- tcg/arm/tcg-target.inc.c | 26 +++++++++----------- tcg/i386/tcg-target.inc.c | 17 +++++++------ tcg/mips/tcg-target.inc.c | 29 +++++++++------------- tcg/ppc/tcg-target.inc.c | 47 ++++++++++++++++++++++-------------- tcg/s390/tcg-target.inc.c | 37 +++++++++++++++++++--------- tcg/sparc/tcg-target.inc.c | 13 ++++++---- tcg/tcg-pool.inc.c | 5 +++- tcg/tcg.c | 8 +++--- tcg/tci/tcg-target.inc.c | 3 ++- 10 files changed, 125 insertions(+), 104 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 083592a4d7..30091f6a69 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -78,48 +78,40 @@ static const int tcg_target_call_oarg_regs[1] =3D { #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif =20 -static inline void reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) +static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) { ptrdiff_t offset =3D target - code_ptr; - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 26)); - /* read instruction, mask away previous PC_REL26 parameter contents, - set the proper offset, then write back the instruction. */ - *code_ptr =3D deposit32(*code_ptr, 0, 26, offset); + if (offset =3D=3D sextract64(offset, 0, 26)) { + /* read instruction, mask away previous PC_REL26 parameter content= s, + set the proper offset, then write back the instruction. */ + *code_ptr =3D deposit32(*code_ptr, 0, 26, offset); + return true; + } + return false; } =20 -static inline void reloc_pc26_atomic(tcg_insn_unit *code_ptr, - tcg_insn_unit *target) +static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) { ptrdiff_t offset =3D target - code_ptr; - tcg_insn_unit insn; - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 26)); - /* read instruction, mask away previous PC_REL26 parameter contents, - set the proper offset, then write back the instruction. */ - insn =3D atomic_read(code_ptr); - atomic_set(code_ptr, deposit32(insn, 0, 26, offset)); + if (offset =3D=3D sextract64(offset, 0, 19)) { + *code_ptr =3D deposit32(*code_ptr, 5, 19, offset); + return true; + } + return false; } =20 -static inline void reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) -{ - ptrdiff_t offset =3D target - code_ptr; - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 19)); - *code_ptr =3D deposit32(*code_ptr, 5, 19, offset); -} - -static inline void patch_reloc(tcg_insn_unit *code_ptr, int type, +static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend =3D=3D 0); switch (type) { case R_AARCH64_JUMP26: case R_AARCH64_CALL26: - reloc_pc26(code_ptr, (tcg_insn_unit *)value); - break; + return reloc_pc26(code_ptr, (tcg_insn_unit *)value); case R_AARCH64_CONDBR19: - reloc_pc19(code_ptr, (tcg_insn_unit *)value); - break; + return reloc_pc19(code_ptr, (tcg_insn_unit *)value); default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index e1fbf465cb..80d174ef44 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -187,27 +187,23 @@ static const uint8_t tcg_cond_to_arm_cond[] =3D { [TCG_COND_GTU] =3D COND_HI, }; =20 -static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) +static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) { ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; - *code_ptr =3D (*code_ptr & ~0xffffff) | (offset & 0xffffff); + if (offset =3D=3D sextract32(offset, 0, 24)) { + *code_ptr =3D (*code_ptr & ~0xffffff) | (offset & 0xffffff); + return true; + } + return false; } =20 -static inline void reloc_pc24_atomic(tcg_insn_unit *code_ptr, tcg_insn_uni= t *target) -{ - ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; - tcg_insn_unit insn =3D atomic_read(code_ptr); - tcg_debug_assert(offset =3D=3D sextract32(offset, 0, 24)); - atomic_set(code_ptr, deposit32(insn, 0, 24, offset)); -} - -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend =3D=3D 0); =20 if (type =3D=3D R_ARM_PC24) { - reloc_pc24(code_ptr, (tcg_insn_unit *)value); + return reloc_pc24(code_ptr, (tcg_insn_unit *)value); } else if (type =3D=3D R_ARM_PC13) { intptr_t diff =3D value - (uintptr_t)(code_ptr + 2); tcg_insn_unit insn =3D *code_ptr; @@ -218,10 +214,9 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int t= ype, if (!u) { diff =3D -diff; } - } else { + } else if (diff >=3D 0x1000 && diff < 0x100000) { int rd =3D extract32(insn, 12, 4); int rt =3D rd =3D=3D TCG_REG_PC ? TCG_REG_TMP : rd; - assert(diff >=3D 0x1000 && diff < 0x100000); /* add rt, pc, #high */ *code_ptr++ =3D ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD | (TCG_REG_PC << 16) | (rt << 12) @@ -230,10 +225,13 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int = type, insn =3D deposit32(insn, 12, 4, rt); diff &=3D 0xfff; u =3D 1; + } else { + return false; } insn =3D deposit32(insn, 23, 1, u); insn =3D deposit32(insn, 0, 12, diff); *code_ptr =3D insn; + return true; } else { g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 436195894b..4f66a0c5ae 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -167,29 +167,32 @@ static bool have_lzcnt; =20 static tcg_insn_unit *tb_ret_addr; =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { value +=3D addend; - switch(type) { + + switch (type) { case R_386_PC32: value -=3D (uintptr_t)code_ptr; if (value !=3D (int32_t)value) { - tcg_abort(); + return false; } /* FALLTHRU */ case R_386_32: tcg_patch32(code_ptr, value); - break; + return true; + case R_386_PC8: value -=3D (uintptr_t)code_ptr; if (value !=3D (int8_t)value) { - tcg_abort(); + return false; } tcg_patch8(code_ptr, value); - break; + return true; + default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index cff525373b..e59c66b607 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -144,36 +144,29 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; =20 -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *ta= rget) +static bool reloc_pc16_cond(tcg_insn_unit *pc, tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic.= */ ptrdiff_t disp =3D target - (pc + 1); - tcg_debug_assert(disp =3D=3D (int16_t)disp); - return disp & 0xffff; + if (disp =3D=3D (int16_t)disp) { + *pc =3D deposit32(*pc, 0, 16, disp); + return true; + } else { + return false; + } } =20 -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) { - *pc =3D deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); + tcg_debug_assert(reloc_pc16_cond(pc, target)); } =20 -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *targ= et) -{ - tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) = =3D=3D 0); - return ((uintptr_t)target >> 2) & 0x3ffffff; -} - -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc =3D deposit32(*pc, 0, 26, reloc_26_val(pc, target)); -} - -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(type =3D=3D R_MIPS_PC16); tcg_debug_assert(addend =3D=3D 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); + return reloc_pc16_cond(code_ptr, (tcg_insn_unit *)value); } =20 #define TCG_CT_CONST_ZERO 0x100 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c2f729ee8f..656a9ff603 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -186,16 +186,14 @@ static inline bool in_range_b(tcg_target_long target) return target =3D=3D sextract64(target, 0, 26); } =20 -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc24_cond(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp =3D tcg_ptr_byte_diff(target, pc); - tcg_debug_assert(in_range_b(disp)); - return disp & 0x3fffffc; -} - -static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc =3D (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target); + if (in_range_b(disp)) { + *pc =3D (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + return true; + } + return false; } =20 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) @@ -205,10 +203,22 @@ static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg= _insn_unit *target) return disp & 0xfffc; } =20 +static bool reloc_pc14_cond(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp =3D tcg_ptr_byte_diff(target, pc); + if (disp =3D=3D (int16_t) disp) { + *pc =3D (*pc & ~0xfffc) | (disp & 0xfffc); + return true; + } + return false; +} + +#ifdef CONFIG_SOFTMMU static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) { - *pc =3D (*pc & ~0xfffc) | reloc_pc14_val(pc, target); + tcg_debug_assert(reloc_pc14_cond(pc, target)); } +#endif =20 static inline void tcg_out_b_noaddr(TCGContext *s, int insn) { @@ -525,7 +535,7 @@ static const uint32_t tcg_to_isel[] =3D { [TCG_COND_GTU] =3D ISEL | BC_(7, CR_GT), }; =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_insn_unit *target; @@ -536,11 +546,9 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int t= ype, =20 switch (type) { case R_PPC_REL14: - reloc_pc14(code_ptr, target); - break; + return reloc_pc14_cond(code_ptr, target); case R_PPC_REL24: - reloc_pc24(code_ptr, target); - break; + return reloc_pc24_cond(code_ptr, target); case R_PPC_ADDR16: /* We are abusing this relocation type. This points to a pair of insns, addis + load. If the displacement is small, we @@ -552,11 +560,14 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int = type, } else { int16_t lo =3D value; int hi =3D value - lo; - assert(hi + lo =3D=3D value); - code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); - code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + if (hi + lo =3D=3D value) { + code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + } else { + return false; + } } - break; + return true; default: g_assert_not_reached(); } diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 17c435ade5..a8d72dd630 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -366,7 +366,7 @@ static void * const qemu_st_helpers[16] =3D { static tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities; =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { intptr_t pcrel2; @@ -377,22 +377,35 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int = type, =20 switch (type) { case R_390_PC16DBL: - assert(pcrel2 =3D=3D (int16_t)pcrel2); - tcg_patch16(code_ptr, pcrel2); + if (pcrel2 =3D=3D (int16_t)pcrel2) { + tcg_patch16(code_ptr, pcrel2); + return true; + } break; case R_390_PC32DBL: - assert(pcrel2 =3D=3D (int32_t)pcrel2); - tcg_patch32(code_ptr, pcrel2); + if (pcrel2 =3D=3D (int32_t)pcrel2) { + tcg_patch32(code_ptr, pcrel2); + return true; + } break; case R_390_20: - assert(value =3D=3D sextract64(value, 0, 20)); - old =3D *(uint32_t *)code_ptr & 0xf00000ff; - old |=3D ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); + if (value =3D=3D sextract64(value, 0, 20)) { + old =3D *(uint32_t *)code_ptr & 0xf00000ff; + old |=3D ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); + tcg_patch32(code_ptr, old); + return true; + } break; default: g_assert_not_reached(); } + return false; +} + +static void patch_reloc_force(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(patch_reloc(code_ptr, type, value, addend)); } =20 /* parse target specific constraints */ @@ -1618,7 +1631,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); + patch_reloc_force(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2); =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1639,7 +1653,8 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); + patch_reloc_force(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2); =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 04bdc3df5e..111f3312d3 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -291,32 +291,34 @@ static inline int check_fit_i32(int32_t val, unsigned= int bits) # define check_fit_ptr check_fit_i32 #endif =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { uint32_t insn =3D *code_ptr; intptr_t pcrel; + bool ret; =20 value +=3D addend; pcrel =3D tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); =20 switch (type) { case R_SPARC_WDISP16: - assert(check_fit_ptr(pcrel >> 2, 16)); + ret =3D check_fit_ptr(pcrel >> 2, 16); insn &=3D ~INSN_OFF16(-1); insn |=3D INSN_OFF16(pcrel); break; case R_SPARC_WDISP19: - assert(check_fit_ptr(pcrel >> 2, 19)); + ret =3D check_fit_ptr(pcrel >> 2, 19); insn &=3D ~INSN_OFF19(-1); insn |=3D INSN_OFF19(pcrel); break; case R_SPARC_13: /* Note that we're abusing this reloc type for our own needs. */ + ret =3D true; if (!check_fit_ptr(value, 13)) { int adj =3D (value > 0 ? 0xff8 : -0x1000); value -=3D adj; - assert(check_fit_ptr(value, 13)); + ret =3D check_fit_ptr(value, 13); *code_ptr++ =3D (ARITH_ADD | INSN_RD(TCG_REG_T2) | INSN_RS1(TCG_REG_TB) | INSN_IMM13(adj)); insn ^=3D INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2); @@ -328,12 +330,13 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int = type, /* Note that we're abusing this reloc type for our own needs. */ code_ptr[0] =3D deposit32(code_ptr[0], 0, 22, value >> 10); code_ptr[1] =3D deposit32(code_ptr[1], 0, 10, value); - return; + return value =3D=3D (intptr_t)(uint32_t)value; default: g_assert_not_reached(); } =20 *code_ptr =3D insn; + return ret; } =20 /* parse target specific constraints */ diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c index 7af5513ff3..ab8f6df8b0 100644 --- a/tcg/tcg-pool.inc.c +++ b/tcg/tcg-pool.inc.c @@ -140,6 +140,8 @@ static bool tcg_out_pool_finalize(TCGContext *s) =20 for (; p !=3D NULL; p =3D p->next) { size_t size =3D sizeof(tcg_target_ulong) * p->nlong; + bool ok; + if (!l || l->nlong !=3D p->nlong || memcmp(l->data, p->data, size)= ) { if (unlikely(a > s->code_gen_highwater)) { return false; @@ -148,7 +150,8 @@ static bool tcg_out_pool_finalize(TCGContext *s) a +=3D size; l =3D p; } - patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + ok =3D patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->adde= nd); + tcg_debug_assert(ok); } =20 s->code_ptr =3D a; diff --git a/tcg/tcg.c b/tcg/tcg.c index e85133ef05..54f1272187 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,7 +66,7 @@ static void tcg_target_init(TCGContext *s); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); static void tcg_target_qemu_prologue(TCGContext *s); -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); =20 /* The CIE and FDE header definitions will be common to all hosts. */ @@ -268,7 +268,8 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit = *code_ptr, int type, /* FIXME: This may break relocations on RISC targets that modify instruction fields in place. The caller may not have=20 written the initial value. */ - patch_reloc(code_ptr, type, l->u.value, addend); + bool ok =3D patch_reloc(code_ptr, type, l->u.value, addend); + tcg_debug_assert(ok); } else { /* add a new relocation entry */ r =3D tcg_malloc(sizeof(TCGRelocation)); @@ -288,7 +289,8 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, t= cg_insn_unit *ptr) tcg_debug_assert(!l->has_value); =20 for (r =3D l->u.first_reloc; r !=3D NULL; r =3D r->next) { - patch_reloc(r->ptr, r->type, value, r->addend); + bool ok =3D patch_reloc(r->ptr, r->type, value, r->addend); + tcg_debug_assert(ok); } =20 l->has_value =3D 1; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 62ed097254..0015a98485 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -369,7 +369,7 @@ static const char *const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { }; #endif =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { /* tcg_out_reloc always uses the same type, addend. */ @@ -381,6 +381,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, } else { tcg_patch64(code_ptr, value); } + return true; } =20 /* Parse target specific constraints. */ --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984694635947.0328041645436; Fri, 23 Nov 2018 06:51:34 -0800 (PST) Received: from localhost ([::1]:52779 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCnt-00054V-8x for importer@patchew.org; Fri, 23 Nov 2018 09:51:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yT-Qu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCid-00038B-MO for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:50875) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCic-00036n-KQ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:07 -0500 Received: by mail-wm1-x342.google.com with SMTP id 125so12199204wmh.0 for ; Fri, 23 Nov 2018 06:46:05 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gMtbi1YlmG7TeeMSvQDC1HT4x/YMqKbJWvOlr3IvkwQ=; b=WI97c4vsLQIhI8ZI+ykjd9EbCJUVakHqvRhgolNwE7j6N2/h18B4bktAfpRUgZvfUN rlVLW6I4UDmp7W0ESy/+KvZ3E2OCfDQM/a6gg1spCN9GSzOWpoG2CnYFaXC2046hCsHq s7Pr+uucuMItAX9ILPCFgScPwVOnMv/cy4pLc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gMtbi1YlmG7TeeMSvQDC1HT4x/YMqKbJWvOlr3IvkwQ=; b=gKKid48oo9b45qMAsXqt1060OqGrrlf1siacWrENHKvmYSrihPmQ7sMOTgVtmlVbvo eKdGsbWRhquy06Fy43+znuLlndya9UThAStWaKH2tJ6PxgLRixEbFDY0WUzE23G1nEgE HXH7ZcgonLAz3aMkSGa5XuisGH07OcGvR5Yc+QnCVv7KJFjwX7jVbbJGG3CyskTaF1Qu +ndDIN8+KiGrRy1DceB4gx78x9HRx90tCaqgpl+RRYSWbgRxo3LBqt+CR2jEFiM9Ns1O i1QNFqp82p0Zn5JcNMYvaZulc6M0JiZOv44VC4CvAlz7j5H/lkBDv/Fp5OkWhySapAqR n4mQ== X-Gm-Message-State: AA+aEWYLhSkxo+Li7qXD9BLMbXsZBJ3VB0aFpTlI3CcE//PciWOmcSq8 NdNV8F/mHyWVaz6qxgVgiUCXFwZOyl3b9Q== X-Google-Smtp-Source: AJdET5ckzYXtv2jS95LT0R/L8WGOysub8rQN9XGl7N7CqVEtbXANc4wjqGypzpU7oswC9ELXHuNdRQ== X-Received: by 2002:a1c:aecb:: with SMTP id x194mr13020337wme.96.1542984364704; Fri, 23 Nov 2018 06:46:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:25 +0100 Message-Id: <20181123144558.5048-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 04/37] tcg: Add TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This variant of tcg-ldst.inc.c allows the entire thunk to be moved out-of-line, with caching across TBs within a region. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.h | 5 +++ accel/tcg/translate-all.c | 15 +++++-- tcg/tcg-ldst-ool.inc.c | 95 +++++++++++++++++++++++++++++++++++++++ tcg/tcg.c | 28 ++++++++++++ 4 files changed, 140 insertions(+), 3 deletions(-) create mode 100644 tcg/tcg-ldst-ool.inc.c diff --git a/tcg/tcg.h b/tcg/tcg.h index f4efbaa680..73737dc671 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -706,6 +706,11 @@ struct TCGContext { #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdst) ldst_labels; #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdstOol) ldst_ool_labels; + GHashTable *ldst_ool_thunks; + size_t ldst_ool_generation; +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS struct TCGLabelPoolData *pool_labels; #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b2728..dd9332b24c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1678,6 +1678,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong virt_page2; tcg_insn_unit *gen_code_buf; int gen_code_size, search_size; +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + size_t ldst_ool_generation =3D tcg_ctx->ldst_ool_generation; +#endif #ifdef CONFIG_PROFILER TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; @@ -1831,10 +1834,16 @@ TranslationBlock *tb_gen_code(CPUState *cpu, existing_tb =3D tb_link_page(tb, phys_pc, phys_page2); /* if the TB already exists, discard what we just translated */ if (unlikely(existing_tb !=3D tb)) { - uintptr_t orig_aligned =3D (uintptr_t)gen_code_buf; + bool discard =3D true; =20 - orig_aligned -=3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); - atomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + discard =3D ldst_ool_generation =3D=3D tcg_ctx->ldst_ool_generatio= n; +#endif + if (discard) { + uintptr_t orig_aligned =3D (uintptr_t)gen_code_buf; + orig_aligned -=3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); + atomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); + } return existing_tb; } tcg_tb_insert(tb); diff --git a/tcg/tcg-ldst-ool.inc.c b/tcg/tcg-ldst-ool.inc.c new file mode 100644 index 0000000000..70b8789797 --- /dev/null +++ b/tcg/tcg-ldst-ool.inc.c @@ -0,0 +1,95 @@ +/* + * TCG Backend Data: load-store optimization only. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelQemuLdstOol { + QSIMPLEQ_ENTRY(TCGLabelQemuLdstOol) next; + tcg_insn_unit *label; /* label pointer to be updated */ + int reloc; /* relocation type from label_ptr */ + intptr_t addend; /* relocation addend from label_ptr */ + uint32_t key; /* oi : is_64 : is_ld */ +} TCGLabelQemuLdstOol; + + +/* + * Generate TB finalization at the end of block + */ + +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is64, TCGMemOpIdx oi); + +static bool tcg_out_ldst_ool_finalize(TCGContext *s) +{ + TCGLabelQemuLdstOol *lb; + + /* qemu_ld/st slow paths */ + QSIMPLEQ_FOREACH(lb, &s->ldst_ool_labels, next) { + gpointer dest, key =3D (gpointer)(uintptr_t)lb->key; + TCGMemOpIdx oi; + bool is_ld, is_64, ok; + + /* If we have generated the thunk, and it's still in range, all ok= . */ + dest =3D g_hash_table_lookup(s->ldst_ool_thunks, key); + if (dest && + patch_reloc(lb->label, lb->reloc, (intptr_t)dest, lb->addend))= { + continue; + } + + /* Generate a new thunk. */ + is_ld =3D extract32(lb->key, 0, 1); + is_64 =3D extract32(lb->key, 1, 1); + oi =3D extract32(lb->key, 2, 30); + dest =3D tcg_out_qemu_ldst_ool(s, is_ld, is_64, oi); + + /* Test for (pending) buffer overflow. The assumption is that any + one thunk beginning below the high water mark cannot overrun + the buffer completely. Thus we can test for overflow after + generating code without having to check during generation. */ + if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { + return false; + } + + /* Remember the thunk for next time. */ + g_hash_table_replace(s->ldst_ool_thunks, key, dest); + s->ldst_ool_generation++; + + /* The new thunk must be in range. */ + ok =3D patch_reloc(lb->label, lb->reloc, (intptr_t)dest, lb->adden= d); + tcg_debug_assert(ok); + } + return true; +} + +/* + * Allocate a new TCGLabelQemuLdstOol entry. + */ + +static void add_ldst_ool_label(TCGContext *s, bool is_ld, bool is_64, + TCGMemOpIdx oi, int reloc, intptr_t addend) +{ + TCGLabelQemuLdstOol *lb =3D tcg_malloc(sizeof(*lb)); + + QSIMPLEQ_INSERT_TAIL(&s->ldst_ool_labels, lb, next); + lb->label =3D s->code_ptr; + lb->reloc =3D reloc; + lb->addend =3D addend; + lb->key =3D is_ld | (is_64 << 1) | (oi << 2); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 54f1272187..17c193791f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -521,6 +521,13 @@ static void tcg_region_assign(TCGContext *s, size_t cu= rr_region) s->code_gen_ptr =3D start; s->code_gen_buffer_size =3D end - start; s->code_gen_highwater =3D end - TCG_HIGHWATER; + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* No thunks yet generated this region. Even if they were in range, + this is also the most convenient place to clear the table after a + full tb_flush. */ + g_hash_table_remove_all(s->ldst_ool_thunks); +#endif } =20 static bool tcg_region_alloc__locked(TCGContext *s) @@ -756,6 +763,14 @@ void tcg_register_thread(void) err =3D tcg_region_initial_alloc__locked(tcg_ctx); g_assert(!err); qemu_mutex_unlock(®ion.lock); + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* If n =3D=3D 0, keep the hash table we allocated in tcg_context_init= . */ + if (n) { + /* Both key and value are raw pointers. */ + s->ldst_ool_thunks =3D g_hash_table_new(NULL, NULL); + } +#endif } #endif /* !CONFIG_USER_ONLY */ =20 @@ -964,6 +979,11 @@ void tcg_context_init(TCGContext *s) tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); ts =3D tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); cpu_env =3D temp_tcgv_ptr(ts); + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* Both key and value are raw pointers. */ + s->ldst_ool_thunks =3D g_hash_table_new(NULL, NULL); +#endif } =20 /* @@ -3540,6 +3560,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + QSIMPLEQ_INIT(&s->ldst_ool_labels); +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS s->pool_labels =3D NULL; #endif @@ -3620,6 +3643,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -1; } #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + if (!tcg_out_ldst_ool_finalize(s)) { + return -1; + } +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS if (!tcg_out_pool_finalize(s)) { return -1; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 23 Nov 2018 06:46:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:26 +0100 Message-Id: <20181123144558.5048-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 05/37] tcg/i386: Add constraints for r8 and r9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are function call arguments for x86_64 we will need soon. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 4f66a0c5ae..8aef66e430 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -233,6 +233,14 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_REG; tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); break; + case 'E': /* "Eight", r8 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R8); + break; + case 'N': /* "Nine", r9 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R9); + break; case 'q': /* A register that can be used as a byte operand. */ ct->ct |=3D TCG_CT_REG; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984874206953.1504494595638; Fri, 23 Nov 2018 06:54:34 -0800 (PST) Received: from localhost ([::1]:52795 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCqm-0008Kn-T4 for importer@patchew.org; Fri, 23 Nov 2018 09:54:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCih-0007yd-4z for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCif-0003Ab-Q7 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38777) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCif-000384-II for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: by mail-wm1-x341.google.com with SMTP id k198so12261530wmd.3 for ; Fri, 23 Nov 2018 06:46:08 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=g9xQMxzVkTkCohHfoZiNmGPHNlO1kA/TboWANDMJOWl5rHIX8J5lqJUc1MThPmf3OK YoNe6dWyXTxQE/YNWtaaiB3tXcwUC5l8J+ksl+bj6V8rtXJyREEF5VxAxJf0gbvVr2m6 /XdYCYb+yd4zRSjC4D0ioMuxljxlmY+KOz86Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=QfHo55WJklCkQ0hAAkVg25OuQAhpIplrcPVpodR77pgG+I/fLWuyFOV1QtRIUEA7nK +LOhmVXlqnapdmG9VSWvP/PVe/UXbk7d5Olyy/Qacsxlg1HBA+5Hu3t3uEEVgosVRUGA tUXZTkRW63skCuFedXzWp1aUOZj2C8ly6hyvlo/KRBsx0evLILQDowK3QV5ds7jEfiIf iy7h4QxQSWfnik5FECk//JhN25Yyxzqngx8IwtnZ9LtsQfhwN4hkxUpeRUKcC5YuAJ0t YMvzxjkiF/K9+ltNfvHiO6tf3J7uKLnmc0I/Xk8jrsfNEw3gFxuHjg75NlCJY40mpFzR +xow== X-Gm-Message-State: AGRZ1gKcFcowgnwuyUZGcm2dPMSSovk8exuanBNMq7s5e9+ZpgipxD+t NNbbyFbAwLKd7hXNLzS7dj5OFClOALba5A== X-Google-Smtp-Source: AJdET5ctc3TD2uCxyhHRM1zBUHWe6Yvjo3wT8K7OIRb9aSN8J8IL965sB7cWXNeeemRMADO42cPD1g== X-Received: by 2002:a1c:9f8f:: with SMTP id i137mr13672918wme.30.1542984366699; Fri, 23 Nov 2018 06:46:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:27 +0100 Message-Id: <20181123144558.5048-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 06/37] tcg/i386: Return a base register from tcg_out_tlb_load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will shortly be asking the hot path not to assume TCG_REG_L1 for the host base address. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 56 ++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8aef66e430..3234a8d8bf 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1614,9 +1614,9 @@ static void * const qemu_st_helpers[16] =3D { =20 First argument register is clobbered. */ =20 -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, TCGMemOp opc, - tcg_insn_unit **label_ptr, int which) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, TCGMemOp opc, + tcg_insn_unit **label_ptr, int which) { const TCGReg r0 =3D TCG_REG_L0; const TCGReg r1 =3D TCG_REG_L1; @@ -1696,6 +1696,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, /* add addend(r0), r1 */ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, offsetof(CPUTLBEntry, addend) - which); + + return r1; } =20 /* @@ -2001,10 +2003,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif =20 datalo =3D *args++; datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); @@ -2014,17 +2012,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); + { + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; =20 - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_read= )); =20 - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); =20 - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset =3D guest_base; @@ -2141,10 +2143,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif =20 datalo =3D *args++; datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); @@ -2154,17 +2152,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); + { + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; =20 - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_writ= e)); =20 - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); =20 - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset =3D guest_base; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984691313991.3537181446568; Fri, 23 Nov 2018 06:51:31 -0800 (PST) Received: from localhost ([::1]:52778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCnp-00052N-Ff for importer@patchew.org; Fri, 23 Nov 2018 09:51:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCig-0007yY-T5 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCif-0003AS-Oc for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:10 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCif-00038g-HQ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: by mail-wm1-x343.google.com with SMTP id k198so12261561wmd.3 for ; Fri, 23 Nov 2018 06:46:08 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LVTH7A9iopjvf2drxrX25J5edqtzezG4K/9PFSj6hBg=; b=GXAQFiFfHEr+5Kj6xpKsuBuDkpHG6NMlZ4VPMXf788gjNc+Oai1tJrOdV5N+5IHZ5F 56AIt0Fz37CfMmcZPKQAyNvxNhtq0arfOTAEq7ZkGVOgpnS8zlxJTQkuHhzmVgPYX6TK fpJM1L5cPGgpocBK1D6vMBnP7pVE4LM7Kp36c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LVTH7A9iopjvf2drxrX25J5edqtzezG4K/9PFSj6hBg=; b=ubcomIvNgGxsSmgBHRNSAi61RGTQ0Kjj2kBkkUj5JIm/E+Jk0KZIm/TETU0YB1/f0X L7fK3ExqQIr8VpxMhzSnGU3qv/3I0luJZRIQbDp7PFM5fM071N/BUmVx7i1NELwUml3d 2k8R0euhMrwnMgclni1A2Xd6SeiTSd9Fix2lfX1MpMTWE8T5XHN6BTj0AIlmexxujeO0 StL8CD7B/oCXe1IpJiAWEatyxrcorjQmB2BuO4m1ulhCGJ1c1eqcYdWpXhs2+6MhvysS zWk4owKM3i7caJ3N2ziECmG1RU+EIg8bzoLE1MMvoz5fTzI+b8IAdyp2pFx2QNO0dXmz hq3A== X-Gm-Message-State: AA+aEWaBHiARpjzFPK4Y4wVvNMl9D/wNjCRoixVzu8C2nx//m65Zz1fO hliD2PLHBc33n68zSjtmVjX3ewf42irccQ== X-Google-Smtp-Source: AJdET5fOZG45P2xF2gZsnkT9yUtoero/kTpKTcXtFQZgOp/v4yvyyYEPyXa6YBX3Ah+KjXXeiVdxPA== X-Received: by 2002:a1c:b7c1:: with SMTP id h184-v6mr14083142wmf.33.1542984367389; Fri, 23 Nov 2018 06:46:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:28 +0100 Message-Id: <20181123144558.5048-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 07/37] tcg/i386: Change TCG_REG_L[01] to not overlap function arguments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will shortly be forcing qemu_ld/st arguments into registers that match the function call abi of the host, which means that the temps must be elsewhere. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3234a8d8bf..07df4b2b12 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -121,12 +121,16 @@ static const int tcg_target_call_oarg_regs[] =3D { #define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_WSZ 0x800 =20 -/* Registers used with L constraint, which are the first argument - registers on x86_64, and two random call clobbered registers on - i386. */ +/* Registers used with L constraint, which are two random + * call clobbered registers. These should be free. + */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] +# define TCG_REG_L0 TCG_REG_RAX +# ifdef _WIN64 +# define TCG_REG_L1 TCG_REG_R10 +# else +# define TCG_REG_L1 TCG_REG_RDI +# endif #else # define TCG_REG_L0 TCG_REG_EAX # define TCG_REG_L1 TCG_REG_EDX @@ -1628,6 +1632,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, unsigned a_mask =3D (1 << a_bits) - 1; unsigned s_mask =3D (1 << s_bits) - 1; target_ulong tlb_mask; + TCGReg base; =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { if (TARGET_LONG_BITS =3D=3D 64) { @@ -1674,7 +1679,12 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ - tcg_out_mov(s, ttype, r1, addrlo); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + base =3D tcg_target_call_iarg_regs[1]; + } else { + base =3D r1; + } + tcg_out_mov(s, ttype, base, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1693,11 +1703,11 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, =20 /* TLB Hit. */ =20 - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + /* add addend(r0), base */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, base, r0, offsetof(CPUTLBEntry, addend) - which); =20 - return r1; + return base; } =20 /* --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985223143455.9986091506303; Fri, 23 Nov 2018 07:00:23 -0800 (PST) Received: from localhost ([::1]:52827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCwP-0005cW-LR for importer@patchew.org; Fri, 23 Nov 2018 10:00:21 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43907) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCij-00080S-Pr for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCig-0003BO-9c for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:36671) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCig-00039W-0i for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:10 -0500 Received: by mail-wm1-x341.google.com with SMTP id s11so12262538wmh.1 for ; Fri, 23 Nov 2018 06:46:09 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V5pHnTSnR5PCVaavqferbtjCEb5UujC1bIeJMyb+BuI=; b=TTqJjoplBL6nvqoXGZn52nCobTtG/K872FAjHK9FXpeH9dY6apOZZVUll6z4K/TTyp CmFAcH255lpwWYDN7QG1Mqc3+neLDQzE9Pv06Xsow5Q1qDx3h03ikgMRa8bssVNhV5oq 7jmSmqXuUNjW3IvHvL4ocOvFUalPZYbjb+c90= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V5pHnTSnR5PCVaavqferbtjCEb5UujC1bIeJMyb+BuI=; b=PyAmn63kXgTHqqo0R86fbLXd+5L2nhOJkgIyRN8iAHh6UFSbIz+fKONdzqkL3yBOfX Km7tdNln7uQIIU6Zymw9VBLBn5HBeIk1fw3tk9eTAmb2EtCDfF1zGYXjG2oP7/WkVuZU kv2xdg4xvTLKdBN4XmigYV8/tFJoO3AR3IVBs07TwImaPoknNaP42s38igjaiS3dYqTX DC2tnpjexYSLS1JBw7Gm3CHbKSllC3kotyfMI2f2FkEtfQpEeelD9+5oRZUsMaelzKZx /Feuzu7lN4S6RplojdgtEbyZ4vBM651aQpa9zN+3Q3xKIepfvo2oTh0LXivyx6tTKF0g uVRg== X-Gm-Message-State: AGRZ1gLLor/gdQGQ6Z+3R270krK3mhJg0Nx9Vc3KEgjCCHyQDayHFv+a ffGza382hvvRgtZFWDWWP1S8Co2JhIdZuQ== X-Google-Smtp-Source: AJdET5ffD8ifIa9N4pF3ZoBV59N4Fwyqqy+fw+qNq9Xd3Q48JpWXODKNRGgYIon9qF1mlHlYUSzbTg== X-Received: by 2002:a1c:4108:: with SMTP id o8mr13548805wma.91.1542984368404; Fri, 23 Nov 2018 06:46:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:29 +0100 Message-Id: <20181123144558.5048-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 08/37] tcg/i386: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 203 +++++++++++++++++++++++++++++++------- 1 file changed, 169 insertions(+), 34 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 07df4b2b12..50e5dc31b3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -171,6 +171,80 @@ static bool have_lzcnt; =20 static tcg_insn_unit *tb_ret_addr; =20 +typedef enum { + ARG_ADDR, + ARG_STVAL, + ARG_LDVAL, +} QemuMemArgType; + +#ifdef CONFIG_SOFTMMU +/* + * Constraint to choose a particular register. This is used for softmmu + * loads and stores. Registers with no assignment get an empty string. + */ +static const char * const one_reg_constraint[TCG_TARGET_NB_REGS] =3D { + [TCG_REG_EAX] =3D "a", + [TCG_REG_EBX] =3D "b", + [TCG_REG_ECX] =3D "c", + [TCG_REG_EDX] =3D "d", + [TCG_REG_ESI] =3D "S", + [TCG_REG_EDI] =3D "D", +#if TCG_TARGET_REG_BITS =3D=3D 64 + [TCG_REG_R8] =3D "E", + [TCG_REG_R9] =3D "N", +#endif +}; + +/* + * Calling convention for the softmmu load and store thunks. + * + * For 64-bit, we mostly use the host calling convention, therefore the + * real first argument is reserved for the ENV parameter that is passed + * on to the slow path helpers. + * + * For 32-bit, the host calling convention is stack based; we invent a + * private convention that uses 4 of the 6 available host registers. + * We reserve EAX and EDX as temporaries for use by the thunk, we require + * INDEX_op_qemu_st_i32 to have a 'q' register from which to store, and + * further complicate this last by wanting a call-clobbered for that store. + * The 'q' requirement allows MO_8 stores at all; the call-clobbered part + * allows bswap to operate in-place, clobbering the input. + */ +static TCGReg softmmu_arg(QemuMemArgType type, bool is_64, int hi) +{ + switch (type) { + case ARG_ADDR: + tcg_debug_assert(!hi || TARGET_LONG_BITS > TCG_TARGET_REG_BITS); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + return tcg_target_call_iarg_regs[1]; + } else { + return hi ? TCG_REG_EDI : TCG_REG_ESI; + } + case ARG_STVAL: + tcg_debug_assert(!hi || (TCG_TARGET_REG_BITS =3D=3D 32 && is_64)); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + return tcg_target_call_iarg_regs[2]; + } else { + return hi ? TCG_REG_EBX : TCG_REG_ECX; + } + case ARG_LDVAL: + tcg_debug_assert(!hi || (TCG_TARGET_REG_BITS =3D=3D 32 && is_64)); + return tcg_target_call_oarg_regs[hi]; + } + g_assert_not_reached(); +} + +static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, in= t hi) +{ + return one_reg_constraint[softmmu_arg(type, is_64, hi)]; +} +#else +static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, in= t hi) +{ + return "L"; +} +#endif /* CONFIG_SOFTMMU */ + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -1680,11 +1754,15 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { - base =3D tcg_target_call_iarg_regs[1]; + tcg_debug_assert(addrlo =3D=3D tcg_target_call_iarg_regs[1]); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, addrlo, addrlo); + } + base =3D addrlo; } else { base =3D r1; + tcg_out_mov(s, ttype, base, addrlo); } - tcg_out_mov(s, ttype, base, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -2009,16 +2087,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, common. */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) =3D -1; + TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; TCGMemOp opc; + int i =3D -1; =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; + datalo =3D args[++i]; + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + datahi =3D args[++i]; + } + addrlo =3D args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi =3D args[++i]; + } + oi =3D args[++i]; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) @@ -2027,6 +2111,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; =20 + tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_LDVAL, is64, 0)); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_LDVAL, is64, 1)= ); + } + tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); + } + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_read= )); =20 @@ -2149,16 +2242,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) =3D -1; + TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; TCGMemOp opc; + int i =3D -1; =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; + datalo =3D args[++i]; + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + datahi =3D args[++i]; + } + addrlo =3D args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi =3D args[++i]; + } + oi =3D args[++i]; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) @@ -2167,6 +2266,15 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; =20 + tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_STVAL, is64, 0)); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_STVAL, is64, 1)= ); + } + tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); + } + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_writ= e)); =20 @@ -2836,15 +2944,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) static const TCGTargetOpDef r_r_re =3D { .args_ct_str =3D { "r", "r", = "re" } }; static const TCGTargetOpDef r_0_re =3D { .args_ct_str =3D { "r", "0", = "re" } }; static const TCGTargetOpDef r_0_ci =3D { .args_ct_str =3D { "r", "0", = "ci" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; static const TCGTargetOpDef x_x =3D { .args_ct_str =3D { "x", "x" } }; static const TCGTargetOpDef x_x_x =3D { .args_ct_str =3D { "x", "x", "= x" } }; static const TCGTargetOpDef x_x_x_x @@ -3026,17 +3125,53 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) } =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + { + static TCGTargetOpDef ld32; + int i; + + ld32.args_ct_str[0] =3D constrain_memop_arg(ARG_LDVAL, 0, 0); + for (i =3D 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i)= { + ld32.args_ct_str[i + 1] =3D constrain_memop_arg(ARG_ADDR, = 0, i); + } + return &ld32; + } case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + { + static TCGTargetOpDef ld64; + int i, j =3D 0; + + for (i =3D 0; i * TCG_TARGET_REG_BITS < 64; ++i) { + ld64.args_ct_str[j++] =3D constrain_memop_arg(ARG_LDVAL, 1= , i); + } + for (i =3D 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i)= { + ld64.args_ct_str[j++] =3D constrain_memop_arg(ARG_ADDR, 0,= i); + } + return &ld64; + } + case INDEX_op_qemu_st_i32: + { + static TCGTargetOpDef st32; + int i; + + st32.args_ct_str[0] =3D constrain_memop_arg(ARG_STVAL, 0, 0); + for (i =3D 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i)= { + st32.args_ct_str[i + 1] =3D constrain_memop_arg(ARG_ADDR, = 0, i); + } + return &st32; + } case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &L_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + { + static TCGTargetOpDef st64; + int i, j =3D 0; + + for (i =3D 0; i * TCG_TARGET_REG_BITS < 64; ++i) { + st64.args_ct_str[j++] =3D constrain_memop_arg(ARG_STVAL, 1= , i); + } + for (i =3D 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i)= { + st64.args_ct_str[j++] =3D constrain_memop_arg(ARG_ADDR, 0,= i); + } + return &st64; + } =20 case INDEX_op_brcond2_i32: { --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985216965759.4565829770213; Fri, 23 Nov 2018 07:00:16 -0800 (PST) Received: from localhost ([::1]:52824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCwJ-0005WM-Eb for importer@patchew.org; Fri, 23 Nov 2018 10:00:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43991) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCio-00085u-Ez for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCih-0003DI-Bc for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:18 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCih-0003Bn-0e for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: by mail-wm1-x342.google.com with SMTP id j207so5042306wmj.1 for ; Fri, 23 Nov 2018 06:46:10 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EcT4jjYW2sEeAnKGx9+I7bAH1gthrHWnSv8affH5DRQ=; b=IxZTQKmVeEl3+Kx9cesC2lSF2E0aoZSyoDrr1224efJ9rTOqMGOdtMe3PidhfZtLki BRp8dkIIE5PZrQIpWnGFrNT2CuQ56N0MKCpDRK5n75i9YR5g2WcffNsQw6FBjwPBtdvg OcrCHpGCs15I24GdyuD8TPVTqqeGKA2P7G6CQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EcT4jjYW2sEeAnKGx9+I7bAH1gthrHWnSv8affH5DRQ=; b=an9eqfTLBwYDjm9rvi06w6M2/+lF0KIN7Lh73mShN4Y2II09l14nJOjmULwow7k3BY Ct48Vs3XZJZmijsT5jv4hv+CaRSQ8KAQz81q90B8fW9FHT7dVLs3dJN0uGM7KmO8anLg HpDJaqrEtH0eJ0Keu/gnlJu1dDPMYe9u1XE+BeRcIIg5GHSJH7VaIgTZL9Iuu9zyk6z3 ld0Gotu1kCcAjXmZDHtkYy6R2qWrgHQrNkh61kJfgpvJjIN9g7vz9pbGJYpqRZt2R3NL yt/8udfcb8yexC+vTgpGJzuz0YNdsHJMGDtwY8SA9ehjCEhD62yli3xr34/i4d5IksJf ZexA== X-Gm-Message-State: AGRZ1gLVLVgTtqO7fn8qJQonK97SeqEUxvcauDpNkFZZsreWKO3XZZH6 CDtiemgnb9gaMgV36bQbdR2vLWMal1v2gQ== X-Google-Smtp-Source: AFSGD/WnmR2x9JHUyVlOh8LsrZCgwu/hlGCMtZ7iTsMFZiRSSzX2HYpsNtKTEbMq0PH0rB8t5fbSow== X-Received: by 2002:a7b:c397:: with SMTP id s23mr13570418wmj.127.1542984369254; Fri, 23 Nov 2018 06:46:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:30 +0100 Message-Id: <20181123144558.5048-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 09/37] tcg/i386: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the entire memory operation out of line. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 391 ++++++++++++++++---------------------- 2 files changed, 162 insertions(+), 231 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..1b2d4e1b0d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -220,7 +220,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 50e5dc31b3..5c68cbd43d 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1643,7 +1643,7 @@ static void tcg_out_nopn(TCGContext *s, int n) } =20 #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1656,6 +1656,14 @@ static void * const qemu_ld_helpers[16] =3D { [MO_BEUW] =3D helper_be_lduw_mmu, [MO_BEUL] =3D helper_be_ldul_mmu, [MO_BEQ] =3D helper_be_ldq_mmu, + + [MO_SB] =3D helper_ret_ldsb_mmu, + [MO_LESW] =3D helper_le_ldsw_mmu, + [MO_BESW] =3D helper_be_ldsw_mmu, +#if TCG_TARGET_REG_BITS =3D=3D 64 + [MO_LESL] =3D helper_le_ldsl_mmu, + [MO_BESL] =3D helper_be_ldsl_mmu, +#endif }; =20 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, @@ -1765,18 +1773,18 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, } =20 /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + tcg_out_opc(s, OPC_JCC_short + JCC_JNE, 0, 0, 0); label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 4; + s->code_ptr +=3D 1; =20 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { /* cmp 4(r0), addrhi */ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4); =20 /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + tcg_out_opc(s, OPC_JCC_short + JCC_JNE, 0, 0, 0); label_ptr[1] =3D s->code_ptr; - s->code_ptr +=3D 4; + s->code_ptr +=3D 1; } =20 /* TLB Hit. */ @@ -1788,181 +1796,6 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, return base; } =20 -/* - * Record the context of a call to the out of line helper code for the slo= w path - * for a load or store, so that we can later generate the correct helper c= ode - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D raddr; - label->label_ptr[0] =3D label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - -/* - * Generate code for the slow path for a load at the end of block - */ -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); - TCGReg data_reg; - tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - data_reg =3D l->datalo_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW); - break; - case MO_SW: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW); - break; -#if TCG_TARGET_REG_BITS =3D=3D 64 - case MO_SL: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; -#endif - case MO_UB: - case MO_UW: - /* Note that the helpers have zero-extended to tcg_target_long. */ - case MO_UL: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; - case MO_Q: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg =3D=3D TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } - break; - default: - tcg_abort(); - } - - /* Jump to the code corresponding to next IR of qemu_st */ - tcg_out_jmp(s, l->raddr); -} - -/* - * Generate code for the slow path for a store at the end of block - */ -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; - tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - TCGReg retaddr; - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (s_bits =3D=3D MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - retaddr =3D TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr =3D tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr =3D TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); -} #elif defined(__x86_64__) && defined(__linux__) # include # include @@ -2091,7 +1924,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) TCGReg datahi __attribute__((unused)) =3D -1; TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; - TCGMemOp opc; int i =3D -1; =20 datalo =3D args[++i]; @@ -2103,35 +1935,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) addrhi =3D args[++i]; } oi =3D args[++i]; - opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - { - int mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr[2]; - TCGReg base; - - tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_LDVAL, is64, 0)); - if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { - tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_LDVAL, is64, 1)= ); - } - tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); - } - - base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read= )); - - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Assert that we've set up the constraints properly. */ + tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_LDVAL, is64, 0)); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_LDVAL, is64, 1)); } + tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); + } + + /* Call to thunk. */ + tcg_out8(s, OPC_CALL_Jz); + add_ldst_ool_label(s, true, is64, oi, R_386_PC32, -4); + s->code_ptr +=3D 4; #else { + TCGMemOp opc =3D get_memop(oi); int32_t offset =3D guest_base; TCGReg base =3D addrlo; int index =3D -1; @@ -2246,7 +2068,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) TCGReg datahi __attribute__((unused)) =3D -1; TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; - TCGMemOp opc; int i =3D -1; =20 datalo =3D args[++i]; @@ -2258,35 +2079,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) addrhi =3D args[++i]; } oi =3D args[++i]; - opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - { - int mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr[2]; - TCGReg base; - - tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_STVAL, is64, 0)); - if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { - tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_STVAL, is64, 1)= ); - } - tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); - } - - base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_writ= e)); - - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Assert that we've set up the constraints properly. */ + tcg_debug_assert(datalo =3D=3D softmmu_arg(ARG_STVAL, is64, 0)); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D softmmu_arg(ARG_STVAL, is64, 1)); } + tcg_debug_assert(addrlo =3D=3D softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(ARG_ADDR, 0, 1)); + } + + /* Call to thunk. */ + tcg_out8(s, OPC_CALL_Jz); + add_ldst_ool_label(s, false, is64, oi, R_386_PC32, -4); + s->code_ptr +=3D 4; #else { + TCGMemOp opc =3D get_memop(oi); int32_t offset =3D guest_base; TCGReg base =3D addrlo; int seg =3D 0; @@ -2321,6 +2132,126 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) #endif } =20 +#if defined(CONFIG_SOFTMMU) +/* + * Generate code for an out-of-line thunk performing a load. + */ +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGMemOp opc =3D get_memop(oi); + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *label_ptr[2], *thunk; + TCGReg datalo, addrlo, base; + TCGReg datahi __attribute__((unused)) =3D -1; + TCGReg addrhi __attribute__((unused)) =3D -1; + int i; + + /* Since we're amortizing the cost, align the thunk. */ + thunk =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 16); + if (thunk !=3D s->code_ptr) { + memset(s->code_ptr, 0x90, thunk - s->code_ptr); + s->code_ptr =3D thunk; + } + + /* Discover where the inputs are held. */ + addrlo =3D softmmu_arg(ARG_ADDR, 0, 0); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi =3D softmmu_arg(ARG_ADDR, 0, 1); + } + datalo =3D softmmu_arg(is_ld ? ARG_LDVAL : ARG_STVAL, is_64, 0); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is_64) { + datahi =3D softmmu_arg(is_ld ? ARG_LDVAL : ARG_STVAL, is_64, 1); + } + + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + + /* TLB Hit. */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); + } else { + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); + } + tcg_out_opc(s, OPC_RET, 0, 0, 0); + + /* TLB Miss. */ + + /* resolve label address */ + tcg_patch8(label_ptr[0], s->code_ptr - label_ptr[0] - 1); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_patch8(label_ptr[1], s->code_ptr - label_ptr[1] - 1); + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Copy the return address into a temporary. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_ESP, 0); + i =3D 4; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, i); + i +=3D 4; + + tcg_out_st(s, TCG_TYPE_I32, addrlo, TCG_REG_ESP, i); + i +=3D 4; + + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_st(s, TCG_TYPE_I32, addrhi, TCG_REG_ESP, i); + i +=3D 4; + } + + if (!is_ld) { + tcg_out_st(s, TCG_TYPE_I32, datalo, TCG_REG_ESP, i); + i +=3D 4; + + if (is_64) { + tcg_out_st(s, TCG_TYPE_I32, datahi, TCG_REG_ESP, i); + i +=3D 4; + } + } + + tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, i); + i +=3D 4; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_ESP, i); + } else { + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); + + /* The address and data values have been placed by constraints. */ + tcg_debug_assert(addrlo =3D=3D tcg_target_call_iarg_regs[1]); + if (is_ld) { + i =3D 2; + } else { + tcg_debug_assert(datalo =3D=3D tcg_target_call_iarg_regs[2]); + i =3D 3; + } + + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[i++], oi); + + /* Copy the return address from the stack to the rvalue argument. + * WIN64 runs out of argument registers for stores. + */ + if (i < (int)ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[i], + TCG_REG_ESP, 0); + } else { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_RAX, TCG_REG_ESP, 0); + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_RAX, TCG_REG_ESP, + TCG_TARGET_CALL_STACK_OFFSET + 8); + } + } + + /* Tail call to the helper. */ + if (is_ld) { + tcg_out_jmp(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + } else { + tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + } + + return thunk; +} +#endif + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984783780422.8219292020393; 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Fri, 23 Nov 2018 06:46:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:31 +0100 Message-Id: <20181123144558.5048-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 10/37] tcg/aarch64: Add constraints for x0, x1, x2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.inc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 30091f6a69..148de0b7f2 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -125,6 +125,18 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, const char *ct_str, TCGType typ= e) { switch (*ct_str++) { + case 'a': /* x0 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X0); + break; + case 'b': /* x1 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X1); + break; + case 'c': /* x2 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X2); + break; case 'r': /* general registers */ ct->ct |=3D TCG_CT_REG; ct->u.regs |=3D 0xffffffffu; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984872181618.0595214735214; Fri, 23 Nov 2018 06:54:32 -0800 (PST) Received: from localhost ([::1]:52794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCqk-0008JY-Jo for importer@patchew.org; Fri, 23 Nov 2018 09:54:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCik-00081H-O8 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCij-0003FT-20 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:14 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCii-0003EC-Li for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:12 -0500 Received: by mail-wm1-x343.google.com with SMTP id c126so12185456wmh.0 for ; Fri, 23 Nov 2018 06:46:12 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2ItTk51JTjzE0w3i+PlYwVgMsWgaDFle4WWcoNcT4uk=; b=R9VQioAgkT3IKg7jr8Fh2DVC2XXIsU8BxUtEYM000t9M92rnkww6m1J1EVRNParVuO CgssDbJpm4HhnzG5hIceug0qlayr/j0VVKbdS3w14dwBoKg4TLxekSyK85sEU8dkTQtz vXqkmFcQqvzPMvI64KBw3u1JWk3/svsC2KzyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2ItTk51JTjzE0w3i+PlYwVgMsWgaDFle4WWcoNcT4uk=; b=MrF119ufVcyXkF8szI52rSQtrlJexPxPk30OVmRLhM87d4e5pLX0tni3AiYqUFPoQl pSDyF2xNllsjA0vR2NFOrB/mOwv7WFD2qYhxOvKotzVBs/S793VyCw583hA2ciXDkIxr tSh2UCYthNtU8Nf7WoFq/j1RkMJeIXlV/8Cr2lMUSsZVhA3SH6/I1Ysaj4Luc2sI8IWU UD5GHzsrqshotfNZ69IHCZ2Jq6vVGj5r0swD6RC4CnsNymxo5+/idQ/0f8fxLTJR/6IM qFG4a+zAMWpfbgm3Me9pd1TssTuuiMAw64WZg0JPEnSKaumqRc3gNzfZEkLxZbyOyq0q +JfQ== X-Gm-Message-State: AA+aEWZRs/XMBYOHL67XRBbfEevavoqtUTjwZ31FAQamJRrffgAFM7oY 3qzUNDW69N7ZOfOBAv6Ezemm23QIq8bTPw== X-Google-Smtp-Source: AJdET5f/ybBbWwK7PW03jFk/AMF/v6FO51FDw8vheMf2POBXG6O3XsLB9d/Igm6eWEHL7H+JU/tNRA== X-Received: by 2002:a7b:c095:: with SMTP id r21mr14186195wmh.118.1542984371179; Fri, 23 Nov 2018 06:46:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:32 +0100 Message-Id: <20181123144558.5048-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 11/37] tcg/aarch64: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.inc.c | 74 +++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 148de0b7f2..c0ba9a6d50 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1467,13 +1467,15 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finali= zing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) +/* + * Load and compare a TLB entry, emitting the conditional jump to the + * slow path on failure. Returns the register for the host addend. + * Clobbers t0, t1, t2, t3. + */ +static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp op= c, + tcg_insn_unit **label_ptr, int mem_index, + bool is_read, TCGReg t0, TCGReg t1, + TCGReg t2, TCGReg t3) { int tlb_offset =3D is_read ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) @@ -1491,55 +1493,56 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, if (a_bits >=3D s_bits) { x3 =3D addr_reg; } else { + x3 =3D t3; tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 =3D TCG_REG_X3; + x3, addr_reg, s_mask - a_mask); } tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; =20 - /* Extract the TLB index from the address into X0. - X0 =3D + /* Extract the TLB index from the address into T0. + T0 =3D addr_reg */ - tcg_out_ubfm(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, addr_reg, + tcg_out_ubfm(s, TARGET_LONG_BITS =3D=3D 64, t0, addr_reg, TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS); =20 - /* Store the page mask part of the address into X3. */ + /* Store the page mask part of the address into T3. */ tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, tlb_mask); + t3, x3, tlb_mask); =20 - /* Add any "high bits" from the tlb offset to the env address into X2, + /* Add any "high bits" from the tlb offset to the env address into T2, to take advantage of the LSL12 form of the ADDI instruction. - X2 =3D env + (tlb_offset & 0xfff000) */ + T2 =3D env + (tlb_offset & 0xfff000) */ if (tlb_offset & 0xfff000) { - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_X2, base, + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, t2, base, tlb_offset & 0xfff000); - base =3D TCG_REG_X2; + base =3D t2; } =20 - /* Merge the tlb index contribution into X2. - X2 =3D X2 + (X0 << CPU_TLB_ENTRY_BITS) */ - tcg_out_insn(s, 3502S, ADD_LSL, TCG_TYPE_I64, TCG_REG_X2, base, - TCG_REG_X0, CPU_TLB_ENTRY_BITS); + /* Merge the tlb index contribution into T2. + T2 =3D T2 + (T0 << CPU_TLB_ENTRY_BITS) */ + tcg_out_insn(s, 3502S, ADD_LSL, TCG_TYPE_I64, + t2, base, t0, CPU_TLB_ENTRY_BITS); =20 - /* Merge "low bits" from tlb offset, load the tlb comparator into X0. - X0 =3D load [X2 + (tlb_offset & 0x000fff)] */ + /* Merge "low bits" from tlb offset, load the tlb comparator into T0. + T0 =3D load [T2 + (tlb_offset & 0x000fff)] */ tcg_out_ldst(s, TARGET_LONG_BITS =3D=3D 32 ? I3312_LDRW : I3312_LDRX, - TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff, - TARGET_LONG_BITS =3D=3D 32 ? 2 : 3); + t0, t2, tlb_offset & 0xfff, TARGET_LONG_BITS =3D=3D 32 ? = 2 : 3); =20 /* Load the tlb addend. Do that early to avoid stalling. - X1 =3D load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */ - tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2, + T1 =3D load [T2 + (tlb_offset & 0xfff) + offsetof(addend)] */ + tcg_out_ldst(s, I3312_LDRX, t1, t2, (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) - (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)), 3); =20 /* Perform the address comparison. */ - tcg_out_cmp(s, (TARGET_LONG_BITS =3D=3D 64), TCG_REG_X0, TCG_REG_X3, 0= ); + tcg_out_cmp(s, (TARGET_LONG_BITS =3D=3D 64), t0, t3, 0); =20 /* If not equal, we jump to the slow path. */ *label_ptr =3D s->code_ptr; tcg_out_goto_cond_noaddr(s, TCG_COND_NE); + + return t1; } =20 #endif /* CONFIG_SOFTMMU */ @@ -1644,10 +1647,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; + TCGReg base; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); + base =3D tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1, + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3= ); tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); + base, otype, addr_reg); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1669,10 +1674,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; + TCGReg base; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); + base =3D tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0, + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3= ); + tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985426062556.2860822376556; Fri, 23 Nov 2018 07:03:46 -0800 (PST) Received: from localhost ([::1]:52847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCzg-00083d-F2 for importer@patchew.org; Fri, 23 Nov 2018 10:03:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCik-00081X-Vm for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 12/37] tcg/aarch64: Parameterize the temp for tcg_out_goto_long X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We cannot use TCG_REG_LR (aka TCG_REG_TMP) for tail calls. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.inc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c0ba9a6d50..ea5fe33fca 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1134,14 +1134,15 @@ static inline void tcg_out_goto(TCGContext *s, tcg_= insn_unit *target) tcg_out_insn(s, 3206, B, offset); } =20 -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target, + TCGReg scratch) { ptrdiff_t offset =3D target - s->code_ptr; if (offset =3D=3D sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, scratch, (intptr_t)target); + tcg_out_insn(s, 3207, BR, scratch); } } =20 @@ -1716,10 +1717,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 =3D=3D 0) { - tcg_out_goto_long(s, s->code_gen_epilogue); + tcg_out_goto_long(s, s->code_gen_epilogue, TCG_REG_TMP); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); - tcg_out_goto_long(s, tb_ret_addr); + tcg_out_goto_long(s, tb_ret_addr, TCG_REG_TMP); } break; =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985048024603.2377666905793; Fri, 23 Nov 2018 06:57:28 -0800 (PST) Received: from localhost ([::1]:52812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCta-0002Fq-CV for importer@patchew.org; Fri, 23 Nov 2018 09:57:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCio-00085T-4c for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCik-0003IY-RO for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:18 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:37536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCik-0003HE-L3 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:14 -0500 Received: by mail-wm1-x344.google.com with SMTP id p2-v6so12177621wmc.2 for ; Fri, 23 Nov 2018 06:46:14 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZgQoWHRJcRFp4C9KfWwThoalEdmTxoVA/RPtSMYllzE=; b=IO0lPlscYZimtQJ26EFSh6S+eEW6Zc8r8dMpVzjv8SKcV4NCG5qfwx7zPUtoI44WcV LdmtzqxvhhJQlohS1G7KOhDRPzHdLDwpIugVlPGyk8ZtVPB5mOyHhsp0rwu1L94edhV4 59SK759pIY7gziJNojCxeYhfvt/keSPgAE0yY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZgQoWHRJcRFp4C9KfWwThoalEdmTxoVA/RPtSMYllzE=; b=qyxSJ3aevbDoFrg9gNZ2oUA28ItUqyOCsWMTTpcWsrOQ+e79hqJECEwtI/m0BEb3Er VwsmvDwDPhJZlD0wzY5UwHZjKc20rmmQ3MXHVm1f+jZqKev55sYxuW683AzqrvPWP5c+ 5jZmqyq2OEz2bMxC+OMp9CVI77cTzSkfTxppyu8rP3jwqDtLCmY9iftbpnTC6x7LOhir imTleDI+FnmYuT3cTLnyBIA3moDaTcSrXocAnnBmYzk/vnWhvSv3ODdRS9MwP/WHz71y 5SkkdYLnTmG+E2quvt7apqs48wyK0WNHV42feUV/Qm7rhq3zH6j3/dsbJAibrqyOKc0q PIbw== X-Gm-Message-State: AA+aEWapGnRw35ufwSj8MpTENXDiBrSqkXNEmDLMfjptFrIl4l1TUT/d +t94m2fMM37vU/YNRpaI/QJoPzhkYq2OPw== X-Google-Smtp-Source: AJdET5f552Ci0Ff4xH0HfHcYO5wX1SUpDBNVjn45VlOpUtMNHT+gSrsqmaOaDlDN+5kDP1cT0RLOZw== X-Received: by 2002:a1c:7e8e:: with SMTP id z136mr15007888wmc.140.1542984373317; Fri, 23 Nov 2018 06:46:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:34 +0100 Message-Id: <20181123144558.5048-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 13/37] tcg/aarch64: Use B not BL for tcg_out_goto_long X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was a typo copying from tcg_out_call, apparently. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ea5fe33fca..403f5caf14 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1139,7 +1139,7 @@ static inline void tcg_out_goto_long(TCGContext *s, t= cg_insn_unit *target, { ptrdiff_t offset =3D target - s->code_ptr; if (offset =3D=3D sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); + tcg_out_insn(s, 3206, B, offset); } else { tcg_out_movi(s, TCG_TYPE_I64, scratch, (intptr_t)target); tcg_out_insn(s, 3207, BR, scratch); --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984733416721.1271682034392; Fri, 23 Nov 2018 06:52:13 -0800 (PST) Received: from localhost ([::1]:52782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCoV-0005bX-TW for importer@patchew.org; Fri, 23 Nov 2018 09:52:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCio-00085Q-42 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCim-0003L7-0b for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:18 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:55872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCil-0003JF-M5 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:15 -0500 Received: by mail-wm1-x341.google.com with SMTP id y139so12074837wmc.5 for ; Fri, 23 Nov 2018 06:46:15 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UrR/IldFdFkWy6ywHmFI8AClyOk1jWWQ8mWiO+LW0Iw=; b=FlGMdLNPO95E0P+uMYKw323F+PHb4hxhD2IsOtPI0rtna6KxRZcROdYXrhwG2TsWfw 5ghRcxSXdGYyqynzFqnr3IxU01N9kGcvVgnGvu2ocn7RHzZKZ7prUuCQeypryzcQ35Zj 7PpYuuwWPAh0nAwYEdJZmc1e514Se28xSDIeQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UrR/IldFdFkWy6ywHmFI8AClyOk1jWWQ8mWiO+LW0Iw=; b=XXIoOe/cezZhOReKPwYJdYOpc7ojwFAWBJIgpj9iROvv8uS5j1kQwKjFBPEdONyEry tdpxA9C38ZJS4+fcpGzU/AChb7Oia9zF2xeV9M92pChFeWUDzt1wKp8PuW5wYP9y1pSl Rzhu9kYhdlhZ3QBmskfwBA1PAecPLHFHnes2EkHZuAOyr3wAHFL5ghA0BzA3F2sbJt/B RVP+I1VQTDfcuVa+1gBCWWMn/gFObZ0/7hFaDm9R5yTEfzAmKkUQCr47PYqORfNbrdO1 BxWLNmkW5KUA3KlBdy23dOEq4mUo+/L/KQ532pDS20FWcW2gjgv/Wtr8z/kw9cz6EzBh 1iPQ== X-Gm-Message-State: AGRZ1gKODgLq5j1jRJZH6eMLcuzm3g9UqiskXLK+ZYMIW7B11PH+5zwe oPdHzVqt9+JN3MdsArIbwdkwyYj560toZQ== X-Google-Smtp-Source: AJdET5eWfWd+cbZuERfSdY+U/rWarjlwMtt3HqdJUbuVn2HpYCXHAs5jwf9gL3cxXVpbUZAUZS29TA== X-Received: by 2002:a1c:a13:: with SMTP id 19mr14069153wmk.81.1542984374230; Fri, 23 Nov 2018 06:46:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:35 +0100 Message-Id: <20181123144558.5048-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 14/37] tcg/aarch64: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 191 +++++++++++++++++------------------ 2 files changed, 93 insertions(+), 100 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 9aea1d1771..d1bd77c41d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -146,7 +146,7 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 403f5caf14..8edea527f7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -145,18 +145,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_REG; ct->u.regs |=3D 0xffffffff00000000ull; break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D 0xffffffffu; -#ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); -#endif - break; case 'A': /* Valid for arithmetic immediate (positive or negative). */ ct->ct |=3D TCG_CT_CONST_AIMM; break; @@ -1378,7 +1366,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, } =20 #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1391,6 +1379,12 @@ static void * const qemu_ld_helpers[16] =3D { [MO_BEUW] =3D helper_be_lduw_mmu, [MO_BEUL] =3D helper_be_ldul_mmu, [MO_BEQ] =3D helper_be_ldq_mmu, + + [MO_SB] =3D helper_ret_ldsb_mmu, + [MO_LESW] =3D helper_le_ldsw_mmu, + [MO_LESL] =3D helper_le_ldsl_mmu, + [MO_BESW] =3D helper_be_ldsw_mmu, + [MO_BESL] =3D helper_be_ldsl_mmu, }; =20 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, @@ -1407,67 +1401,6 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp size =3D opc & MO_SIZE; - - reloc_pc19(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - if (opc & MO_SIGN) { - tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); - } else { - tcg_out_mov(s, size =3D=3D MO_64, lb->datalo_reg, TCG_REG_X0); - } - - tcg_out_goto(s, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp size =3D opc & MO_SIZE; - - reloc_pc19(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - tcg_out_goto(s, lb->raddr); -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_= reg, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D raddr; - label->label_ptr[0] =3D label_ptr; -} - /* * Load and compare a TLB entry, emitting the conditional jump to the * slow path on failure. Returns the register for the host addend. @@ -1644,19 +1577,22 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, TCGMemOpIdx oi, TCGType ext) { TCGMemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base; =20 - base =3D tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1, - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3= ); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - base, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, - s->code_ptr, label_ptr); +#ifdef CONFIG_SOFTMMU + /* Ignore the requested "ext". We get the same correct result from + * a 16-bit sign-extended to 64-bit as we do sign-extended to 32-bit, + * and we create fewer out-of-line thunks. + */ + bool is_64 =3D (memop & MO_SIGN) || ((memop & MO_SIZE) =3D=3D MO_64); + + tcg_debug_assert(data_reg =3D=3D TCG_REG_X0); + tcg_debug_assert(addr_reg =3D=3D TCG_REG_X1); + + add_ldst_ool_label(s, true, is_64, oi, R_AARCH64_JUMP26, 0); + tcg_out_insn(s, 3206, BL, 0); #else /* !CONFIG_SOFTMMU */ + const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1671,18 +1607,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, TCGMemOpIdx oi) { TCGMemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base; =20 - base =3D tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0, - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3= ); - tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); +#ifdef CONFIG_SOFTMMU + bool is_64 =3D (memop & MO_SIZE) =3D=3D MO_64; + + tcg_debug_assert(addr_reg =3D=3D TCG_REG_X1); + tcg_debug_assert(data_reg =3D=3D TCG_REG_X2); + + add_ldst_ool_label(s, false, is_64, oi, R_AARCH64_JUMP26, 0); + tcg_out_insn(s, 3206, BL, 0); #else /* !CONFIG_SOFTMMU */ + const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1693,6 +1629,52 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, #endif /* CONFIG_SOFTMMU */ } =20 +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + const TCGMemOp memop =3D get_memop(oi); + const unsigned mem_index =3D get_mmuidx(oi); + const TCGReg addr_reg =3D TCG_REG_X1; + const TCGReg data_reg =3D is_ld ? TCG_REG_X0 : TCG_REG_X2; + tcg_insn_unit * const thunk =3D s->code_ptr; + tcg_insn_unit *label; + TCGReg base, arg; + + base =3D tcg_out_tlb_read(s, addr_reg, memop, &label, mem_index, is_ld, + TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7= ); + + /* TLB Hit */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, memop, is_64, data_reg, + base, otype, addr_reg); + } else { + tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); + } + tcg_out_insn(s, 3207, RET, TCG_REG_LR); + + /* TLB Miss */ + reloc_pc19(label, s->code_ptr); + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + /* addr_reg and data_reg are already in place. */ + arg =3D is_ld ? TCG_REG_X2 : TCG_REG_X3; + tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); + tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_REG_LR); + + if (is_ld) { + tcg_out_goto_long(s, qemu_ld_helpers[memop & (MO_BSWAP | MO_SSIZE)= ], + TCG_REG_X7); + } else { + tcg_out_goto_long(s, qemu_st_helpers[memop & (MO_BSWAP | MO_SIZE)], + TCG_REG_X7); + } + + return thunk; +} +#endif + static tcg_insn_unit *tb_ret_addr; =20 static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -2262,10 +2244,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) static const TCGTargetOpDef w_w =3D { .args_ct_str =3D { "w", "w" } }; static const TCGTargetOpDef w_r =3D { .args_ct_str =3D { "w", "r" } }; static const TCGTargetOpDef w_wr =3D { .args_ct_str =3D { "w", "wr" } = }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; - static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; +#ifdef CONFIG_SOFTMMU + static const TCGTargetOpDef a_b =3D { .args_ct_str =3D { "a", "b" } }; + static const TCGTargetOpDef c_b =3D { .args_ct_str =3D { "c", "b" } }; +#endif static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; static const TCGTargetOpDef w_w_wZ =3D { .args_ct_str =3D { "w", "w", = "wZ" } }; @@ -2397,10 +2381,19 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; +#ifdef CONFIG_SOFTMMU + return &a_b; +#else + return &r_r; +#endif + case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; +#ifdef CONFIG_SOFTMMU + return &c_b; +#else + return &r_r; +#endif =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 15/37] tcg/arm: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.inc.c | 89 +++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 43 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 80d174ef44..414c91c9ea 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1245,11 +1245,14 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGR= eg argreg, /* We're expecting to use an 8-bit immediate and to mask. */ QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); =20 -/* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - +/* + *Load and compare a TLB entry, leaving the flags set. Returns the regist= er + * containing the addend of the tlb entry. Clobbers t0, t1, t2, t3. + * T0 and T1 must be consecutive for LDRD. + */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - TCGMemOp opc, int mem_index, bool is_load) + TCGMemOp opc, int mem_index, bool is_load, + TCGReg t0, TCGReg t1, TCGReg t2, TCGReg t3) { TCGReg base =3D TCG_AREG0; int cmp_off =3D @@ -1262,36 +1265,37 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned a_bits =3D get_alignment_bits(opc); =20 /* V7 generates the following: - * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS - * add r2, env, #high - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr r0, [r2, #cmp] - * ldr r2, [r2, #add] - * movw tmp, #page_align_mask - * bic tmp, addrlo, tmp - * cmp r0, tmp + * ubfx t0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS + * add t2, env, #high + * add t2, t2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t2, [t2, #add] + * movw t3, #page_align_mask + * bic t3, addrlo, t3 + * cmp t0, t3 * * Otherwise we generate: - * shr tmp, addrlo, #TARGET_PAGE_BITS - * add r2, env, #high - * and r0, tmp, #(CPU_TLB_SIZE - 1) - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr r0, [r2, #cmp] - * ldr r2, [r2, #add] + * shr t3, addrlo, #TARGET_PAGE_BITS + * add t2, env, #high + * and t0, t3, #(CPU_TLB_SIZE - 1) + * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t2, [t2, #add] * tst addrlo, #s_mask - * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS + * cmpeq t0, t3, lsl #TARGET_PAGE_BITS */ if (use_armv7_instructions) { - tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo, + tcg_out_extract(s, COND_AL, t0, addrlo, TARGET_PAGE_BITS, CPU_TLB_BITS); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t3, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } =20 /* Add portions of the offset until the memory access is in range. * If we plan on using ldrd, reduce to an 8-bit offset; otherwise - * we can use a 12-bit offset. */ + * we can use a 12-bit offset. + */ if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { mask_off =3D 0xff; } else { @@ -1301,34 +1305,33 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, int shift =3D ctz32(cmp_off & ~mask_off) & ~1; int rot =3D ((32 - shift) << 7) & 0xf00; int addend =3D cmp_off & (0xff << shift); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t2, base, rot | ((cmp_off >> shift) & 0xff)); - base =3D TCG_REG_R2; + base =3D t2; add_off -=3D addend; cmp_off -=3D addend; } =20 if (!use_armv7_instructions) { - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t3, CPU_TLB_SIZE - 1); } - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, - TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, t2, base, t0, + SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); =20 /* Load the tlb comparator. Use ldrd if needed and available, but due to how the pointer needs setting up, ldm isn't useful. Base arm5 doesn't have ldrd, but armv5te does. */ if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); + tcg_out_ldrd_8(s, COND_AL, t0, t2, cmp_off); } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + = 4); + tcg_out_ld32_12(s, COND_AL, t1, t2, cmp_off + 4); } } =20 /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); =20 /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ @@ -1341,29 +1344,27 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, int rot =3D encode_imm(mask); =20 if (rot >=3D 0) {=20 - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t3, addrlo, rotl(mask, rot) | (rot << 7)); } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); + tcg_out_movi32(s, COND_AL, t3, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t3, addrlo, t3, 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t3, 0); } else { if (a_bits) { tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); } tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R0, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + 0, t0, t3, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } =20 if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t1, addrhi, 0); } =20 - return TCG_REG_R2; + return t2; } =20 /* Record the context of a call to the out of line helper code for the slow @@ -1629,7 +1630,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_= R14); =20 /* This a conditional BL only to load a pointer within this opcode int= o LR for the slow path. We will not be using the value for a tail call.= */ @@ -1760,7 +1762,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_= R14); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154298496168919.691652334051582; Fri, 23 Nov 2018 06:56:01 -0800 (PST) Received: from localhost ([::1]:52805 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCsB-00015W-QZ for importer@patchew.org; Fri, 23 Nov 2018 09:55:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCis-0008Gf-3n for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCio-0003Ng-4g for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:20 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36673) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCin-0003Ma-OT for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:17 -0500 Received: by mail-wm1-x343.google.com with SMTP id s11so12262861wmh.1 for ; Fri, 23 Nov 2018 06:46:17 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K9NRP+HhbIk1nF+G1KmKV31hLuf4u/VMHyrlWpIJenM=; b=E5tklL5hxeRc8zC2OHdv9x6CEOf0IAp7HTls4N/yLG9J9BTgGpvXZB2s/U8gJMic9k tSJ/DajIZSGdfb3SHX8ONcBIl8VeWalXE6iQ8IYeSim5v7KvrX4Dzdq41bYeMKQrR3xY VIvBSu58i8SSWo37MvI1CkoIvLqlXGw/ycQfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K9NRP+HhbIk1nF+G1KmKV31hLuf4u/VMHyrlWpIJenM=; b=jNyXBTUeNLfYT1EbeKWkItZnpVioLovv16+tvyh7osOotBqwNhtugcQmRZ4VUK26c4 yCRc4nuIFfpQOMCeWEuUe/6cG1vU5U0AlkIcn33CDBhOpZj4DNx2QZ5NbmiBTRbQRXfN OpZZBBdolKAqj6GxEE3NzoDSI2MuFDbo3A1heSPTjakImSVGFWGqBcflYEdfYwtFUxQZ hUWeGnW0AwQYdiNLr32YTHsXJJEnDYWvl2DMdblw2xSS747bY3jAfWp1lQ7IJb220DVu cAYMvH0nXBm3JtavFwpgkRc/V5oTvpSCHSyv3/vgKpFWFTAaR17oFz/th21z+eDLhf5D SKEA== X-Gm-Message-State: AA+aEWZ3ByGygYRMKz3T9zLcisx+gfAZELm/PPKn8HBh481je3yjNU2k ZHDeDboqY38HgN24/Krw7+xkzGDuvrbbCw== X-Google-Smtp-Source: AJdET5cBy2RoqpYb7l3JvAqRtJPcOk6XX0FuORjAU6s+41JOxCMsZxO5GzYrkSKNYJqh7Ijod24Vfg== X-Received: by 2002:a1c:3288:: with SMTP id y130-v6mr13537416wmy.11.1542984376329; Fri, 23 Nov 2018 06:46:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:37 +0100 Message-Id: <20181123144558.5048-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 16/37] tcg/arm: Add constraints for R0-R5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.inc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 414c91c9ea..4339c472e8 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -246,7 +246,12 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e) { - switch (*ct_str++) { + char c =3D *ct_str++; + switch (c) { + case 'a' ... 'f': /* r0 - r5 */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R0 + (c - 'a')); + break; case 'I': ct->ct |=3D TCG_CT_CONST_ARM; break; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154298568262775.27855157076556; Fri, 23 Nov 2018 07:08:02 -0800 (PST) Received: from localhost ([::1]:52874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD3k-0003CF-Au for importer@patchew.org; Fri, 23 Nov 2018 10:07:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCiv-0008Ui-UH for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCis-0003SS-7W for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:24 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37564) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiq-0003Nq-9G for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:22 -0500 Received: by mail-wr1-x443.google.com with SMTP id j10so12585832wru.4 for ; Fri, 23 Nov 2018 06:46:18 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IfteVwIt0QRdTAT9d1pABeNMo7np6fWushm//ba1JvM=; b=g1oiuvpgnRccF4d64LKl01YZBPEobjCeQmkwboWykH8/s4pya/BuT99VUsy9p7+Yfv trSFOs3vk7vr0X9M5hi09KrBzg8g10GdGSBxoKl35iWg8AS7i+CRxe/J0Vbz5emRKxIM S6vZp8Fw6AtULJchuV4Duv54M/4lc9ZX97gFw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IfteVwIt0QRdTAT9d1pABeNMo7np6fWushm//ba1JvM=; b=mN91md4tM+i+t8mJC6pX34DirVxCBWka/L0aZFaf3MV6vqBIqa+iQhEJFdLZkhea+T rA35HI9OH67efFWmPvbwF/2XOFFpp8sgLwZYL0jlPYTVbf8lQbfl6gGPRHP3Z7c98B7E l+Ky3cfa4pOOJ6Zdn3Jh+2WdQHpBUl5LIqcQ5K3kDJu59PDHTx5OxTKUsPKoR+F30Nyw zcPzMgVY92CyMN09MLAreNR+h+u2WLfOCMOMsc8NeMafGSxCOUbRbBfT8f/pl0BvR05X mnR/QENhFvgOb7j26mTEO8e0DEScUfltYk6JK1Fw1CtPJK51ZJrIR9AHka/TY/e5AwRs 3NLQ== X-Gm-Message-State: AA+aEWYd5hKJS+kaOGlfF39DU30ojK1k5loiN1FfUKOfQt4M3g4hol2U EfW1/Rp8DEXUBeog00Mr2HjSksjmOI9kVQ== X-Google-Smtp-Source: AFSGD/X7+NTG+fyPtu0wvVklTDZmH8LlAvrNaRlsejQBDh7tLnFkL4iUgGgS7ldxY4IFLFrRGwmv/A== X-Received: by 2002:adf:c888:: with SMTP id k8mr15338977wrh.6.1542984377475; Fri, 23 Nov 2018 06:46:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:38 +0100 Message-Id: <20181123144558.5048-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 17/37] tcg/arm: Reduce the number of temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When moving the qemu_ld/st thunk out of line, we no longer have LR for use as a temporary. In the worst case we must make do with 3 temps, when dealing with a 64-bit guest address. This in turn imples that we cannot use LDRD anymore, as there are not enough temps. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.inc.c | 97 ++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 44 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 4339c472e8..2deeb1f5d1 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1251,13 +1251,12 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGR= eg argreg, QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); =20 /* - *Load and compare a TLB entry, leaving the flags set. Returns the regist= er - * containing the addend of the tlb entry. Clobbers t0, t1, t2, t3. - * T0 and T1 must be consecutive for LDRD. + * Load and compare a TLB entry, leaving the flags set. Returns the regis= ter + * containing the addend of the tlb entry. Clobbers t0, t1, t2. */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TCGMemOp opc, int mem_index, bool is_load, - TCGReg t0, TCGReg t1, TCGReg t2, TCGReg t3) + TCGReg t0, TCGReg t1, TCGReg t2) { TCGReg base =3D TCG_AREG0; int cmp_off =3D @@ -1265,49 +1264,64 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); int add_off =3D offsetof(CPUArchState, tlb_table[mem_index][0].addend); - int mask_off; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 /* V7 generates the following: * ubfx t0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS * add t2, env, #high - * add t2, t2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] * ldr t2, [t2, #add] - * movw t3, #page_align_mask - * bic t3, addrlo, t3 - * cmp t0, t3 + * movw t1, #page_align_mask + * bic t1, addrlo, t1 + * cmp t0, t1 + * + * ubfx t0, addrlo, #TPB, #CTB -- 64-bit address + * add t2, env, #high + * add t2, t2, t0, lsl #CTEB + * ldr t0, [t2, #cmplo] + * movw t1, #page_align_mask + * bic t1, addrlo, t1 + * cmp t0, t1 + * ldr t0, [t2, #cmphi] + * ldr t2, [t2, #add] + * cmpeq t0, addrhi * * Otherwise we generate: * shr t3, addrlo, #TARGET_PAGE_BITS * add t2, env, #high * and t0, t3, #(CPU_TLB_SIZE - 1) * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS - * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t0, [t2, #cmp] * ldr t2, [t2, #add] * tst addrlo, #s_mask * cmpeq t0, t3, lsl #TARGET_PAGE_BITS + * + * shr t1, addrlo, #TPB -- 64-bit address + * add t2, env, #high + * and t0, t1, #CTS-1 + * add t2, t2, t0, lsl #CTEB + * ldr t0, [t2, #cmplo] + * tst addrlo, #s_mask + * cmpeq t0, t1, lsl #TBP + * ldr t0, [t2, #cmphi] + * ldr t2, [t2, #add] + * cmpeq t0, addrhi */ if (use_armv7_instructions) { tcg_out_extract(s, COND_AL, t0, addrlo, TARGET_PAGE_BITS, CPU_TLB_BITS); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t3, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t1, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } =20 /* Add portions of the offset until the memory access is in range. - * If we plan on using ldrd, reduce to an 8-bit offset; otherwise - * we can use a 12-bit offset. + * We are not using ldrd, so we can use a 12-bit offset. */ - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - mask_off =3D 0xff; - } else { - mask_off =3D 0xfff; - } - while (cmp_off > mask_off) { - int shift =3D ctz32(cmp_off & ~mask_off) & ~1; + while (cmp_off > 0xfff) { + int shift =3D ctz32(cmp_off & ~0xfff) & ~1; int rot =3D ((32 - shift) << 7) & 0xf00; int addend =3D cmp_off & (0xff << shift); tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t2, base, @@ -1318,25 +1332,13 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, } =20 if (!use_armv7_instructions) { - tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t3, CPU_TLB_SIZE - 1); + tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t1, CPU_TLB_SIZE - 1); } tcg_out_dat_reg(s, COND_AL, ARITH_ADD, t2, base, t0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); =20 - /* Load the tlb comparator. Use ldrd if needed and available, - but due to how the pointer needs setting up, ldm isn't useful. - Base arm5 doesn't have ldrd, but armv5te does. */ - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, t0, t2, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, t1, t2, cmp_off + 4); - } - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); + /* Load the tlb comparator (low part). */ + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); =20 /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ @@ -1349,24 +1351,31 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, int rot =3D encode_imm(mask); =20 if (rot >=3D 0) {=20 - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t3, addrlo, + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t1, addrlo, rotl(mask, rot) | (rot << 7)); } else { - tcg_out_movi32(s, COND_AL, t3, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t3, addrlo, t3, 0); + tcg_out_movi32(s, COND_AL, t1, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t1, addrlo, t1, 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t3, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t1, 0); } else { if (a_bits) { tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); } tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, t0, t3, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + 0, t0, t1, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } =20 + /* Load the tlb comparator (high part). */ if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t1, addrhi, 0); + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off + 4); + } + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); + + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t0, addrhi, 0); } =20 return t2; @@ -1636,7 +1645,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_= R14); + TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); =20 /* This a conditional BL only to load a pointer within this opcode int= o LR for the slow path. We will not be using the value for a tail call.= */ @@ -1768,7 +1777,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_= R14); + TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 154298569568856.2740844500197; Fri, 23 Nov 2018 07:08:15 -0800 (PST) Received: from localhost ([::1]:52875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD3x-0003dO-49 for importer@patchew.org; Fri, 23 Nov 2018 10:08:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EE-MI for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiw-0003XC-05 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:32860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCis-0003PG-2q for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:24 -0500 Received: by mail-wr1-x442.google.com with SMTP id c14so6955777wrr.0 for ; Fri, 23 Nov 2018 06:46:19 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XzP/1RMAHcHXzxJDoQwNYCK5LC+cbzzfmGI/RlU+HSs=; b=J98NTb6XbYxORmwvhZR4ARcl4L6phAArnXIU6gfW9CTcj/Os4+sIhFrltsbzzRtYWy AzvmEm5nUdQ/syDNAxC3XfitFClp+Dza6qeE9yEYCf9uxJ6Y6/FrZgF8DorhRQtzccjV XQF8cRxyldnllHVIIv04TcD8FiUaLYznzOXvg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XzP/1RMAHcHXzxJDoQwNYCK5LC+cbzzfmGI/RlU+HSs=; b=VcuPsxFaWvMHpRqHYoEFg6lOTC1AysU2o2ggsfcUTUi7S0xR0Cf3Wp0E64bWlZZvwP EsxQ3ODPjHwf/CTc4JtEkTdGlfFgs9X/d9nKdHcQZrRIGppZzkx0Tm30tKhbXpW0x1Qe JYUtVy8EFpDy4LVDfoxWc4rOtv6V+YwTgSRxeA/sQVI+vqbqsoySbcV2FRHErnG9ycgS BSIweNXHxZoZFLK+kVbpBJi2VBI2ZgEPQAur4BtsgZ0oUSHvIvx6IZIFkS6d0kw+LgYl VMqDbI68Jo91QrcjDAqPhuaWsRXHLnowLnSFgXQJJd4njsCc89kEovuRRAjkzyzYcZaA 6g6w== X-Gm-Message-State: AA+aEWZlGvVKfZ245PAUtRE8GYDI5NF8tUBJUw/WO6jlzQq5+urumNwH 5saPOumS2IUp7LaTXi9tirmKPM02WVDrpg== X-Google-Smtp-Source: AFSGD/W0f48ocm3/zYkpvWH2ZF/5G3DQ6N+vqS7+/a1Gc41FOPQ4F7/of2Mjg/OasBFMiDQ0hb4eFA== X-Received: by 2002:adf:8421:: with SMTP id 30mr14625931wrf.153.1542984378432; Fri, 23 Nov 2018 06:46:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:39 +0100 Message-Id: <20181123144558.5048-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 18/37] tcg/arm: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.inc.c | 113 +++++++++++++++++++++++++-------------- 1 file changed, 73 insertions(+), 40 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2deeb1f5d1..6b89ac7983 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -270,37 +270,13 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, ct->u.regs =3D 0xffff; break; =20 - /* qemu_ld address */ - case 'l': - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D 0xffff; -#ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif - break; - /* qemu_st address & data */ case 's': ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu o= nly) - and r0-r1 doing the byte swapping, so don't use these. */ + /* r0-r1 doing the byte swapping, so don't use these */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); -#if TARGET_LONG_BITS =3D=3D 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif break; =20 default: @@ -1630,8 +1606,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; + int mem_index, avail; + TCGReg addend, t0, t1; tcg_insn_unit *label_ptr; #endif =20 @@ -1644,8 +1620,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); + + avail =3D 0xf; + avail &=3D ~(1 << addrlo); + if (TARGET_LONG_BITS =3D=3D 64) { + avail &=3D ~(1 << addrhi); + } + tcg_debug_assert(avail & 1); + t0 =3D TCG_REG_R0; + avail &=3D ~1; + tcg_debug_assert(avail !=3D 0); + t1 =3D ctz32(avail); + addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); + t0, t1, TCG_REG_TMP); =20 /* This a conditional BL only to load a pointer within this opcode int= o LR for the slow path. We will not be using the value for a tail call.= */ @@ -1762,8 +1750,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; + int mem_index, avail; + TCGReg addend, t0, t1; tcg_insn_unit *label_ptr; #endif =20 @@ -1776,8 +1764,24 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); + + avail =3D 0xf; + avail &=3D ~(1 << addrlo); + avail &=3D ~(1 << datalo); + if (TARGET_LONG_BITS =3D=3D 64) { + avail &=3D ~(1 << addrhi); + } + if (is64) { + avail &=3D ~(1 << datahi); + } + tcg_debug_assert(avail & 1); + t0 =3D TCG_REG_R0; + avail &=3D ~1; + tcg_debug_assert(avail !=3D 0); + t1 =3D ctz32(avail); + addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); + t0, t1, TCG_REG_TMP); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); =20 @@ -2118,11 +2122,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; static const TCGTargetOpDef s_s =3D { .args_ct_str =3D { "s", "s" } }; - static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; + static const TCGTargetOpDef a_b =3D { .args_ct_str =3D { "a", "b" } }; + static const TCGTargetOpDef c_b =3D { .args_ct_str =3D { "c", "b" } }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_r_l =3D { .args_ct_str =3D { "r", "r", "= l" } }; - static const TCGTargetOpDef r_l_l =3D { .args_ct_str =3D { "r", "l", "= l" } }; static const TCGTargetOpDef s_s_s =3D { .args_ct_str =3D { "s", "s", "= s" } }; + static const TCGTargetOpDef a_c_d =3D { .args_ct_str =3D { "a", "c", "= d" } }; + static const TCGTargetOpDef a_b_b =3D { .args_ct_str =3D { "a", "b", "= b" } }; + static const TCGTargetOpDef e_c_d =3D { .args_ct_str =3D { "e", "c", "= d" } }; + static const TCGTargetOpDef e_f_b =3D { .args_ct_str =3D { "e", "f", "= b" } }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; static const TCGTargetOpDef r_r_rIN @@ -2131,10 +2138,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =3D { .args_ct_str =3D { "r", "r", "rIK" } }; static const TCGTargetOpDef r_r_r_r =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - =3D { .args_ct_str =3D { "r", "r", "l", "l" } }; static const TCGTargetOpDef s_s_s_s =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; + static const TCGTargetOpDef a_b_c_d + =3D { .args_ct_str =3D { "a", "b", "c", "d" } }; + static const TCGTargetOpDef e_f_c_d + =3D { .args_ct_str =3D { "e", "f", "c", "d" } }; static const TCGTargetOpDef br =3D { .args_ct_str =3D { "r", "rIN" } }; static const TCGTargetOpDef dep @@ -2215,13 +2224,37 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) return &setc2; =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &r_l : &r_l_l; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS =3D=3D 32 ? &r_r : &r_r_r; + } else if (TARGET_LONG_BITS =3D=3D 32) { + return &a_b; /* temps available r0, r2, r3, r12 */ + } else { + return &a_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &r_r_l : &r_r_l_l; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS =3D=3D 32 ? &r_r_r : &r_r_r_r; + } else if (TARGET_LONG_BITS =3D=3D 32) { + return &a_b_b; /* temps available r0, r2, r3, r12 */ + } else { + return &a_b_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + } else if (TARGET_LONG_BITS =3D=3D 32) { + return &c_b; /* temps available r0, r3, r12 */ + } else { + return &e_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; + } else if (TARGET_LONG_BITS =3D=3D 32) { + return &e_f_b; /* temps available r0, r2, r3, r12 */ + } else { + return &e_f_c_d; /* temps available r0, r1, r12 */ + } =20 default: return NULL; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985823744394.01168669904746; Fri, 23 Nov 2018 07:10:23 -0800 (PST) Received: from localhost ([::1]:52885 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD60-0006fB-DZ for importer@patchew.org; Fri, 23 Nov 2018 10:10:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EC-ME for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiw-0003XI-0d for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCis-0003PU-6u for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:24 -0500 Received: by mail-wr1-x444.google.com with SMTP id p4so12585272wrt.7 for ; Fri, 23 Nov 2018 06:46:20 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yJf+mKna6oyCQX+8QLpW7ASUSLIfMAQTCAnpD7BKT6k=; b=VwzHPYs9C7UuIY4KGMIrosfHyNAOJk4qyWtdTuO0VNDktUtWzsJE59Od+xWNw0B7K5 ghDzU3TUbuDsjCLf6a+1YMwN/ZZKZSr1l5ciG9TkPypbH5ctmWz8m0ahXKFsStBxO7+0 leDpaXZPovxkwM/wRgjU1hyMsBnrvoMvvX+Vk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yJf+mKna6oyCQX+8QLpW7ASUSLIfMAQTCAnpD7BKT6k=; b=Nq99cw6Rd2Af7hBAjrfrM4dh+0RAAYPbWws6NY/GepElwHfwFmw/mpDSazkxSOMD8W 9vt3JHpGkkGevf2S2WTg6Yu2fWGafu0qKih0CEXfGtKq80TyO72Vdta0FVDRMAAkpBE9 qcZRbtnvCSzKNnC65uJzeBwutuVjtjl5CRA9aW9JyZmNPVwZYjFt3IwhRQs8p/EjI/v2 ybfaCVaN3rRGapBK5XwI9toZAd3ILQ/D6Bd3EbOVHCMOz0U93KY1sj4BYE/SCyOqZ5jW f3p2WLadz3yOjEQ0e3kgN3TxSvrJ0nEVoX2aVf6iUzXgb4fLbr8HjjtO4FAjIH8MA2J9 +/JQ== X-Gm-Message-State: AA+aEWY/l5wapeSFinoeq4ucpdtviGSbd5kZqsLQB2OP1YNnjUDeBQNo vd1NJjgwCFXOe/47zGpMpxLzV5GR6Aav+g== X-Google-Smtp-Source: AFSGD/UvwbmY87zkV0HSMORmXH2hLPWInd4iMdeuKrSJBY92nFF6qHHfwATp2yE8csu8QJSeHpuunQ== X-Received: by 2002:a5d:4e82:: with SMTP id e2mr13891111wru.291.1542984379140; Fri, 23 Nov 2018 06:46:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:40 +0100 Message-Id: <20181123144558.5048-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 19/37] tcg/arm: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.inc.c | 314 ++++++++++++++++----------------------- 2 files changed, 125 insertions(+), 191 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94b3578c55..02981abdcc 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,7 +141,7 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 6b89ac7983..5a15f6a546 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1133,7 +1133,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGA= rg *args, } =20 #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1356,128 +1356,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, =20 return t2; } - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrl= o, - TCGReg addrhi, tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D raddr; - label->label_ptr[0] =3D label_ptr; -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - void *func; - - reloc_pc24(lb->label_ptr[0], s->code_ptr); - - argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* For armv6 we can use the canonical unsigned helpers and minimize - icache usage. For pre-armv6, use the signed helpers since we do - not have a single insn sign-extend. */ - if (use_armv6_instructions) { - func =3D qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]; - } else { - func =3D qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; - if (opc & MO_SIGN) { - opc =3D MO_UL; - } - } - tcg_out_call(s, func); - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_SW: - tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); - break; - default: - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_Q: - if (datalo !=3D TCG_REG_R1) { - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - } else if (datahi !=3D TCG_REG_R0) { - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - } else { - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); - } - break; - } - - tcg_out_goto(s, COND_AL, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - - reloc_pc24(lb->label_ptr[0], s->code_ptr); - - argreg =3D TCG_REG_R0; - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg =3D tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg =3D tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg =3D tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Tail-call to the helper, which will return to the fast path. */ - tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); -} #endif /* SOFTMMU */ =20 static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, @@ -1602,14 +1480,12 @@ static inline void tcg_out_qemu_ld_direct(TCGContex= t *s, TCGMemOp opc, =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index, avail; - TCGReg addend, t0, t1; - tcg_insn_unit *label_ptr; -#endif =20 datalo =3D *args++; datahi =3D (is64 ? *args++ : 0); @@ -1619,32 +1495,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - - avail =3D 0xf; - avail &=3D ~(1 << addrlo); - if (TARGET_LONG_BITS =3D=3D 64) { - avail &=3D ~(1 << addrhi); - } - tcg_debug_assert(avail & 1); - t0 =3D TCG_REG_R0; - avail &=3D ~1; - tcg_debug_assert(avail !=3D 0); - t1 =3D ctz32(avail); - - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - t0, t1, TCG_REG_TMP); - - /* This a conditional BL only to load a pointer within this opcode int= o LR - for the slow path. We will not be using the value for a tail call.= */ - label_ptr =3D s->code_ptr; - tcg_out_bl_noaddr(s, COND_NE); - - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); - - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ + add_ldst_ool_label(s, true, is64, oi, R_ARM_PC24, 0); + tcg_out_bl_noaddr(s, COND_AL); +#else if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); @@ -1746,14 +1599,12 @@ static inline void tcg_out_qemu_st_direct(TCGContex= t *s, TCGMemOp opc, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index, avail; - TCGReg addend, t0, t1; - tcg_insn_unit *label_ptr; -#endif =20 datalo =3D *args++; datahi =3D (is64 ? *args++ : 0); @@ -1763,35 +1614,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - - avail =3D 0xf; - avail &=3D ~(1 << addrlo); - avail &=3D ~(1 << datalo); - if (TARGET_LONG_BITS =3D=3D 64) { - avail &=3D ~(1 << addrhi); - } - if (is64) { - avail &=3D ~(1 << datahi); - } - tcg_debug_assert(avail & 1); - t0 =3D TCG_REG_R0; - avail &=3D ~1; - tcg_debug_assert(avail !=3D 0); - t1 =3D ctz32(avail); - - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - t0, t1, TCG_REG_TMP); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); - - /* The conditional call must come last, as we're going to return here.= */ - label_ptr =3D s->code_ptr; - tcg_out_bl_noaddr(s, COND_NE); - - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ + add_ldst_ool_label(s, false, is64, oi, R_ARM_PC24, 0); + tcg_out_bl_noaddr(s, COND_AL); +#else if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_st_index(s, COND_AL, opc, datalo, @@ -1802,6 +1627,115 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) #endif } =20 +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGReg addrlo, addrhi, datalo, datahi, addend, argreg, t0, t1; + TCGMemOp opc =3D get_memop(oi); + int mem_index =3D get_mmuidx(oi); + tcg_insn_unit *thunk =3D s->code_ptr; + tcg_insn_unit *label; + uintptr_t func; + int avail; + + /* Pick out where the arguments are located. A 64-bit address is + * aligned in the register pair R2:R3. Loads return into R0:R1. + * A 32-bit store with a 32-bit address has room at R2, but + * otherwise uses R4:R5. + */ + if (TARGET_LONG_BITS =3D=3D 64) { + addrlo =3D TCG_REG_R2, addrhi =3D TCG_REG_R3; + } else { + addrlo =3D TCG_REG_R1, addrhi =3D -1; + } + if (is_ld) { + datalo =3D TCG_REG_R0; + } else if (TARGET_LONG_BITS =3D=3D 64 || is_64) { + datalo =3D TCG_REG_R4; + } else { + datalo =3D TCG_REG_R2; + } + datahi =3D (is_64 ? datalo + 1 : -1); + + /* We need 3 call-clobbered temps. One of them is always R12, + * one of them is always R0. The third is somewhere in R[1-3]. + */ + avail =3D 0xf; + avail &=3D ~(1 << addrlo); + if (TARGET_LONG_BITS =3D=3D 64) { + avail &=3D ~(1 << addrhi); + } + if (!is_ld) { + avail &=3D ~(1 << datalo); + if (is_64) { + avail &=3D ~(1 << datahi); + } + } + tcg_debug_assert(avail & 1); + t0 =3D TCG_REG_R0; + avail &=3D ~1; + tcg_debug_assert(avail !=3D 0); + t1 =3D ctz32(avail); + + addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, is_ld, + t0, t1, TCG_REG_TMP); + + label =3D s->code_ptr; + tcg_out_b_noaddr(s, COND_NE); + + /* TCG Hit. */ + if (is_ld) { + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); + } else { + tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, addrlo, add= end); + } + tcg_out_bx(s, COND_AL, TCG_REG_R14); + + /* TLB Miss. */ + reloc_pc24(label, s->code_ptr); + + tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); + /* addrlo and addrhi are in place -- see above */ + argreg =3D addrlo + (TARGET_LONG_BITS / 32); + if (!is_ld) { + switch (opc & MO_SIZE) { + case MO_8: + argreg =3D tcg_out_arg_reg8(s, argreg, datalo); + break; + case MO_16: + argreg =3D tcg_out_arg_reg16(s, argreg, datalo); + break; + case MO_32: + argreg =3D tcg_out_arg_reg32(s, argreg, datalo); + break; + case MO_64: + argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); + break; + default: + g_assert_not_reached(); + } + } + argreg =3D tcg_out_arg_imm32(s, argreg, oi); + argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + + /* Tail call to the helper. */ + if (is_ld) { + func =3D (uintptr_t)qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; + } else { + func =3D (uintptr_t)qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]; + } + if (use_armv7_instructions) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, func); + tcg_out_bx(s, COND_AL, TCG_REG_TMP); + } else { + tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, func); + } + + return thunk; +} +#endif + static tcg_insn_unit *tb_ret_addr; =20 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 20/37] tcg/ppc: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.inc.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 656a9ff603..6e656cd41e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1516,12 +1516,14 @@ static void * const qemu_st_helpers[16] =3D { }; =20 /* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ + in CR7, loads the addend of the TLB, and returns the register containing + the guest address, places the addend into T0. + Clobbers t0, t1, TCG_REG_R0, TCG_REG_TMP1. */ =20 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) + int mem_index, bool is_read, + TCGReg t0, TCGReg t1) { int cmp_off =3D (is_read @@ -1536,10 +1538,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, if (TCG_TARGET_REG_BITS =3D=3D 64) { if (TARGET_LONG_BITS =3D=3D 32) { /* Zero-extend the address into a place helpful for further us= e. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; + tcg_out_ext32u(s, t1, addrlo); + addrlo =3D t1; } else { - tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo, + tcg_out_rld(s, RLDICL, t0, addrlo, 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS); } } @@ -1559,27 +1561,27 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =20 /* Extraction and shifting, part 2. */ if (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BITS =3D=3D 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo, + tcg_out_rlw(s, RLWINM, t0, addrlo, 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS), 31 - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS); + tcg_out_shli64(s, t0, t0, CPU_TLB_ENTRY_BITS); } =20 - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base)); + tcg_out32(s, ADD | TAB(t0, t0, base)); =20 /* Load the tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); + tcg_out_ld(s, TCG_TYPE_I32, t1, t0, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, t0, cmp_off + 4); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, t0, cmp_off); } =20 /* Load the TLB addend for use on the fast path. Do this asap to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, t0, t0, add_off); =20 /* Clear the non-page, non-alignment bits from the address */ if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -1624,7 +1626,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemO= p opc, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, t1, 0, 6, TCG_TYPE_I32); tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, @@ -1778,13 +1780,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + rbase =3D TCG_REG_R3; + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, + rbase, TCG_REG_R4); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); =20 - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { @@ -1853,13 +1856,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + rbase =3D TCG_REG_R3; + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, + rbase, TCG_REG_R4); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); =20 - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985798093839.1885001992446; Fri, 23 Nov 2018 07:09:58 -0800 (PST) Received: from localhost ([::1]:52884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD5b-0006N4-UL for importer@patchew.org; Fri, 23 Nov 2018 10:09:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EB-M9 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiw-0003Xg-5p for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46584) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiu-0003Rv-MR for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:25 -0500 Received: by mail-wr1-x443.google.com with SMTP id l9so12570617wrt.13 for ; Fri, 23 Nov 2018 06:46:22 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hZUCxApR4j0ObPvqrCHsopCtmT5xOXmakkLY1hrC/Hk=; b=jMvyyhaphe8ow49+KZIp3sK5IJCWA7NwPJeCGmw94pNxqomexsLUNXwVspLXqGGM9M /6flI1CK3//66zUG7y40aAM07gK2+9mn4OXroLCPDHJNVw6Uzr1HMrcNe4dHJ8A83RDh KfaKJu+Mb2ym8+Xc+e+4bSQbJXD3FlyIyCvQE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hZUCxApR4j0ObPvqrCHsopCtmT5xOXmakkLY1hrC/Hk=; b=Za25MyzFh2RUHO8tq39zDG6lXspgRznfiNdaxoRC+WmGDZiabVbpO76G3YmkDVef8/ uEwwKEvdaYZGgI9/vzhqwd3emQSjFyTPweAQdMkVtA4hj9AccbREaQV7MUdQdbPEVVpv 8btV425JzCJC9IopwEvOCkaVLm+z1BRaiCQCk+1wIb7BOFAkmo0btrkPhRDeYvA8w5lK ltSNYs8DWHgQEfMMC0cOin5xGRGMKugOnSwifvliYI+D2DGS2kBuHFU/TyhOVdPuknw2 /tuEjnnFnc38ch7/Evld9weLZyX4eGzM2bp7O2n6ISrGsM9YnItT6CfHPfFTKxLVvmF5 sFjA== X-Gm-Message-State: AA+aEWaP1/MArgswnrUnCE6DlVuZrrE9Z9NrOCfyV1/iwJxQnhVUZlar 5fGCOstMBfRvqloMMxlYsPrhgLW39pNQ2g== X-Google-Smtp-Source: AFSGD/UPhYW311dm3Vdtv+JEYjsJdJ6SFrt/X7BDLj8LR4pvPYtC81ggxGEN9TDnIsbCstj011h55g== X-Received: by 2002:adf:f984:: with SMTP id f4mr14472801wrr.234.1542984381291; Fri, 23 Nov 2018 06:46:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:42 +0100 Message-Id: <20181123144558.5048-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 21/37] tcg/ppc: Split out tcg_out_call_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pass in a LK parameter, allowing us to create tail calls. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.inc.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6e656cd41e..6377e3a829 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1408,7 +1408,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_addr, } } =20 -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *target, int lk) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1419,7 +1419,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *target) =20 if (in_range_b(diff) && toc =3D=3D (uint32_t)toc) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); + tcg_out_b(s, lk, tgt); } else { /* Fold the low bits of the constant into the addresses below. */ intptr_t arg =3D (intptr_t)target; @@ -1434,7 +1434,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *target) tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 intptr_t diff; @@ -1448,16 +1448,21 @@ static void tcg_out_call(TCGContext *s, tcg_insn_un= it *target) =20 diff =3D tcg_pcrel_diff(s, target); if (in_range_b(diff)) { - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); } else { tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #else - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); #endif } =20 +static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +{ + tcg_out_call_int(s, target, LK); +} + static const uint32_t qemu_ldx_opc[16] =3D { [MO_UB] =3D LBZX, [MO_UW] =3D LHZX, --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542984924751373.6803419419599; Fri, 23 Nov 2018 06:55:24 -0800 (PST) Received: from localhost ([::1]:52798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCrT-0000UN-VT for importer@patchew.org; Fri, 23 Nov 2018 09:55:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EA-LF for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiw-0003Xa-4u for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiu-0003T4-29 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:25 -0500 Received: by mail-wr1-x443.google.com with SMTP id x10so12591707wrs.8 for ; Fri, 23 Nov 2018 06:46:23 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2kjkOBwc36m3JzNrOy40V8NSFyoaC4yO+K9bCMPV9ck=; b=UX5DI7DshmBua7hZKefFU1DfJOwZYnhQAeuD8RwbqAVvRdPz1n1WaKYJqxb4UPpnrP UrzR2oWanT11/kCauIDhFP+VZX4/mCOLp5WfFmScNNOv+OWdgZDjPOoSYHv9jhCj/urQ 6BM3is+uy44U8rcG0F/kRj8ZdCkStENAvv4Cw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2kjkOBwc36m3JzNrOy40V8NSFyoaC4yO+K9bCMPV9ck=; b=FptfohtlXxvNbcuW++pQo5rq5qOO1Qa31CiPBHx2ZFAo+ovfWjKQWszFvgztSTryhR 28OZJJRHdZQS2i7cMfr+4yinrrsHntXd6WepV/H6eX069EF7Tbsnv5t/eMrQFgLoyCyb XNVk6HbasI5YsE+mm+GCuvZw7oj10Ko7UhmnoLwkTZC+yZbQno3HDbWFUIbZxUNAcpX4 Dw4gY/TjgCuQfmq8wUsO6WYC7ADha/wTo1wGEBb1SDS4rij4agn9VYa3qcQXdrNfPybT vumO1kdykO8yQsO7K+mSRy2M2mNbi26teIvEdH+TPfP4y4sqt7qAjFcDzgpGALu0yBnN 3BWQ== X-Gm-Message-State: AA+aEWZBlMU9puOw6wj8n2cqq94bzPiL5StP9qKCU5xHEm8MVtMI2/KQ WTETsG9mG733wVmYjxVQqoAR/G5U4ByIkg== X-Google-Smtp-Source: AFSGD/VYUUXHRiMI5e+u93x4k1ZtByhOTlWwkSe+fgUGIP4PABX9J37jMbqvs3bPE71+sPXxhdQ4Ng== X-Received: by 2002:adf:f903:: with SMTP id b3mr14726177wrr.82.1542984382198; Fri, 23 Nov 2018 06:46:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:43 +0100 Message-Id: <20181123144558.5048-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 22/37] tcg/ppc: Add constraints for R7-R8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.inc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6377e3a829..484d90ead2 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -236,10 +236,11 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, i= nt insn) static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e) { - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': + char c =3D *ct_str++; + switch (c) { + case 'A': case 'B': case 'C': case 'D': case 'E': case 'F': ct->ct |=3D TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); + tcg_regset_set_reg(ct->u.regs, 3 + c - 'A'); break; case 'r': ct->ct |=3D TCG_CT_REG; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985093559577.5634785785116; Fri, 23 Nov 2018 06:58:13 -0800 (PST) Received: from localhost ([::1]:52816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCuK-0002rW-3V for importer@patchew.org; Fri, 23 Nov 2018 09:58:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EF-MM for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCix-0003aN-U2 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiw-0003Ti-3g for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:27 -0500 Received: by mail-wm1-x343.google.com with SMTP id q26so12173210wmf.5 for ; Fri, 23 Nov 2018 06:46:24 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vcnioQXCG048QsIG8yjmBWpdApnTjYfBp7eDl5pVV3c=; b=BFdz5YCxofKL+qYW99/s86B/LDTWQen9/zxWFuknIjXrmFEuSYTHYg7SoQ2pUGxdck 91NxD973TLP8wwWCnr9m9WnD+FUrbRpkgZSR8eN9EpSUH/ZUAHLB29CrBAL7X6pwGTfy lh0hkVo5WsOeR/mU8RRl18U950wwKJspxqQh8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vcnioQXCG048QsIG8yjmBWpdApnTjYfBp7eDl5pVV3c=; b=RNvV+20FHhsFf5AK20OzvSxUXhI+d4sIPBKnWwbm0IZ0HE7S7MfPytdZyx7LIsLb0c TSSULOA/Eb3Zo8i6F6ptfuajml9TCTzge97XofsK2GYPOlDsjwP0Us082lyIWsCvidmI 2uFUztQi+2LBP1UMKD5zeSALwKdxBnYVZtSv2zoYrGIc6RrqM+QbjzIG/wFufe1VjsU2 ZU/KEyalDg1X9E5B+N0A7JY7rbpzFGulNTV9ZrGPGoOeICiWVrJiK6O4Fy6EuGWg9kKa jjQx07fawLfHM2ahWh3bI2w/pkJFaq3qogErYA9DN8fa6lPVUlZQm0vTNvC6zXOehsQV Suaw== X-Gm-Message-State: AGRZ1gLEJ17DYA59j9aCGfXnLYFWI545Yptc6sRWQUHH+lvd3Dxbyr89 iLIE4Gln0O18C0ivvzyoCKNKzcjqIlEFXQ== X-Google-Smtp-Source: AJdET5duMv0qzw5cBkpWppesrnc0jF+1HTK2mPeSpBrnkyA4ases06XyYFq3PihkQOurynBlf/5/Dg== X-Received: by 2002:a1c:c545:: with SMTP id v66mr13553690wmf.132.1542984383136; Fri, 23 Nov 2018 06:46:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:44 +0100 Message-Id: <20181123144558.5048-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 23/37] tcg/ppc: Change TCG_TARGET_CALL_ALIGN_ARGS to bool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleaner not to treat this as #ifdef. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.inc.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 484d90ead2..f7c33f3b7f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -30,6 +30,8 @@ #endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 +#else +# define TCG_TARGET_CALL_ALIGN_ARGS 0 #endif =20 /* For some memory operations, we need a scratch that isn't R0. For the A= IX @@ -1675,9 +1677,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) lo =3D lb->addrlo_reg; hi =3D lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |=3D 1; -#endif + arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -1720,9 +1720,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) lo =3D lb->addrlo_reg; hi =3D lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |=3D 1; -#endif + arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -1736,9 +1734,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) if (TCG_TARGET_REG_BITS =3D=3D 32) { switch (s_bits) { case MO_64: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |=3D 1; -#endif + arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); /* FALLTHRU */ case MO_32: --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985659222829.6735684799643; Fri, 23 Nov 2018 07:07:39 -0800 (PST) Received: from localhost ([::1]:52873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD3H-0002oQ-SY for importer@patchew.org; Fri, 23 Nov 2018 10:07:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000E9-LE for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiy-0003af-13 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54488) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCix-0003Un-Qx for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:27 -0500 Received: by mail-wm1-x343.google.com with SMTP id r63-v6so12199042wma.4 for ; Fri, 23 Nov 2018 06:46:25 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vw53NxlkIM0aRxCvl+l6ZZoxsk+nWK7e+ZpN0X1cy0Y=; b=Sp4SHAVvrfU2Ij5VTVCiXr88npowWS1Pr+S7nqPmO1Dgo1W08u3AWUpCBENnsiwxOo p/CgkKE82rxodZQMlp9LRvjxjtAQT3Us0zinseuyMVGyt/BUCcH5KLFL/YwDEy75B8yz ktCpghaHg5mZdpXcIecMTdk3rbLGRY+bUd6wk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vw53NxlkIM0aRxCvl+l6ZZoxsk+nWK7e+ZpN0X1cy0Y=; b=CXSdVgl9P1vwmo3F6f+XznVYUDQKsr5bmqN3Tw4GqYIRYrumTViDtMuNAxJzqPBfn5 IlUHbEjkPT9GX6GoczeuAWJHvRWpkHKtDUMeobJgMWckbJBcs761VNof57CSMtlDj00V nHK60HopU4suRnQJqvn1qFrfprah3CaQj1y6GUBk9nGbiq2xwXxRoareAdJfcS70MaVN OsRfrlhm63R9Jw75o+g/+IkIRfX28brFlFvV2L9xulv55S7MlfyFhUYjqcSDC4HC2j2z K1OCdaBKCUR+msxlOmBlpkljqcOi03SaO9jJnHBhPaJtWOxjzhF+FNb2T5WBSZU2m+FE h+Ow== X-Gm-Message-State: AA+aEWbezSe0FNGGdsQ9uroDZt8KFgWFQBB2qnhwtJC5PIZNBBFdz3iZ O+Xv9CQ1iK4EU1Ik5H1cYhhSdDjBSG/UQg== X-Google-Smtp-Source: AFSGD/XinSQouxGZIyBVxtm2OvGADiSj2KVjPRVsn/aIrR+V2MJEcdw14UbKT12iIHsH/hoxFWj3ig== X-Received: by 2002:a1c:cf0d:: with SMTP id f13mr3506527wmg.70.1542984384176; Fri, 23 Nov 2018 06:46:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:45 +0100 Message-Id: <20181123144558.5048-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 24/37] tcg/ppc: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.inc.c | 151 ++++++++++++++++++++++++++++----------- 1 file changed, 111 insertions(+), 40 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index f7c33f3b7f..c706b2cf53 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -248,25 +248,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffff; break; - case 'L': /* qemu_ld constraint */ - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); -#endif - break; case 'I': ct->ct |=3D TCG_CT_CONST_S16; break; @@ -1759,6 +1740,21 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) =20 tcg_out_b(s, 0, lb->raddr); } + +static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo, TCGReg *hi) +{ +#ifdef HOST_WORDS_BIGENDIAN + static bool is_be =3D true; +#else + static bool is_be =3D false; +#endif + + assert(TCG_TARGET_REG_BITS =3D=3D 32); + reg |=3D TCG_TARGET_CALL_ALIGN_ARGS; + *(is_be ? hi : lo) =3D reg; + *(is_be ? lo : hi) =3D reg + 1; + return reg + 2; +} #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) @@ -1782,9 +1778,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - rbase =3D TCG_REG_R3; + rbase =3D TCG_REG_R9; addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, - rbase, TCG_REG_R4); + rbase, TCG_REG_R10); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -1858,9 +1854,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); - rbase =3D TCG_REG_R3; + rbase =3D TCG_REG_R9; addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, - rbase, TCG_REG_R4); + rbase, TCG_REG_R10); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2627,13 +2623,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) { static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef S_S =3D { .args_ct_str =3D { "S", "S" } }; static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef S_S_S =3D { .args_ct_str =3D { "S", "S", "= S" } }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; static const TCGTargetOpDef r_r_rT =3D { .args_ct_str =3D { "r", "r", = "rT" } }; @@ -2644,10 +2635,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) =3D { .args_ct_str =3D { "r", "rI", "rT" } }; static const TCGTargetOpDef r_r_rZW =3D { .args_ct_str =3D { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - =3D { .args_ct_str =3D { "S", "S", "S", "S" } }; static const TCGTargetOpDef movc =3D { .args_ct_str =3D { "r", "r", "ri", "rZ", "rZ" } }; static const TCGTargetOpDef dep @@ -2660,6 +2647,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; +#ifdef CONFIG_SOFTMMU + static const char * const arg_letter[] =3D { + NULL, NULL, NULL, "A", "B", "C", "D", "E", "F", NULL, NULL + }; + TCGReg hi, lo, arg; +#else + static const TCGTargetOpDef r_r_r_r + =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; +#endif =20 switch (op) { case INDEX_op_goto_ptr: @@ -2782,18 +2778,93 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_sub2_i32: return &sub2; =20 +#ifdef CONFIG_SOFTMMU case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &r_L : &r_L_L); + { + static TCGTargetOpDef ld32; + ld32.args_ct_str[0] =3D arg_letter[tcg_target_call_oarg_regs[0= ]]; + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + ld32.args_ct_str[1] =3D arg_letter[tcg_target_call_iarg_re= gs[1]]; + } else { + arg =3D tcg_target_call_iarg_regs[1]; + arg =3D softmmu_args_2(arg, &lo, &hi); + ld32.args_ct_str[1] =3D arg_letter[lo]; + ld32.args_ct_str[2] =3D arg_letter[hi]; + } + return &ld32; + } case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? &S_S : &S_S_S); + { + static TCGTargetOpDef st32; + arg =3D tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + st32.args_ct_str[0] =3D arg_letter[arg + 1]; + st32.args_ct_str[1] =3D arg_letter[arg]; + } else { + arg =3D softmmu_args_2(arg, &lo, &hi); + st32.args_ct_str[0] =3D arg_letter[arg]; + st32.args_ct_str[1] =3D arg_letter[lo]; + st32.args_ct_str[2] =3D arg_letter[hi]; + } + return &st32; + } case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS =3D=3D 32 ? &L_L_L : &L_L_L_L); + { + static TCGTargetOpDef ld64; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + ld64.args_ct_str[0] =3D arg_letter[tcg_target_call_oarg_re= gs[0]]; + ld64.args_ct_str[1] =3D arg_letter[tcg_target_call_iarg_re= gs[1]]; + } else { + arg =3D tcg_target_call_oarg_regs[1]; + arg =3D softmmu_args_2(arg, &lo, &hi); + ld64.args_ct_str[0] =3D arg_letter[lo]; + ld64.args_ct_str[1] =3D arg_letter[hi]; + arg =3D tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS =3D=3D 32) { + ld64.args_ct_str[2] =3D arg_letter[arg]; + } else { + arg =3D softmmu_args_2(arg, &lo, &hi); + ld64.args_ct_str[2] =3D arg_letter[lo]; + ld64.args_ct_str[3] =3D arg_letter[hi]; + } + } + return &ld64; + } case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S - : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); + { + static TCGTargetOpDef st64; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + st64.args_ct_str[1] =3D arg_letter[tcg_target_call_iarg_re= gs[1]]; + st64.args_ct_str[0] =3D arg_letter[tcg_target_call_iarg_re= gs[2]]; + } else { + arg =3D tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS =3D=3D 32) { + st64.args_ct_str[2] =3D arg_letter[arg++]; + } else { + arg =3D softmmu_args_2(arg, &lo, &hi); + st64.args_ct_str[2] =3D arg_letter[lo]; + st64.args_ct_str[3] =3D arg_letter[hi]; + } + arg =3D softmmu_args_2(arg, &lo, &hi); + st64.args_ct_str[0] =3D arg_letter[lo]; + st64.args_ct_str[1] =3D arg_letter[hi]; + } + return &st64; + } +#else + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r : &r_r_r; + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + return &r_r; + } else if (TARGET_LONG_BITS =3D=3D 32) { + return &r_r_r; + } else { + return &r_r_r_r; + } +#endif =20 default: return NULL; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985321636991.2651734553239; Fri, 23 Nov 2018 07:02:01 -0800 (PST) Received: from localhost ([::1]:52841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCy0-0006qU-4V for importer@patchew.org; Fri, 23 Nov 2018 10:02:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj3-0000Ha-Ak for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiz-0003dg-OM for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:34360) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiy-0003Wb-1E for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:29 -0500 Received: by mail-wm1-x342.google.com with SMTP id y185so7738001wmd.1 for ; Fri, 23 Nov 2018 06:46:26 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4SK9gU8naH9sM9NW9c9OPn3r+aLaMwI873v6N6J6XYs=; b=bXr8TcCxBNiwl89uiwDB17DpWVPGxfkg7I+44n99nwd3NCngvQ+NOrQKnf9jOXDXPA S1drTzZpmG3Pq5Uka0++8ONy6vx/NWVck6Gu2LxGmUXVIzZ1R2WgFSuFBOLkElCYZorz LGAkjZquiHOz/Od1zhu57Ys3Yts6gEFZpW0sY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4SK9gU8naH9sM9NW9c9OPn3r+aLaMwI873v6N6J6XYs=; b=OvE0+8Ct1aYe+HPux03JlY5OxCvKMFCTW2SsKCD42T1HvM0500YfYpcdgoV8YtdzuP bMzBuOJ/4+1EeC1A7wjrX8L0mv2tV10DU+oo6c1g3cpDZ870jqx1GPkN+nkzxscvRZJS 3HA/QHAIJWBq/GCh+z2hOJBjPf7QLkqkXlZow4w4gqPg0hthS8a1pQl8FV2Bis664t6h VPXCqLfa+b71Y9f/3uCLcr2RFEMkpRPc9GUW9SQPpsuDmLySnd3uTnUk8vjVBNYr4cSl zuubCHrFcn4Re0J4EXb4H3vLhGrhjFoWhYA6M3e3NSr/nvzvL7PKCjavsBz0kqoQEzek Zrjw== X-Gm-Message-State: AA+aEWb6u7suxAaKwd+yGZMQ1zxdsx1RiJOdWdrcl7DKb9Okp8bLSwOU Dpabg0XgyCAMc0Ieaqq6sXretfjI7eOfmA== X-Google-Smtp-Source: AJdET5clkHzF/cepUmaCJd9ujCoEZQ7wzT46FUNWv1SirFUcd2KNzDYj/Y1Qdk4uNuINKBIkAQVqiw== X-Received: by 2002:a1c:cb4c:: with SMTP id b73mr15074247wmg.69.1542984384861; Fri, 23 Nov 2018 06:46:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:46 +0100 Message-Id: <20181123144558.5048-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 25/37] tcg/ppc: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 326 +++++++++++++++++---------------------- 2 files changed, 141 insertions(+), 187 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be52ad1d2e..bbc49bb1be 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -130,7 +130,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #define TCG_TARGET_DEFAULT_MO (0) =20 #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c706b2cf53..fed7f5fe6e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1476,7 +1476,7 @@ static const uint32_t qemu_exts_opc[4] =3D { }; =20 #if defined (CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" =20 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1489,6 +1489,14 @@ static void * const qemu_ld_helpers[16] =3D { [MO_BEUW] =3D helper_be_lduw_mmu, [MO_BEUL] =3D helper_be_ldul_mmu, [MO_BEQ] =3D helper_be_ldq_mmu, + + [MO_SB] =3D helper_ret_ldsb_mmu, + [MO_LESW] =3D helper_le_ldsw_mmu, + [MO_BESW] =3D helper_be_ldsw_mmu, +#if TCG_TARGET_REG_BITS =3D=3D 64 + [MO_LESL] =3D helper_le_ldsl_mmu, + [MO_BESL] =3D helper_be_ldsl_mmu, +#endif }; =20 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, @@ -1526,9 +1534,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemO= p opc, /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { if (TARGET_LONG_BITS =3D=3D 32) { - /* Zero-extend the address into a place helpful for further us= e. */ - tcg_out_ext32u(s, t1, addrlo); - addrlo =3D t1; + /* Zero-extend the address now. */ + tcg_out_ext32u(s, addrlo, addrlo); } else { tcg_out_rld(s, RLDICL, t0, addrlo, 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS); @@ -1625,122 +1632,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, return addrlo; } =20 -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->datalo_reg =3D datalo_reg; - label->datahi_reg =3D datahi_reg; - label->addrlo_reg =3D addrlo_reg; - label->addrhi_reg =3D addrhi_reg; - label->raddr =3D raddr; - label->label_ptr[0] =3D lptr; -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGReg hi, lo, arg =3D TCG_REG_R3; - - reloc_pc14(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else if (opc & MO_SIGN) { - uint32_t insn =3D qemu_exts_opc[opc & MO_SIZE]; - tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); - } else { - tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); - } - - tcg_out_b(s, 0, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; - TCGReg hi, lo, arg =3D TCG_REG_R3; - - reloc_pc14(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - switch (s_bits) { - case MO_64: - arg |=3D TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - /* FALLTHRU */ - case MO_32: - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - break; - default: - tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); - break; - } - } else { - if (s_bits =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); - } else { - tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); - } - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - tcg_out_b(s, 0, lb->raddr); -} - static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo, TCGReg *hi) { #ifdef HOST_WORDS_BIGENDIAN @@ -1757,44 +1648,10 @@ static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo= , TCGReg *hi) } #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, + TCGReg addrlo, TCGReg rbase, TCGMemOp o= pc) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - TCGMemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif - - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - rbase =3D TCG_REG_R9; - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, - rbase, TCG_REG_R10); - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - -#else /* !CONFIG_SOFTMMU */ - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); @@ -1811,7 +1668,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); } } else { - uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; + uint32_t insn =3D qemu_ldx_opc[opc & (MO_SSIZE | MO_BSWAP)]; if (!HAVE_ISA_2_06 && insn =3D=3D LDBRX) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); @@ -1822,55 +1679,45 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) } else { insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); - insn =3D qemu_exts_opc[s_bits]; + insn =3D qemu_exts_opc[opc & MO_SIZE]; tcg_out32(s, insn | RA(datalo) | RS(datalo)); } } - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg datalo, datahi, addrlo, rbase; + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif =20 datalo =3D *args++; datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); addrlo =3D *args++; addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - rbase =3D TCG_REG_R9; - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, - rbase, TCG_REG_R10); + add_ldst_ool_label(s, true, is_64, oi, R_PPC_REL24, 0); + tcg_out_b_noaddr(s, B | LK); +#else + TCGMemOp opc =3D get_memop(oi); + TCGReg rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; =20 - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - -#else /* !CONFIG_SOFTMMU */ - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); addrlo =3D TCG_REG_TMP1; } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, rbase, opc); #endif +} =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, + TCGReg addrlo, TCGReg rbase, TCGMemOp o= pc) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); @@ -1894,10 +1741,34 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); } } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + + datalo =3D *args++; + datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); + addrlo =3D *args++; + addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi =3D *args++; =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_ldst_ool_label(s, false, is_64, oi, R_PPC_REL24, 0); + tcg_out_b_noaddr(s, B | LK); +#else + TCGMemOp opc =3D get_memop(oi); + TCGReg rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; + + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + addrlo =3D TCG_REG_TMP1; + } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, rbase, opc); #endif } =20 @@ -1909,6 +1780,89 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) } } =20 +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGMemOp opc =3D get_memop(oi); + int mem_index =3D get_mmuidx(oi); + TCGReg addrlo, addrhi, datalo, datahi, rbase, nextarg; + tcg_insn_unit *thunk, *label; + + /* Since we're amortizing the cost, align the thunk. */ + thunk =3D QEMU_ALIGN_PTR_UP(s->code_ptr, 16); + if (thunk !=3D s->code_ptr) { + tcg_out_nop_fill(s->code_ptr, thunk - s->code_ptr); + s->code_ptr =3D thunk; + } + + /* Discover where the inputs are held. */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + addrhi =3D addrlo =3D tcg_target_call_iarg_regs[1]; + if (is_ld) { + datahi =3D datalo =3D tcg_target_call_oarg_regs[0]; + nextarg =3D addrlo + 1; + } else { + datahi =3D datalo =3D addrlo + 1; + nextarg =3D addrlo + 2; + } + } else { + nextarg =3D tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS =3D=3D 64) { + nextarg =3D softmmu_args_2(nextarg, &addrlo, &addrhi); + } else { + addrhi =3D addrlo =3D nextarg++; + } + if (is_ld) { + TCGReg arg =3D tcg_target_call_oarg_regs[0]; + if (is_64) { + softmmu_args_2(arg, &datalo, &datahi); + } else { + addrhi =3D addrlo =3D arg; + } + } else { + if (is_64) { + nextarg =3D softmmu_args_2(nextarg, &datalo, &datahi); + } else { + addrhi =3D addrlo =3D nextarg++; + } + } + } + + rbase =3D TCG_REG_R9; + tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, + is_ld, rbase, TCG_REG_R10); + + label =3D s->code_ptr; + tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE); + + /* TLB Hit */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, rbase, opc); + } else { + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, rbase, opc); + } + tcg_out32(s, BCLR | BO_ALWAYS); + + /* TLB Miss */ + reloc_pc14(label, s->code_ptr); + + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The addrhi, addrlo, datahi, datalo registers are already in place. = */ + tcg_out_movi(s, TCG_TYPE_I32, nextarg++, oi); + tcg_out32(s, MFSPR | RT(nextarg) | LR); + + /* Tail call to the helper. */ + if (is_ld) { + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], = 0); + } else { + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], 0= ); + } + + return thunk; +} +#endif + /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_EXTEND_ARGS 1 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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Fri, 23 Nov 2018 06:46:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:47 +0100 Message-Id: <20181123144558.5048-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 26/37] tcg: Clean up generic bswap32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Based on the only current user, Sparc: New code uses 1 constant that takes 2 insns to create, plus 8. Old code used 2 constants that took 2 insns to create, plus 9. The result is a new total of 10 vs an old total of 13. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg-op.c | 54 ++++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7a8015c5a9..a956499e46 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1012,22 +1012,22 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) if (TCG_TARGET_HAS_bswap32_i32) { tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); } else { - TCGv_i32 t0, t1; - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_const_i32(0x00ff00ff); =20 - tcg_gen_shli_i32(t0, arg, 24); + /* arg =3D abcd */ + tcg_gen_shri_i32(t0, arg, 8); /* t0 =3D .abc */ + tcg_gen_and_i32(t1, arg, t2); /* t1 =3D .b.d */ + tcg_gen_and_i32(t0, t0, t2); /* t0 =3D .a.c */ + tcg_temp_free_i32(t2); + tcg_gen_shli_i32(t1, t1, 8); /* t1 =3D b.d. */ + tcg_gen_or_i32(ret, t0, t1); /* ret =3D badc */ =20 - tcg_gen_andi_i32(t1, arg, 0x0000ff00); - tcg_gen_shli_i32(t1, t1, 8); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t0, ret, 16); /* t0 =3D ..ba */ + tcg_gen_shli_i32(t1, ret, 16); /* t1 =3D dc.. */ + tcg_gen_or_i32(ret, t0, t1); /* ret =3D dcba */ =20 - tcg_gen_shri_i32(t1, arg, 8); - tcg_gen_andi_i32(t1, t1, 0x0000ff00); - tcg_gen_or_i32(t0, t0, t1); - - tcg_gen_shri_i32(t1, arg, 24); - tcg_gen_or_i32(ret, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); } @@ -1638,23 +1638,23 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) } else if (TCG_TARGET_HAS_bswap32_i64) { tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); } else { - TCGv_i64 t0, t1; - t0 =3D tcg_temp_new_i64(); - t1 =3D tcg_temp_new_i64(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_const_i64(0x00ff00ff); =20 - tcg_gen_shli_i64(t0, arg, 24); - tcg_gen_ext32u_i64(t0, t0); + /* arg =3D ....abcd */ + tcg_gen_shri_i64(t0, arg, 8); /* t0 =3D .....abc */ + tcg_gen_and_i64(t1, arg, t2); /* t1 =3D .....b.d */ + tcg_gen_and_i64(t0, t0, t2); /* t0 =3D .....a.c */ + tcg_temp_free_i64(t2); + tcg_gen_shli_i64(t1, t1, 8); /* t1 =3D ....b.d. */ + tcg_gen_or_i64(ret, t0, t1); /* ret =3D ....badc */ =20 - tcg_gen_andi_i64(t1, arg, 0x0000ff00); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_shli_i64(t1, ret, 48); /* t1 =3D dc...... */ + tcg_gen_shri_i64(t0, ret, 16); /* t0 =3D ......ba */ + tcg_gen_shri_i64(t1, ret, 32); /* t1 =3D ....dc.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret =3D ....dcba */ =20 - tcg_gen_shri_i64(t1, arg, 8); - tcg_gen_andi_i64(t1, t1, 0x0000ff00); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 24); - tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); } --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Fri, 23 Nov 2018 06:46:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:48 +0100 Message-Id: <20181123144558.5048-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 27/37] tcg: Clean up generic bswap64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Based on the only current user, Sparc: New code uses 2 constants that take 2 insns to load from constant pool, plus 13. Old code used 6 constants that took 1 or 2 insns to create, plus 21. The result is a new total of 17 vs an old total of 29. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg-op.c | 43 ++++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a956499e46..887b371a81 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1678,37 +1678,30 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) } else { TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_shli_i64(t0, arg, 56); + /* arg =3D abcdefgh */ + tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull); + tcg_gen_shri_i64(t0, arg, 8); /* t0 =3D .abcdefg */ + tcg_gen_and_i64(t1, arg, t2); /* t1 =3D .b.d.f.h */ + tcg_gen_and_i64(t0, t0, t2); /* t0 =3D .a.c.e.g */ + tcg_gen_shli_i64(t1, t1, 8); /* t1 =3D b.d.f.h. */ + tcg_gen_or_i64(ret, t0, t1); /* ret =3D badcfehg */ =20 - tcg_gen_andi_i64(t1, arg, 0x0000ff00); - tcg_gen_shli_i64(t1, t1, 40); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull); + tcg_gen_shri_i64(t0, ret, 16); /* t0 =3D ..badcfe */ + tcg_gen_and_i64(t1, ret, t2); /* t1 =3D ..dc..hg */ + tcg_gen_and_i64(t0, t0, t2); /* t0 =3D ..ba..fe */ + tcg_gen_shli_i64(t1, t1, 16); /* t1 =3D dc..hg.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret =3D dcbahgfe */ =20 - tcg_gen_andi_i64(t1, arg, 0x00ff0000); - tcg_gen_shli_i64(t1, t1, 24); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_shri_i64(t0, ret, 32); /* t0 =3D ....dcba */ + tcg_gen_shli_i64(t1, ret, 32); /* t1 =3D hgfe.... */ + tcg_gen_or_i64(ret, t0, t1); /* ret =3D hgfedcba */ =20 - tcg_gen_andi_i64(t1, arg, 0xff000000); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 8); - tcg_gen_andi_i64(t1, t1, 0xff000000); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 24); - tcg_gen_andi_i64(t1, t1, 0x00ff0000); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 40); - tcg_gen_andi_i64(t1, t1, 0x0000ff00); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 56); - tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } } =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985527156158.59677702967133; Fri, 23 Nov 2018 07:05:27 -0800 (PST) Received: from localhost ([::1]:52852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD1D-0000lf-17 for importer@patchew.org; Fri, 23 Nov 2018 10:05:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj2-0000H3-KE for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PATCH for-4.0 v2 28/37] tcg/optimize: Optimize bswap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Somehow we forgot these operations, once upon a time. This will allow immediate stores to have their bswap optimized away. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/optimize.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5dbe11c3c8..6b98ec13e6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -353,6 +353,15 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGA= rg x, TCGArg y) CASE_OP_32_64(ext16u): return (uint16_t)x; =20 + CASE_OP_32_64(bswap16): + return bswap16(x); + + CASE_OP_32_64(bswap32): + return bswap32(x); + + case INDEX_op_bswap64_i64: + return bswap64(x); + case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: return (int32_t)x; @@ -1105,6 +1114,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(ext16s): CASE_OP_32_64(ext16u): CASE_OP_32_64(ctpop): + CASE_OP_32_64(bswap16): + CASE_OP_32_64(bswap32): + case INDEX_op_bswap64_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985421774414.8324590614749; Fri, 23 Nov 2018 07:03:41 -0800 (PST) Received: from localhost ([::1]:52845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCzc-0007zB-Al for importer@patchew.org; Fri, 23 Nov 2018 10:03:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj4-0000He-S3 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj3-0003ji-FJ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj2-0003dG-LD for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:33 -0500 Received: by mail-wm1-x343.google.com with SMTP id k198so12262516wmd.3 for ; Fri, 23 Nov 2018 06:46:30 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iWb2bt6sblF41jXuHpGYj8BfGGXw2Ubf5D8PGYLewXs=; b=a8sTexFtSq0vS5HD/6YKoW8iwnDPqy7lqMiQn2QATxs7ABGIsKQnsVjrM1q5cebAc1 BVlADQMTTOwEI5zH7K1Jad1TuB3J5mtRE0EeaoE2TzOKQjpHk/mCnCEjkA2o2po10g3o /1bjNbPs29ElXV4onRvoj9u+Ljqnip4XCuifE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iWb2bt6sblF41jXuHpGYj8BfGGXw2Ubf5D8PGYLewXs=; b=uezoqNzNytYJZNg2AOUnBMur9jNrFxdt+AQ381jbtqcO7RLOG/SF2hhACONhZ8LnD1 ZSLxDbjQcgV2nfdhV02EYAAqo1QDemJvOoADSIfiNLfjkotR/x0aZMtmuav+xSc77s/G v+edKqMGKfZjDn6LD2Qm7PN5YdTCGC/hGHkr+fQQQomcgBvbZtSK600iMqYd00BKHJv9 o0KdoqoRfh0xLZJ68RitKj85C/U8TnMBgeww/NsQqf6/nbXbuB9lZgZWN2LraQbBxlgk 7PBIa0BKXvNVW5xMp6LBV50brrwHl9xbp9kuFtux/xKBbKe4NqIcQh9tOqxET2jacIoX 6Gkw== X-Gm-Message-State: AGRZ1gIv4MiLaeHcgdnwzURtKfnnm/+mP2ljmeZ6MYoxndK71aoy73ZE +F/V3eZ+ZT3R7KBvm1LM+GZTxxcGQEcodQ== X-Google-Smtp-Source: AJdET5dRUqyj+aEykkXqbJhbQkiVXC0KOEnUjwC+K05kHHiIhj5qLoAlp2dJf9odajfavFvn60b3EA== X-Received: by 2002:a1c:4406:: with SMTP id r6mr14245953wma.151.1542984388703; Fri, 23 Nov 2018 06:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:50 +0100 Message-Id: <20181123144558.5048-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 29/37] tcg: Add TCG_TARGET_HAS_MEMORY_BSWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For now, defined universally as true, since we previously required backends to implement swapped memory operations. Future patches may now remove that support where it is onerous. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 2 + tcg/tcg-op.c | 118 ++++++++++++++++++++++++++++++++++++++- 9 files changed, 126 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d1bd77c41d..0788f2eecb 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,6 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 02981abdcc..7a4c55d66d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,6 +131,7 @@ enum { }; =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 1b2d4e1b0d..212ba554e9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -219,6 +219,8 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index a8222476f0..5cb8672470 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -203,6 +203,7 @@ extern bool use_mips32r2_instructions; #endif =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index bbc49bb1be..6f587010fb 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -128,6 +128,7 @@ void flush_icache_range(uintptr_t start, uintptr_t stop= ); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 6f2b06a7d1..853ed6e7aa 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -135,6 +135,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_CALL_STACK_OFFSET 160 =20 #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8339bf010..a0ed2a3342 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -164,6 +164,7 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 26140d78cb..086f34e69a 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,6 +198,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) We prefer consistency across hosts on this. */ #define TCG_TARGET_DEFAULT_MO (0) =20 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t = addr) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 887b371a81..1ad095cc35 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2694,25 +2694,78 @@ static void tcg_gen_req_mo(TCGBar type) =20 void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + TCGMemOp orig_memop; + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop =3D memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SSIZE) =3D=3D MO_SW) { + memop &=3D ~MO_SIGN; + } + } + gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i32(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i32(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i32(val, val); + break; + default: + g_assert_not_reached(); + } + } } =20 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + TCGv_i32 swap =3D NULL; + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap =3D tcg_temp_new_i32(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i32(swap, val); + tcg_gen_bswap16_i32(swap, swap); + break; + case MO_32: + tcg_gen_bswap32_i32(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i32(swap); + } } =20 void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + TCGMemOp orig_memop; + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2723,24 +2776,85 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, T= CGArg idx, TCGMemOp memop) return; } =20 + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop =3D memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { + memop &=3D ~MO_SIGN; + } + } + gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i64(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext32s_i64(val, val); + } + break; + case MO_64: + tcg_gen_bswap64_i64(val, val); + break; + default: + g_assert_not_reached(); + } + } } =20 void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + TCGv_i64 swap =3D NULL; + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; } =20 + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap =3D tcg_temp_new_i64(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i64(swap, val); + tcg_gen_bswap16_i64(swap, swap); + break; + case MO_32: + tcg_gen_ext32u_i64(swap, val); + tcg_gen_bswap32_i64(swap, swap); + break; + case MO_64: + tcg_gen_bswap64_i64(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i64(swap); + } } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Fri, 23 Nov 2018 06:46:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:51 +0100 Message-Id: <20181123144558.5048-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.0 v2 30/37] tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always true for softmmu and when movbe is available. In the softmmu case we always have call-clobbered scratch registers available, and having the bswap in the softmmu thunk maximizes code sharing. For user-only and without movbe, leave this to generic code. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.h | 5 ++ tcg/i386/tcg-target.inc.c | 122 ++++++++++++++++++++++++-------------- 2 files changed, 82 insertions(+), 45 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 212ba554e9..2d7cbb5dd6 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -101,6 +101,7 @@ extern bool have_bmi1; extern bool have_popcnt; extern bool have_avx1; extern bool have_avx2; +extern bool have_movbe; =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -219,7 +220,11 @@ static inline void tb_target_set_jmp_target(uintptr_t = tc_ptr, =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 +#ifdef CONFIG_SOFTMMU #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#else +#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe +#endif =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5c68cbd43d..76235e90c9 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -158,13 +158,12 @@ bool have_bmi1; bool have_popcnt; bool have_avx1; bool have_avx2; +bool have_movbe; =20 #ifdef CONFIG_CPUID_H -static bool have_movbe; static bool have_bmi2; static bool have_lzcnt; #else -# define have_movbe 0 # define have_bmi2 0 # define have_lzcnt 0 #endif @@ -1818,13 +1817,24 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, TCGMemOp memop) { - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + bool use_bswap =3D memop & MO_BSWAP; + bool use_movbe =3D false; int movop =3D OPC_MOVL_GvEv; =20 - if (have_movbe && real_bswap) { - bswap =3D 0; - movop =3D OPC_MOVBE_GyMy; + /* + * Do big-endian loads with movbe or softmmu. + * User-only without movbe will have its swapping done generically. + */ + if (use_bswap) { + if (have_movbe) { + use_bswap =3D false; + use_movbe =3D true; + movop =3D OPC_MOVBE_GyMy; + } else { +#ifndef CONFIG_SOFTMMU + g_assert_not_reached(); +#endif + } } =20 switch (memop & MO_SSIZE) { @@ -1837,40 +1847,52 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); - } - break; - case MO_SW: - if (real_bswap) { - if (have_movbe) { + if (use_movbe) { + /* There is no extending movbe; only low 16-bits are modified.= */ + if (datalo !=3D base && datalo !=3D index) { + /* XOR breaks zeros while breaking dependency chains. */ + tgen_arithr(s, ARITH_XOR, datalo, datalo); tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, datalo, base, index, 0, ofs); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, + datalo, base, index, 0, ofs); + tcg_out_ext16u(s, datalo, datalo); + } + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + base, index, 0, ofs); + if (use_bswap) { tcg_out_rolw_8(s, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo); + } + break; + case MO_SW: + if (use_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16s(s, datalo, datalo, P_REXW); } else { tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, datalo, base, index, 0, ofs); + if (use_bswap) { + tcg_out_rolw_8(s, datalo); + tcg_out_ext16s(s, datalo, datalo, P_REXW); + } } break; case MO_UL: tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); } break; #if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: - if (real_bswap) { + if (use_bswap || use_movbe) { tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); } tcg_out_ext32s(s, datalo, datalo); @@ -1884,12 +1906,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); - if (bswap) { + if (use_bswap) { tcg_out_bswap64(s, datalo); } } else { - if (real_bswap) { - int t =3D datalo; + if (use_bswap || use_movbe) { + TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } @@ -1904,14 +1926,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); } - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); tcg_out_bswap32(s, datahi); } } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1991,24 +2013,34 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, TCGReg base, intptr_t ofs, int seg, TCGMemOp memop) { - /* ??? Ideally we wouldn't need a scratch register. For user-only, - we could perform the bswap twice to restore the original value - instead of moving to the scratch. But as it is, the L constraint - means that TCG_REG_L0 is definitely free here. */ const TCGReg scratch =3D TCG_REG_L0; - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + bool use_bswap =3D memop & MO_BSWAP; + bool use_movbe =3D false; int movop =3D OPC_MOVL_EvGv; =20 - if (have_movbe && real_bswap) { - bswap =3D 0; - movop =3D OPC_MOVBE_MyGy; + /* + * Do big-endian stores with movbe or softmmu. + * User-only without movbe will have its swapping done generically. + */ + if (use_bswap) { + if (have_movbe) { + use_bswap =3D false; + use_movbe =3D true; + movop =3D OPC_MOVBE_MyGy; + } else { +#ifndef CONFIG_SOFTMMU + g_assert_not_reached(); +#endif + } } =20 switch (memop & MO_SIZE) { case MO_8: - /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. - Use the scratch register if necessary. */ + /* + * In 32-bit mode, 8-bit stores can only happen from [abcd]x. + * ??? Adjust constraints such that this is is forced, then + * we won't need a scratch at all for user-only. + */ if (TCG_TARGET_REG_BITS =3D=3D 32 && datalo >=3D 4) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo =3D scratch; @@ -2017,7 +2049,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, datalo, base, ofs); break; case MO_16: - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_rolw_8(s, scratch); datalo =3D scratch; @@ -2025,7 +2057,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); break; case MO_32: - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_bswap32(s, scratch); datalo =3D scratch; @@ -2034,13 +2066,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); tcg_out_bswap64(s, scratch); datalo =3D scratch; } tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, of= s); - } else if (bswap) { + } else if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); tcg_out_bswap32(s, scratch); tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s); @@ -2048,8 +2080,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_out_bswap32(s, scratch); tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s+4); } else { - if (real_bswap) { - int t =3D datalo; + if (use_movbe) { + TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } @@ -2058,7 +2090,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 31/37] tcg/aarch64: Set TCG_TARGET_HAS_MEMORY_BSWAP to false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to remove some code from the backend, allowing the generic code to emit any extra bswaps. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 51 +++++++----------------------------- 2 files changed, 10 insertions(+), 43 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 0788f2eecb..7f55d50400 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,7 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 8edea527f7..34f9347cdf 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1485,8 +1485,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1497,43 +1495,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGMemOp memop, TCGType ext, break; case MO_UW: tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev16(s, data_r, data_r); - } break; case MO_SW: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - tcg_out_rev16(s, data_r, data_r); - tcg_out_sxt(s, ext, MO_16, data_r, data_r); - } else { - tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), + data_r, addr_r, otype, off_r); break; case MO_UL: tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev32(s, data_r, data_r); - } break; case MO_SL: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - tcg_out_rev32(s, data_r, data_r); - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r); - } else { - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); break; case MO_Q: tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev64(s, data_r, data_r); - } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1541,35 +1518,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGMemOp memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); break; case MO_16: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev16(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); break; case MO_32: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev32(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); break; case MO_64: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev64(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1578,6 +1541,8 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { TCGMemOp memop =3D get_memop(oi); =20 + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU /* Ignore the requested "ext". We get the same correct result from * a 16-bit sign-extended to 64-bit as we do sign-extended to 32-bit, @@ -1608,6 +1573,8 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { TCGMemOp memop =3D get_memop(oi); =20 + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU bool is_64 =3D (memop & MO_SIZE) =3D=3D MO_64; =20 --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542986266685755.8429380140997; Fri, 23 Nov 2018 07:17:46 -0800 (PST) Received: from localhost ([::1]:52940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDDB-0004cB-Ed for importer@patchew.org; Fri, 23 Nov 2018 10:17:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj5-0000Hg-FT for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj3-0003jw-KT for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:46584) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj3-0003hc-Ae for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:33 -0500 Received: by mail-wr1-x442.google.com with SMTP id l9so12571118wrt.13 for ; Fri, 23 Nov 2018 06:46:32 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HTYkvsG0udVGuawIRsgNi33ekLoZkN1Kc95kEWex73U=; b=Jv5aw1gXrYHa5lX61lUpc5KKKXaM2RHbriAPo8nuCEwOjAOlNcECbf1i0quYntI08W MXNDmM5SWk/C1O9t1hxlImNKeUJaR/dR+5UnF8anhQgKlP5FyeNt3PVkZ38yl2vwhV57 FG5ZDF1Fvp+u3yMgoHDrzTpBtfhuSsq6lR//k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HTYkvsG0udVGuawIRsgNi33ekLoZkN1Kc95kEWex73U=; b=ZdewyK7zEeW7Gsz5FQPmHKNsyQWGIiBAAZwfNHJsTlJq6YuvXrXBPkNE0cE+pbP3Bv Y8pKCrPBUMSehUXOK1jeT3JuOhsGp8hJJIg+HbPYksHKKGOPvUrHQ/EjysOHAFYaqGab s37IrlBd8IAmwnEX0Q1nW0SPp4viwUTMIjxX8HzsOdHEUvEitLJEI4YH8cSxBZWRB+zI 4Jb/sMgixbAU/gZwHhAlMg/MLuAxq4pQg7sb7xJ75cyyK8lfDUxxo1euvh/adTugyKls RH61PqzQ5OtNlMjJ/WvuKZl+YP6uY68vFkNfMAVJ7w6sqZ2Z1w7zoFWQ6Yy3x1zDalJR duhQ== X-Gm-Message-State: AA+aEWZ9z9A4EqZlpxtOu15oHgH6V8vB6S4FwdX0dE9RVavavS+Kt5Ij 2TS19CmLDm8y19iVCUvsvUCMX9NL9UfM0Q== X-Google-Smtp-Source: AFSGD/WRbSb+aPbAS0dXcA1zrc9HjfX/VzPBp2rrpEB6VmKuHDlkqU0S5/ix2bEZpMBwqH9tmTifzg== X-Received: by 2002:adf:81b6:: with SMTP id 51mr15186676wra.240.1542984391256; Fri, 23 Nov 2018 06:46:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:53 +0100 Message-Id: <20181123144558.5048-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 32/37] tcg/arm: Set TCG_TARGET_HAS_MEMORY_BSWAP to false for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Letting the generic code emit any bswaps allows us to avoid reserving an extra register for CONFIG_USER_ONLY. For SOFTMMU, where we have free call-clobbered registers anyway, leaving the bswap in the out-of-line thunk maximizes code sharing. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/arm/tcg-target.h | 4 ++ tcg/arm/tcg-target.inc.c | 129 +++++++++++++-------------------------- 2 files changed, 48 insertions(+), 85 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 7a4c55d66d..a05310a684 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,7 +131,11 @@ enum { }; =20 #define TCG_TARGET_DEFAULT_MO (0) +#ifdef CONFIG_SOFTMMU #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#else +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#endif =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 5a15f6a546..898701f105 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -270,15 +270,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->u.regs =3D 0xffff; break; =20 - /* qemu_st address & data */ - case 's': - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D 0xffff; - /* r0-r1 doing the byte swapping, so don't use these */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - break; - default: return NULL; } @@ -1363,6 +1354,7 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, TCGMemOp opc, TCGReg addrlo, TCGReg addend) { TCGMemOp bswap =3D opc & MO_BSWAP; + assert(USING_SOFTMMU || !bswap); =20 switch (opc & MO_SSIZE) { case MO_UB: @@ -1386,7 +1378,6 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, TCGMemOp opc, } break; case MO_UL: - default: tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); if (bswap) { tcg_out_bswap32(s, COND_AL, datalo, datalo); @@ -1416,6 +1407,8 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, TCGMemOp opc, } } break; + default: + g_assert_not_reached(); } } =20 @@ -1424,6 +1417,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, TCGMemOp opc, TCGReg addrlo) { TCGMemOp bswap =3D opc & MO_BSWAP; + assert(!USING_SOFTMMU && !bswap); =20 switch (opc & MO_SSIZE) { case MO_UB: @@ -1434,47 +1428,24 @@ static inline void tcg_out_qemu_ld_direct(TCGContex= t *s, TCGMemOp opc, break; case MO_UW: tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } break; case MO_SW: - if (bswap) { - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); break; case MO_UL: - default: tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } break; case MO_Q: - { - TCGReg dl =3D (bswap ? datahi : datalo); - TCGReg dh =3D (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) =3D=3D 0 && dh =3D=3D dl + 1) { - tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0); - } else if (dl =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - } else { - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } + if (datalo =3D=3D addrlo) { + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + } else { + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1485,19 +1456,18 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) TCGReg datalo __attribute__((unused)); TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; =20 datalo =3D *args++; datahi =3D (is64 ? *args++ : 0); addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; - opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU add_ldst_ool_label(s, true, is64, oi, R_ARM_PC24, 0); tcg_out_bl_noaddr(s, COND_AL); #else + TCGMemOp opc =3D get_memop(oi); if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); @@ -1512,6 +1482,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *= s, int cond, TCGMemOp opc, TCGReg addrlo, TCGReg addend) { TCGMemOp bswap =3D opc & MO_BSWAP; + assert(USING_SOFTMMU || !bswap); =20 switch (opc & MO_SIZE) { case MO_8: @@ -1526,7 +1497,6 @@ static inline void tcg_out_qemu_st_index(TCGContext *= s, int cond, TCGMemOp opc, } break; case MO_32: - default: if (bswap) { tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend); @@ -1535,20 +1505,32 @@ static inline void tcg_out_qemu_st_index(TCGContext= *s, int cond, TCGMemOp opc, } break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datahi); - tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo); - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + /* + * Assert inputs are where I think, for the softmmu thunk. + * One pair of R0/R1 or R2/R3 will be free and call-clobbered, + * which allows the use of STRD below. Note the bswaps also + * reverse the lo/hi registers to swap the two words. + */ + tcg_debug_assert(addend =3D=3D TCG_REG_TMP); + tcg_debug_assert(datalo =3D=3D TCG_REG_R4); + tcg_debug_assert(datahi =3D=3D TCG_REG_R5); + datalo =3D addrlo =3D=3D TCG_REG_R1 ? TCG_REG_R2 : TCG_REG_R0; + datahi =3D datalo + 1; + tcg_out_bswap32(s, cond, datalo, TCG_REG_R5); + tcg_out_bswap32(s, cond, datahi, TCG_REG_R4); + } + /* Avoid strd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); tcg_out_st32_12(s, cond, datahi, addend, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1557,43 +1539,25 @@ static inline void tcg_out_qemu_st_direct(TCGContex= t *s, TCGMemOp opc, TCGReg addrlo) { TCGMemOp bswap =3D opc & MO_BSWAP; + assert(!USING_SOFTMMU && !bswap); =20 switch (opc & MO_SIZE) { case MO_8: tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); break; case MO_16: - if (bswap) { - tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); break; case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); - } + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); break; + default: + g_assert_not_reached(); } } =20 @@ -1604,19 +1568,18 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) TCGReg datalo __attribute__((unused)); TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; =20 datalo =3D *args++; datahi =3D (is64 ? *args++ : 0); addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; - opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU add_ldst_ool_label(s, false, is64, oi, R_ARM_PC24, 0); tcg_out_bl_noaddr(s, COND_AL); #else + TCGMemOp opc =3D get_memop(oi); if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_st_index(s, COND_AL, opc, datalo, @@ -2055,11 +2018,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) { static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; - static const TCGTargetOpDef s_s =3D { .args_ct_str =3D { "s", "s" } }; static const TCGTargetOpDef a_b =3D { .args_ct_str =3D { "a", "b" } }; static const TCGTargetOpDef c_b =3D { .args_ct_str =3D { "c", "b" } }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; - static const TCGTargetOpDef s_s_s =3D { .args_ct_str =3D { "s", "s", "= s" } }; static const TCGTargetOpDef a_c_d =3D { .args_ct_str =3D { "a", "c", "= d" } }; static const TCGTargetOpDef a_b_b =3D { .args_ct_str =3D { "a", "b", "= b" } }; static const TCGTargetOpDef e_c_d =3D { .args_ct_str =3D { "e", "c", "= d" } }; @@ -2072,8 +2033,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "r", "r", "rIK" } }; static const TCGTargetOpDef r_r_r_r =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; - static const TCGTargetOpDef s_s_s_s - =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; static const TCGTargetOpDef a_b_c_d =3D { .args_ct_str =3D { "a", "b", "c", "d" } }; static const TCGTargetOpDef e_f_c_d @@ -2175,7 +2134,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) } case INDEX_op_qemu_st_i32: if (!USING_SOFTMMU) { - return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? &r_r : &r_r_r; } else if (TARGET_LONG_BITS =3D=3D 32) { return &c_b; /* temps available r0, r3, r12 */ } else { @@ -2183,7 +2142,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) } case INDEX_op_qemu_st_i64: if (!USING_SOFTMMU) { - return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS =3D=3D 32 ? &r_r_r : &r_r_r_r; } else if (TARGET_LONG_BITS =3D=3D 32) { return &e_f_b; /* temps available r0, r2, r3, r12 */ } else { --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542986277141125.83583216020304; Fri, 23 Nov 2018 07:17:57 -0800 (PST) Received: from localhost ([::1]:52941 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDDP-0004mn-Sj for importer@patchew.org; Fri, 23 Nov 2018 10:17:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj6-0000Hj-RR for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj4-0003lo-Su for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:32861) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj4-0003iu-Ki for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: by mail-wr1-x441.google.com with SMTP id c14so6956475wrr.0 for ; Fri, 23 Nov 2018 06:46:33 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ftMZ3fz35dYKoMc8uTCKp7fh8kUWUt+B2yZR69ArZfM=; b=C0BGPmG6ZXBTup7b6ZlFpG2gESXyr8l9FLstYIP3caLxWVWfHSORxi2HxlHukoBBPZ nO9PZm+GlHFTkbaHzi8H8/xDaOY9kzlCpZeARg4JlNQHG5VQHEvBD75FWesXxJHMYb3a AXjqKLRSMpONusJU1PlZXBwcvMeQXeyqkj3YM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ftMZ3fz35dYKoMc8uTCKp7fh8kUWUt+B2yZR69ArZfM=; b=kL+YF60s8HhqVFVG63A2xMq+tr/dQQrYgBVZBiUu+u9EWaCOt3GIUtpKxTwz63FmzJ gABFqo7O80sffTFIBCsdnTHtzG1PPgGs8Bb86bZBHNMtfos30WlbI+iSMqLO7TtOKhBX q/ti3oPKeqgpBfuZ05wKPTo/fnuNI6P2YadgG11q1vsi+x/0EPNwxo3bcYBiPQ2DzD1G xCUfhBi+LaaEUxZTCihQWYKLMSalO15/fwiMl+Oin3UdPPxNlVg03xXbi5mL8veu6w08 S6t1mJFKrpHe2N3VCsOOC51liXqgEIWvi15ejHg61hV2KioP+4yP1uhxqhNw/vBn+1G3 BZCQ== X-Gm-Message-State: AA+aEWYPCssV25770aJmpPDqwYYisVAh4aWHAg5DNTPe1PsiAX/a/9xg d82rkg0srbh1Oz1eXywG2wtRiT+jRT2J4g== X-Google-Smtp-Source: AFSGD/W1PBlUOD1EbxlwkuznlBgjop3RHaDn2aSx9eWUCUZ97gcn811ZzkpcDxcA8v2D0BIV0tuCRQ== X-Received: by 2002:adf:c888:: with SMTP id k8mr15339977wrh.6.1542984392410; Fri, 23 Nov 2018 06:46:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:54 +0100 Message-Id: <20181123144558.5048-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.0 v2 33/37] tcg/i386: Propagate is64 to tcg_out_qemu_ld_direct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This can save a few rex prefixes for qemu_ld_i32. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 76235e90c9..5cad31cfe5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1815,10 +1815,11 @@ static inline void setup_guest_base_seg(void) { } =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) + int seg, bool is64, TCGMemOp memop) { bool use_bswap =3D memop & MO_BSWAP; bool use_movbe =3D false; + int rexw =3D is64 * P_REXW; int movop =3D OPC_MOVL_GvEv; =20 /* @@ -1843,7 +1844,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, base, index, 0, ofs); break; case MO_UW: @@ -1871,14 +1872,15 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, if (use_movbe) { tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); - tcg_out_ext16s(s, datalo, datalo, P_REXW); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, + tcg_out_ext16s(s, datalo, datalo, rexw); + } else if (use_bswap) { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + seg, + datalo, base, index, 0, ofs); + tcg_out_rolw_8(s, datalo); + tcg_out_ext16s(s, datalo, datalo, rexw); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); - if (use_bswap) { - tcg_out_rolw_8(s, datalo); - tcg_out_ext16s(s, datalo, datalo, P_REXW); - } } break; case MO_UL: @@ -2004,7 +2006,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, opc); + base, index, offset, seg, is64, opc); } #endif } @@ -2202,7 +2204,7 @@ static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContex= t *s, bool is_ld, =20 /* TLB Hit. */ if (is_ld) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, is_64, o= pc); } else { tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); } --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985979151612.7492612950218; Fri, 23 Nov 2018 07:12:59 -0800 (PST) Received: from localhost ([::1]:52903 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD8Q-0000Bg-Q0 for importer@patchew.org; Fri, 23 Nov 2018 10:12:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj6-0000Hi-RH for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 34/37] tcg/i386: Restrict user-only qemu_st_i32 values to q-regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5cad31cfe5..79de8d0cd2 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,7 +240,17 @@ static const char *constrain_memop_arg(QemuMemArgType = type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, in= t hi) { - return "L"; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* Temps are still needed for guest_base && !guest_base_flags. */ + return "L"; + } else if (type =3D=3D ARG_STVAL && !is_64) { + /* Byte stores must happen from q-regs. Because of this, we must + * constrain all INDEX_op_qemu_st_i32 to use q-regs. + */ + return "q"; + } else { + return "r"; + } } #endif /* CONFIG_SOFTMMU */ =20 @@ -2038,15 +2048,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TC= GReg datalo, TCGReg datahi, =20 switch (memop & MO_SIZE) { case MO_8: - /* - * In 32-bit mode, 8-bit stores can only happen from [abcd]x. - * ??? Adjust constraints such that this is is forced, then - * we won't need a scratch at all for user-only. - */ - if (TCG_TARGET_REG_BITS =3D=3D 32 && datalo >=3D 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo =3D scratch; - } + /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. */ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || datalo < 4); tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, ofs); break; --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542985947166455.50103415469493; Fri, 23 Nov 2018 07:12:27 -0800 (PST) Received: from localhost ([::1]:52900 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD7z-0008J4-VJ for importer@patchew.org; Fri, 23 Nov 2018 10:12:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LQ-CR for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj5-0003nL-O8 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:36618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj5-0003ly-HF for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: by mail-wr1-x444.google.com with SMTP id t3so12596704wrr.3 for ; Fri, 23 Nov 2018 06:46:35 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pjRtmlyYSb1VLkGjhaHARmsTCgNRA8M6YYDKvLblOwM=; b=IW95SJNHj/hYK6QwjfgzZrgLVDyCnmkfrgdwyb1qV6tFKdoc7v7BTc9HQ18wWPxIAA WFFyKf3DyV1uRZrEFzQTBpc8kALNMWyqWIe3lcYq1vzktTPISxiIKXaoOESKjo/Ufgqn p70MHi3Eg18+IQN24sSrTZ3OzIXC6rP89RbYk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pjRtmlyYSb1VLkGjhaHARmsTCgNRA8M6YYDKvLblOwM=; b=FHeOHzNfgxMYDMxKBkd43VRwfgYlw72H/qlnCSdT+PG9CRWWmD0T5fyz4WVAl4GPD9 vUhf1qEawwnDpMQVBv/R54slFeDbny+t+sm143ZeQ3Q44pjOdiAV76h+/H0YfkXI9w/z lAlTKBSxvHyMF2yONJYNFa2Q3D6YgYeJFXt4VGS16xLxGBuOxh6HzyU8L8CjzC5G3xNU nlwbStzlCaRhp+mPAa8l7bhMX4m4StvDsPMZ43ZKB8Eylcudnv3o5DQ2t16Bndh7qxtZ m7c1/XCP6tkMCqJK9gfR4d1rwgrOt5vh2qFpuDWweXjouEwIGbjBmomJel8Mk2Mbek+m XuPA== X-Gm-Message-State: AA+aEWY2lO8vc7DWGMRxwwptmrDzIslWDgEqHWV+9FDHzxgI8J4fRJRB uG7zW4IYkj9UgJf7Q+RHdHvam9tUNYZCsA== X-Google-Smtp-Source: AFSGD/X+CuF6XnjsM+It2jZlzY17ZzbXj3ew2hjyBnLwxb1cJY3cIMXgDhNsgw14rW1dMNVhcTOWww== X-Received: by 2002:adf:b30f:: with SMTP id j15mr11189970wrd.46.1542984394121; Fri, 23 Nov 2018 06:46:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:56 +0100 Message-Id: <20181123144558.5048-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 35/37] tcg/i386: Add setup_guest_base_seg for FreeBSD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 79de8d0cd2..55c5a8516c 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1818,6 +1818,16 @@ static inline void setup_guest_base_seg(void) guest_base_flags =3D P_GS; } } +#elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) +# include + +static int guest_base_flags; +static inline void setup_guest_base_seg(void) +{ + if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { + guest_base_flags =3D P_GS; + } +} #else # define guest_base_flags 0 static inline void setup_guest_base_seg(void) { } --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542986116870556.8139063191821; Fri, 23 Nov 2018 07:15:16 -0800 (PST) Received: from localhost ([::1]:52923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDAi-0002WE-Hh for importer@patchew.org; Fri, 23 Nov 2018 10:15:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LT-Cq for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj6-0003pH-MU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj6-0003nu-GY for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:36 -0500 Received: by mail-wm1-x341.google.com with SMTP id 125so12200616wmh.0 for ; Fri, 23 Nov 2018 06:46:36 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=hP4OZGZei8NzZOZZq4OPeDcY7xKz+fnV+V8ZUI2IFJgMMxQFCl4aFt9+Pnk1jN+5MM 9edwPiTSgUfUZGbPjy2UrxpDXuvsaePSOoN0zWCOUD6jRBEWBqg1qB//ha+8tw3KlxJ2 sfaaf91mDBLV1b6+1maMx1N1hIObKag3EF/3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=J0VTvWygSs60QWMc8E6WKNqTvoNEX0tQuhDRghUyWgRfP/FvO53JdZv1PQFeRx2Gtl fb43jd9XkgpZb+R2S3KfeuRGSOJzWPbTyM3kF0kbgGp8PueCPJLkSzLyczbV5V7ipET9 3vUBRk5d3c8xNdgnITmXXRVrjvsOw8nE8cHuPG6MZqF83zHac/4okp4YdF9Di7ebfSvC f6PysLl3K3IljhUhX0lqEyMHPVZny/U7dMqhwilr/xuzFlchGry1wVDRa41U0+r45mby lkv3DIT8HX4p69JtDKn78O+UHlJEOAi9N5AsDcxWDpEoV3iHhJntY0Z/QL0UsSuRj3Wa Uc1g== X-Gm-Message-State: AGRZ1gLNVYAUvGzFFB5mpKvue/AsyGXkcHCqiBeUUR/z9dAWk82Cnsyp jvmwGoxK9eSnC6ucsDIht05B1O2tBnp/lg== X-Google-Smtp-Source: AJdET5d19jgvg6HyHKMTk1pQ22Yr4SFKQP2vVY5L0hUTZJj64vucTz7pPVFG0RZvgNkoaE8CRQeyWQ== X-Received: by 2002:a1c:a754:: with SMTP id q81mr13200585wme.132.1542984395154; Fri, 23 Nov 2018 06:46:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:57 +0100 Message-Id: <20181123144558.5048-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 36/37] tcg/i386: Require segment syscalls to succeed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There ought be no reason they should ever fail. If we don't know how to set a segment base register for user-only (NetBSD, OpenBSD?), then error out if we cannot proceed. This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 54 +++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 55c5a8516c..19a0fa8a03 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1814,9 +1814,12 @@ int arch_prctl(int code, unsigned long addr); static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (arch_prctl(ARCH_SET_GS, guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + /* There is no reason this syscall should fail. */ + if (arch_prctl(ARCH_SET_GS, guest_base) < 0) { + perror("arch_prctl(ARCH_SET_GS)"); + exit(1); } + guest_base_flags =3D P_GS; } #elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) # include @@ -1824,13 +1827,28 @@ static inline void setup_guest_base_seg(void) static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { - guest_base_flags =3D P_GS; + /* There is no reason this syscall should fail. */ + if (sysarch(AMD64_SET_GSBASE, &guest_base) < 0) { + perror("sysarch(AMD64_SET_GSBASE)"); + exit(1); } + guest_base_flags =3D P_GS; } #else # define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +static inline void setup_guest_base_seg(void) +{ + /* + * Verify we can proceed without scratch registers. + * If guest_base > INT32_MAX, then it would need to be loaded. + * If 32-bit guest, the address would need to be zero-extended. + */ + if (TCG_TARGET_REG_BITS =3D=3D 64 + && (TARGET_LONG_BITS =3D=3D 32 || guest_base > INT32_MAX)) { + error_report("Segment base register not supported on this OS"); + exit(1); + } +} #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2013,16 +2031,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |=3D P_ADDR32; } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - if (offset !=3D guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index =3D TCG_REG_L1; - offset =3D 0; - } } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, @@ -2156,22 +2164,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |=3D P_ADDR32; } - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset !=3D guest_base) { - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base =3D TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base =3D TCG_REG_L1; - offset =3D 0; - } else if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base =3D TCG_REG_L1; - } } =20 tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); --=20 2.17.2 From nobody Sat May 4 10:23:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154298641419598.86734848202013; Fri, 23 Nov 2018 07:20:14 -0800 (PST) Received: from localhost ([::1]:52955 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQDFY-0007R8-MT for importer@patchew.org; Fri, 23 Nov 2018 10:20:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LP-CM for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj7-0003qN-F9 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj7-0003pL-9N for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:37 -0500 Received: by mail-wr1-x444.google.com with SMTP id v13so9118649wrw.5 for ; Fri, 23 Nov 2018 06:46:37 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b79TMT1xsQ1kNxl+TOgvq76GlDxOHE/SHes3qAZINQQ=; b=XDdC8TkT/H6QSB8JQTTABNVFnIRdHU/W7JMCrNR4qkXUMIa8UpH3PsijCoG1S5idE+ /0Tf9y8QVrTvp7Kvfgr15KZBZm9RM05aoCln5X+Cbvlnt1RKh4WgWfNzHYkq4pJTTTBx RnRH9R2fcOziWeWBWtwJhBObgDr0uRjBQykyI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b79TMT1xsQ1kNxl+TOgvq76GlDxOHE/SHes3qAZINQQ=; b=ATmlztqKhW6ZLUWBjTN0CLoNfB6nZfAL9h/bDQVDaUCZ0wS+9zlht3N4ehrG4z4Hmk 8+BALXe6TxLXd1p8DjJ/wD4DOKIG+D9NNhRzGhR6+PUlrIzZigzp/jV3GUgtMdRpJ7hY Lyv0rpA8aBO1jFYb96R/Q66YMuumdSIv6GoxqMm5PtniFnwuJ/iZpgFnp5OIYJTz0p4a hvARk1JK2c5dNsur1+OLci5CoEBKd5qhuoEeQiMTFmzAoTVdh1tClUffBEdcdje2A9eU qX07+qeP9Vr7PEYbDb+c7jQEzT5A+zMWP/GhkK7hjQ7lRvL5+DphCn+lra6x0VyC/K+R 7w9Q== X-Gm-Message-State: AA+aEWaRMAwVWnb0rm1BwRZjk7TmCcnrQndQ8g/Tp6q5XvpO/H/ONtg6 lJ3p4K7iYA82QucrvbwvxiIHAWWEwD2v8A== X-Google-Smtp-Source: AFSGD/Vb0Cery1yViGLHjinkfHZ4NY3c3a+LrCSoSOm/u2THctaJ8y39pDmM4fIk1nl5c/FHNKHtZA== X-Received: by 2002:a5d:46c2:: with SMTP id g2mr14796626wrs.49.1542984396072; Fri, 23 Nov 2018 06:46:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:58 +0100 Message-Id: <20181123144558.5048-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 37/37] tcg/i386: Remove L constraint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We no longer need any scratch registers for user-only memory ops. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 19a0fa8a03..2815dd25a0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,10 +240,7 @@ static const char *constrain_memop_arg(QemuMemArgType = type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, in= t hi) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Temps are still needed for guest_base && !guest_base_flags. */ - return "L"; - } else if (type =3D=3D ARG_STVAL && !is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D ARG_STVAL && !is_64) { /* Byte stores must happen from q-regs. Because of this, we must * constrain all INDEX_op_qemu_st_i32 to use q-regs. */ @@ -353,14 +350,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->u.regs |=3D ALL_VECTOR_REGS; break; =20 - /* qemu_ld/st address constraint */ - case 'L': - ct->ct |=3D TCG_CT_REG; - ct->u.regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - break; - case 'e': ct->ct |=3D (type =3D=3D TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONS= T_S32); break; --=20 2.17.2