From nobody Wed May 1 16:17:50 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542893838888770.8017615645143; Thu, 22 Nov 2018 05:37:18 -0800 (PST) Received: from localhost ([::1]:46620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPpAE-0000B0-Sd for importer@patchew.org; Thu, 22 Nov 2018 08:37:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPp8c-0007vU-7p for qemu-devel@nongnu.org; Thu, 22 Nov 2018 08:35:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPp8a-0001hP-6s for qemu-devel@nongnu.org; Thu, 22 Nov 2018 08:35:22 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52746) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gPp8W-0001bx-An; Thu, 22 Nov 2018 08:35:16 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gPp8Q-0005AS-US; Thu, 22 Nov 2018 13:35:10 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 22 Nov 2018 13:35:06 +0000 Message-Id: <20181122133507.30950-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122133507.30950-1-peter.maydell@linaro.org> References: <20181122133507.30950-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-4.0 1/2] exec.c: Rename cpu_physical_memory_write_rom_internal() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , Richard Henderson , patches@linaro.org, Mark Cave-Ayland , Paolo Bonzini , Artyom Tarasenko Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Rename cpu_physical_memory_write_rom_internal() to address_space_write_rom_internal(), and make it take MemTxAttrs and return a MemTxResult. This brings its API into line with address_space_write(). This is an internal function to exec.c; fixing its API will allow us to change the global function cpu_physical_memory_write_rom(). Signed-off-by: Peter Maydell Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- exec.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/exec.c b/exec.c index bb6170dbffe..92679508ba3 100644 --- a/exec.c +++ b/exec.c @@ -3388,8 +3388,12 @@ enum write_rom_type { FLUSH_CACHE, }; =20 -static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, - hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) +static inline MemTxResult address_space_write_rom_internal(AddressSpace *a= s, + hwaddr addr, + MemTxAttrs attr= s, + const uint8_t *= buf, + int len, + enum write_rom_= type type) { hwaddr l; uint8_t *ptr; @@ -3399,8 +3403,7 @@ static inline void cpu_physical_memory_write_rom_inte= rnal(AddressSpace *as, rcu_read_lock(); while (len > 0) { l =3D len; - mr =3D address_space_translate(as, addr, &addr1, &l, true, - MEMTXATTRS_UNSPECIFIED); + mr =3D address_space_translate(as, addr, &addr1, &l, true, attrs); =20 if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { @@ -3423,13 +3426,15 @@ static inline void cpu_physical_memory_write_rom_in= ternal(AddressSpace *as, addr +=3D l; } rcu_read_unlock(); + return MEMTX_OK; } =20 /* used for ROM loading : can write in RAM and ROM */ void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, const uint8_t *buf, int len) { - cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); + address_space_write_rom_internal(as, addr, MEMTXATTRS_UNSPECIFIED, + buf, len, WRITE_DATA); } =20 void cpu_flush_icache_range(hwaddr start, int len) @@ -3444,8 +3449,9 @@ void cpu_flush_icache_range(hwaddr start, int len) return; } =20 - cpu_physical_memory_write_rom_internal(&address_space_memory, - start, NULL, len, FLUSH_CACHE); + address_space_write_rom_internal(&address_space_memory, + start, MEMTXATTRS_UNSPECIFIED, + NULL, len, FLUSH_CACHE); } =20 typedef struct { --=20 2.19.1 From nobody Wed May 1 16:17:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154289519076919.46889100279259; Thu, 22 Nov 2018 05:59:50 -0800 (PST) Received: from localhost ([::1]:46749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPpW9-0001GL-Tw for importer@patchew.org; Thu, 22 Nov 2018 08:59:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPpV8-0000qw-Jx for qemu-devel@nongnu.org; Thu, 22 Nov 2018 08:58:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPpV6-000740-RU for qemu-devel@nongnu.org; Thu, 22 Nov 2018 08:58:38 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gPpV2-0006wi-NK; Thu, 22 Nov 2018 08:58:32 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gPp8R-0005Ak-Rx; Thu, 22 Nov 2018 13:35:11 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 22 Nov 2018 13:35:07 +0000 Message-Id: <20181122133507.30950-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122133507.30950-1-peter.maydell@linaro.org> References: <20181122133507.30950-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-4.0 2/2] Rename cpu_physical_memory_write_rom() to address_space_write_rom() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , Richard Henderson , patches@linaro.org, Mark Cave-Ayland , Paolo Bonzini , Artyom Tarasenko Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The API of cpu_physical_memory_write_rom() is odd, because it takes an AddressSpace, unlike all the other cpu_physical_memory_* access functions. Rename it to address_space_write_rom(), and bring its API into line with address_space_write(). Signed-off-by: Peter Maydell Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-common.h | 2 -- include/exec/memory.h | 26 ++++++++++++++++++++++++++ exec.c | 14 ++++++++------ hw/core/loader.c | 4 ++-- hw/intc/apic.c | 7 ++++--- hw/misc/tz-mpc.c | 2 +- hw/sparc/sun4m.c | 5 +++-- docs/devel/loads-stores.rst | 35 ++++++++++++++++------------------- 8 files changed, 60 insertions(+), 35 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 18b40d6145c..2ad2d6d86bb 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -111,8 +111,6 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr); */ void qemu_flush_coalesced_mmio_buffer(void); =20 -void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len); void cpu_flush_icache_range(hwaddr start, int len); =20 extern struct MemoryRegion io_mem_rom; diff --git a/include/exec/memory.h b/include/exec/memory.h index 8e61450de32..ffd23ed8d8d 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1792,6 +1792,32 @@ MemTxResult address_space_write(AddressSpace *as, hw= addr addr, MemTxAttrs attrs, const uint8_t *buf, int len); =20 +/** + * address_space_write_rom: write to address space, including ROM. + * + * This function writes to the specified address space, but will + * write data to both ROM and RAM. This is used for non-guest + * writes like writes from the gdb debug stub or initial loading + * of ROM contents. + * + * Note that portions of the write which attempt to write data to + * a device will be silently ignored -- only real RAM and ROM will + * be written to. + * + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). + * + * @as: #AddressSpace to be accessed + * @addr: address within that address space + * @attrs: memory transaction attributes + * @buf: buffer with the data transferred + * @len: the number of bytes to write + */ +MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + const uint8_t *buf, int len); + /* address_space_ld*: load from an address space * address_space_st*: store to an address space * diff --git a/exec.c b/exec.c index 92679508ba3..6e875f0640a 100644 --- a/exec.c +++ b/exec.c @@ -3430,11 +3430,12 @@ static inline MemTxResult address_space_write_rom_i= nternal(AddressSpace *as, } =20 /* used for ROM loading : can write in RAM and ROM */ -void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len) +MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + const uint8_t *buf, int len) { - address_space_write_rom_internal(as, addr, MEMTXATTRS_UNSPECIFIED, - buf, len, WRITE_DATA); + return address_space_write_rom_internal(as, addr, attrs, + buf, len, WRITE_DATA); } =20 void cpu_flush_icache_range(hwaddr start, int len) @@ -3879,8 +3880,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong a= ddr, l =3D len; phys_addr +=3D (addr & ~TARGET_PAGE_MASK); if (is_write) { - cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, - phys_addr, buf, l); + address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, + MEMTXATTRS_UNSPECIFIED, + buf, l); } else { address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, MEMTXATTRS_UNSPECIFIED, diff --git a/hw/core/loader.c b/hw/core/loader.c index aa0b3fc8679..66a616608af 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1103,8 +1103,8 @@ static void rom_reset(void *unused) void *host =3D memory_region_get_ram_ptr(rom->mr); memcpy(host, rom->data, rom->datasize); } else { - cpu_physical_memory_write_rom(rom->as, rom->addr, rom->data, - rom->datasize); + address_space_write_rom(rom->as, rom->addr, MEMTXATTRS_UNSPECI= FIED, + rom->data, rom->datasize); } if (rom->isrom) { /* rom needs to be written only once */ diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 97ffdd820f2..c9dd65b3a03 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -122,9 +122,10 @@ static void apic_sync_vapic(APICCommonState *s, int sy= nc_type) } vapic_state.irr =3D vector & 0xff; =20 - cpu_physical_memory_write_rom(&address_space_memory, - s->vapic_paddr + start, - ((void *)&vapic_state) + start, leng= th); + address_space_write_rom(&address_space_memory, + s->vapic_paddr + start, + MEMTXATTRS_UNSPECIFIED, + ((void *)&vapic_state) + start, length); } } =20 diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index e0c58ba37ec..fb48a1540b9 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -448,7 +448,7 @@ static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iom= mu, MemTxAttrs attrs) { /* We treat unspecified attributes like secure. Transactions with * unspecified attributes come from places like - * cpu_physical_memory_write_rom() for initial image load, and we want + * rom_reset() for initial image load, and we want * those to pass through the from-reset "everything is secure" config. * All the real during-emulation transactions from the CPU will * specify attributes. diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 3c29b68e67f..639906cca30 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -559,8 +559,9 @@ static void idreg_init(hwaddr addr) s =3D SYS_BUS_DEVICE(dev); =20 sysbus_mmio_map(s, 0, addr); - cpu_physical_memory_write_rom(&address_space_memory, - addr, idreg_data, sizeof(idreg_data)); + address_space_write_rom(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, + idreg_data, sizeof(idreg_data)); } =20 #define MACIO_ID_REGISTER(obj) \ diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index 57d8c524bfe..c74cd090e64 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -253,6 +253,22 @@ Regexes for git grep - ``\`` - ``\`` =20 +``address_space_write_rom`` +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This function performs a write by physical address like +``address_space_write``, except that if the write is to a ROM then +the ROM contents will be modified, even though a write by the guest +CPU to the ROM would be ignored. This is used for non-guest writes +like writes from the gdb debug stub or initial loading of ROM contents. + +Note that portions of the write which attempt to write data to a +device will be silently ignored -- only real RAM and ROM will +be written to. + +Regexes for git grep + - ``address_space_write_rom`` + ``{ld,st}*_phys`` ~~~~~~~~~~~~~~~~~ =20 @@ -315,25 +331,6 @@ For new code they are better avoided: Regexes for git grep - ``\`` =20 -``cpu_physical_memory_write_rom`` -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -This function performs a write by physical address like -``address_space_write``, except that if the write is to a ROM then -the ROM contents will be modified, even though a write by the guest -CPU to the ROM would be ignored. - -Note that unlike ``cpu_physical_memory_write()`` this function takes -an AddressSpace argument, but unlike ``address_space_write()`` this -function does not take a ``MemTxAttrs`` or return a ``MemTxResult``. - -**TODO**: we should probably clean up this inconsistency and -turn the function into ``address_space_write_rom`` with an API -matching ``address_space_write``. - -``cpu_physical_memory_write_rom`` - - ``cpu_memory_rw_debug`` ~~~~~~~~~~~~~~~~~~~~~~~ =20 --=20 2.19.1